JP2007027377A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of semiconductor device for transferring and forming a wiring layer on a temporary substrate on a semiconductor substrate without generation of any defect, and for stably removing the temporary substrate from the semiconductor substrate. <P>SOLUTION: An ultraviolet ray irradiation peeling type bonding layer 12 is formed on the temporary substrate 10, and a wiring layer 3 provided with a connecting part 26 at the highest part is formed on the ultraviolet ray irradiation peeling type bonding layer 12. Thereafter, the connecting part 26 of a wiring layer 3 on the temporary substrate 10 is joined with a connecting part 38 of the semiconductor substrate 30 where a semiconductor circuit is formed. Moreover, the ultraviolet ray irradiation peeling type bonding layer 12 and the temporary substrate 10 are peeled for removal by radiating the ultraviolet ray to the ultraviolet ray irradiation peeling type bonding layer 12 from the side of temporary substrate 10. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device applicable to manufacturing a wafer level package in which a CSP (chip size package) process is performed on a wafer.

  In recent years, LSI technology, which is a key technology for realizing multimedia devices, has been steadily developed for higher data transmission speed and capacity. Along with this, the density of packaging technology that serves as an interface between LSI and electronic devices is being increased.

  As an IC package that meets such requirements, a CSP packaged in a size substantially equal to the chip size is known. Further, a wafer level CSP is known in which film formation and processing related to the CSP structure are performed at the wafer stage, and then dicing is performed to obtain individual CSPs.

  In the wafer level CSP, after a necessary rewiring layer and connection terminals are formed on connection pads of a silicon wafer on which a semiconductor circuit is formed, the silicon wafer is diced to obtain individual CSPs.

  However, in the above-described wafer level CSP manufacturing method, since the rewiring layer and the connection terminal are directly formed on the silicon wafer on which the semiconductor circuit is formed, a process that damages the semiconductor circuit cannot be performed. The method may be restricted. Further, when the silicon wafer is thinned to reduce the package thickness and the strength is reduced, handling in the rewiring process becomes difficult.

Therefore, a wiring layer is formed on a temporary substrate different from the silicon wafer, the wiring layer on the temporary substrate is bonded to the connection pad of the silicon wafer, and then the temporary substrate is selectively removed to thereby remove the silicon wafer. There has been proposed a method for transferring and forming a wiring layer thereon. Techniques similar to such a method are described in Patent Documents 1 to 3.
JP 2002-76576 A JP 2002-231855 A JP 2004-63808 A

  However, the technique for bonding the wiring layer formed on the temporary substrate to the connection portion of the silicon wafer with high accuracy and stably removing the temporary substrate from the silicon wafer is not sufficiently established. There is an aspirational situation for such technology.

  The present invention was created in view of the above problems, and without causing any problems, the wiring layer on the temporary substrate can be accurately transferred and formed on the semiconductor substrate, and the temporary substrate can be stabilized from the semiconductor substrate. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can be removed in this manner.

  In order to solve the above-described problems, the present invention relates to a method for manufacturing a semiconductor device, and includes a step of forming an ultraviolet irradiation peelable adhesive layer on a temporary substrate, and an uppermost connection portion on the ultraviolet radiation peelable adhesive layer. A step of forming a required wiring layer comprising: a step of bonding the connection portion of the wiring layer on the temporary substrate and a connection portion of a semiconductor substrate on which a semiconductor circuit is formed; A step of peeling and removing the ultraviolet irradiation peelable adhesive layer and the temporary substrate by irradiating the ultraviolet radiation peelable adhesive layer with ultraviolet rays.

In the present invention, first, a required wiring layer having a connection portion at the top is formed on a temporary substrate (glass or resin) through which ultraviolet rays are transmitted via an ultraviolet ray irradiation peelable adhesive layer. Thereafter, the connection portion of the temporary substrate is bonded to the connection portion of the semiconductor substrate (such as a silicon wafer) on which the semiconductor circuit is formed.
Further, the ultraviolet irradiation peelable adhesive layer is irradiated with ultraviolet rays from the temporary substrate side, and the adhesive strength of the ultraviolet irradiation peelable adhesive layer is reduced, whereby the ultraviolet irradiation peelable adhesive layer and the temporary substrate are peeled and removed.

  In the present invention, when transferring and forming a wiring layer on a temporary substrate onto a semiconductor substrate, an ultraviolet irradiation peelable adhesive layer having a characteristic that the adhesive strength is reduced by ultraviolet irradiation as a release layer for removing an unnecessary temporary substrate. Is used. For this reason, since the temporary substrate can be easily removed by irradiating the ultraviolet irradiation peelable adhesive layer with an ultraviolet ray in an arbitrary process, a rewiring layer can be easily formed on the semiconductor substrate by a transfer technique. become able to.

  In addition, since a temporary substrate (for example, glass or resin) that transmits ultraviolet rays can be selected to approximate the thermal expansion coefficient of a semiconductor substrate (for example, silicon), the connection portion of the temporary substrate is bonded to the connection portion of the semiconductor substrate. Generation of thermal stress can be suppressed. Therefore, the connection part of the temporary substrate and the connection part of the semiconductor substrate can be bonded with high reliability without causing positional displacement.

  In addition, since a method of transferring the wiring layer formed on the temporary substrate to the semiconductor substrate is adopted, even a technique (for example, laser) that adversely affects the semiconductor circuit of the semiconductor substrate in the step of forming the wiring layer should be used. The manufacturing method is not limited.

  In a preferred aspect of the present invention, the step of forming the wiring layer includes the step of forming the external connection terminal pad in the opening of the first resin layer provided on the ultraviolet radiation peelable adhesive layer; Forming a wiring part electrically connected to the external connection terminal pad on the first resin layer; and covering a part of the wiring part and providing an opening on the wiring part. Forming the connecting portion in the opening of the two resin layers.

  In this aspect, the wiring layer formed on the temporary substrate is provided with the external connection terminal pads at the bottom, and the exposed external connection terminal pads are removed after the temporary substrate and the ultraviolet irradiation peelable adhesive layer are removed. External connection terminals are provided.

  As described above, according to the present invention, the wiring layer formed on the temporary substrate can be transferred and formed on the semiconductor substrate without causing any problems.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

(First embodiment)
1 to 5 are sectional views showing a method for manufacturing a semiconductor device according to the first embodiment of the present invention. FIGS. 6 and 7 are sectional views showing a method for forming bumps on a silicon wafer. In the method for manufacturing a semiconductor device according to the first embodiment, as shown in FIG. 1A, first, a temporary substrate 10 having characteristics of transmitting ultraviolet rays (UV) is prepared. Examples of such a temporary substrate 10 include borosilicate glass, silica glass, acrylic resin, or polytetrafluoroethylene (Teflon (registered trademark)) resin that transmits ultraviolet light having a wavelength of 200 to 450 nm. Its thickness is 0.5-1 mm.

  Thereafter, as shown in FIG. 1B, an ultraviolet irradiation peelable adhesive layer 12 is formed on the temporary substrate 10. The ultraviolet irradiation peelable adhesive layer 12 has a characteristic that it can be peeled off by reducing the adhesive strength by irradiating ultraviolet rays (UV). As a suitable example of the ultraviolet irradiation peelable adhesive layer 12, there is an ultraviolet curable resin having a characteristic that the adhesive strength is reduced by ultraviolet irradiation by introducing a photofunctional group into an epoxy polymer or an acrylic polymer. ˜100 μm.

  Next, as shown in FIG. 1B, a first seed layer 14 made of copper (Cu) or the like is formed on the ultraviolet irradiation peelable adhesive layer 12 by sputtering or electroless plating. Subsequently, as shown in FIG. 1C, the first resin layer 16 having the opening 16 a is formed on the first seed layer 14. As a method of forming the first resin layer 16, a method of forming the opening 16a by photolithography after forming the photosensitive resin layer may be used, or after forming the thermosetting resin layer, the opening is formed by laser. The portion 16a may be formed.

  Thereafter, as shown in FIG. 1C, an external connection terminal made of copper (Cu) or the like is formed by electrolytic plating using the first seed layer 14 as a plating power feeding layer in the opening 16a of the first resin layer 16. The pad 18 is formed. The external connection terminal pad 18 is provided with an external connection terminal later.

  Next, as shown in FIG. 2A, after the second seed layer 20a is formed on the external connection terminal pad 18, the resist film 22 having the opening 22a provided on the second seed layer 20a is photolithography. Formed by. Subsequently, the metal layer 20b is formed in the opening 22a by electrolytic plating using the second seed layer 20a as a plating power feeding layer.

  Further, as shown in FIG. 2B, after the resist film 22 is removed, the second seed layer 20a is etched using the metal layer 20b as a mask, thereby forming the seed layer 20a and the metal layer 20b. Then, the wiring part 20 electrically connected to the external connection terminal pad 18 is obtained.

  Next, as shown in FIG. 2C, the second resin layer 24 having the opening 24 a provided on the wiring portion 20 is formed by a method similar to the method for forming the first resin layer 16. Thereafter, the Ni / Au layer is formed in the opening 24a of the second resin layer 24 by electrolytic plating using the first seed layer 14, the external connection terminal pad 18 and the wiring portion 20 as a power feeding path, thereby connecting the connection pad. 26 (connection part). When the connection pad 26 is formed so as to protrude from the upper surface of the second resin layer 24, the upper part of the connection pad 26 may be polished and planarized.

  As described above, the rewiring layer 3 composed of the external connection terminal pad 18, the wiring portion 20, and the connection pad 26 is formed on the temporary substrate 10 via the ultraviolet irradiation peelable adhesive layer 12 and the first seed layer 14. Is done. Note that the rewiring layer 3 may be formed by stacking the wiring portions 20 in n layers (n is an integer of 2 or more).

  The redistribution layer 3 formed on the temporary substrate 10 is divided into a plurality of regions so that the semiconductor circuit becomes a redistribution layer of a regular silicon wafer (semiconductor substrate) formed in the plurality of element formation regions. It is formed. As will be described later, the rewiring layer 3 formed on the temporary substrate 10 is transferred and formed on a regular silicon wafer on which the semiconductor circuit is formed, and the rewiring layer connected to the semiconductor circuit Become.

  Next, a method for forming bumps on such a regular silicon wafer will be described. 6A to 6D show a method for forming gold bumps on a silicon wafer. As shown in FIG. 6A, first, a required transistor or the like is formed to form a semiconductor circuit (not shown), and the connection pad 32 connected to the semiconductor circuit is exposed on the upper surface side. A silicon wafer 30 is prepared. Thereafter, as shown in FIG. 6B, a seed layer 34 that covers the connection pads 32 is formed on the silicon wafer 30. Further, as shown in FIG. 6C, after forming a resist film 36 having an opening 36a on the seed layer 34a on the connection pad 32, the seed layer 34 is plated in the opening 36a. A gold (Au) layer 38a is formed by electrolytic plating used for the power feeding layer.

  Next, as shown in FIG. 6D, after removing the resist film 36, the seed layer 34 is etched using the gold layer 38a as a mask. As a result, a gold bump 38 (connection portion) that is electrically connected to the connection pad 32 via the seed layer 34 is obtained.

  Alternatively, solder bumps may be provided on the silicon wafer 30 instead of the gold bumps 34. In the case of this embodiment, as shown in FIG. 7A, a resist film 36 having an opening 36a on the seed layer 34 on the connection pad 32 is formed as in FIG. After the formation, a copper (Cu) / nickel (Ni) / gold (Au) layer 35a and a solder layer 35b are sequentially formed in the opening 36a by electrolytic plating.

  Subsequently, as shown in FIG. 7B, after removing the resist film 36 and then etching the seed layer 34 using the solder layer 35b as a mask, the solder layer 35b is subjected to reflow heating to thereby form solder bumps 35 (connections). Part).

  In addition, although the thing provided with the gold bump 38 and the solder bump 35 was illustrated as the silicon wafer 30, it cannot be overemphasized that various metal bumps can be used.

  Next, a method for transferring and forming the rewiring layer 3 on the temporary substrate 10 described above on the silicon wafer 30 on which the semiconductor circuit is formed will be described. In the present embodiment, an example in which the silicon wafer 30 provided with the gold bumps 38 in FIG.

  As shown in FIG. 3A, the temporary bump 10 of the silicon wafer 30 in FIG. 6D corresponds to the connection pad 26 (Ni / Au layer) of the temporary substrate 10 in FIG. A silicon wafer 30 is disposed on the substrate 10, and the connection pads 26 (Ni / Au layer) of the temporary substrate 10 and the gold bumps 38 of the silicon wafer 30 are joined by thermocompression bonding. At this time, when the thermal expansion coefficient of the temporary substrate 10 is significantly different from the thermal expansion coefficient (3.4 ppm / ° C.) of the silicon wafer 30, the connection pads 26 of the temporary substrate 10 and the gold bumps of the silicon wafer 30 are generated due to the generation of thermal stress. 38 is misaligned and a highly reliable joint cannot be obtained. However, in this embodiment, since the thermal expansion coefficient of the temporary substrate 10 (glass or resin) can be set to 3.4 ± 2 ppm / ° C., the connection pads 26 of the temporary substrate 10 and the gold bumps 38 of the silicon wafer 30 are positioned. It is possible to join with high reliability without occurrence of displacement.

  Note that an underfill resin may be filled between the temporary substrate 10 and the silicon wafer 30 after the connection pads 26 of the temporary substrate 10 and the gold bumps 38 of the silicon wafer 30 are bonded.

Next, as illustrated in FIG. 3B, ultraviolet rays having a wavelength of 200 to 450 nm are transmitted through the temporary substrate 10 from the outside of the temporary substrate 10 and irradiated to the ultraviolet irradiation peelable adhesive layer 12. At this time, the irradiation intensity of ultraviolet rays is set in the range of 1000 to 5000 mJ / cm ² . As described above, the ultraviolet irradiation peelable adhesive layer 12 has a function capable of being peeled off by irradiating ultraviolet rays, and can be peeled off at the interface between the first seed layer 14 and the ultraviolet radiation peelable adhesive layer 12.

  As a result, as shown in FIG. 4A, the temporary substrate 10 and the ultraviolet irradiation peelable adhesive layer 12 are removed from the structure of FIG. 3B, and the first seed layer 14 is exposed on the lower side. It becomes. Thus, in this embodiment, since the ultraviolet irradiation peelable adhesive layer 12 is used as a peelable layer, the temporary substrate 10 is stably removed in a predetermined process without causing problems such as stress generation during peeling. can do.

  Subsequently, as shown in FIG. 4B, the seed layer 14 is selectively removed from the structure of FIG. 4A by etching, whereby the external connection terminal pad 18 and the first resin layer are formed on the lower side. 16 is exposed. In this manner, the rewiring layer 3 including the connection pads 26, the wiring portions 20, and the external connection terminal pads 18 is formed on the silicon wafer 30 (on the bottom in FIG. 4B). 38 is transferred and formed in an electrically connected state.

  In the above-described embodiment, metal bumps (gold bumps 38 or solder bumps 35) are exemplified as connection portions of the silicon wafer 30, and connection pads 26 made of Ni / Au layers are exemplified as connection portions of the temporary substrate 10. The connection part of the silicon wafer 30 may be a connection pad, and the connection part of the temporary substrate 10 may be a metal bump. Moreover, the material of each connection part of the silicon wafer 30 and the temporary substrate 10 can employ | adopt the combination of various metals. Moreover, you may make it join the connection part of the temporary substrate 10 and the connection part of the silicon wafer 30 with a conductive resin paste.

  Next, as shown in FIG. 4C, a solder layer is formed on the external connection terminal pad 18 by printing and then reflow heating is performed to form the external connection terminal 39. Alternatively, the external connection terminals 39 may be formed by reflow heating after mounting solder balls on the external connection terminal pads 18. The external connection terminal pad 18 may be used as the external connection terminal without providing the external connection terminal 39.

  Thereafter, as shown in FIG. 5, the structure shown in FIG. 4C is cut so that individual element formation regions of the silicon wafer 30 can be obtained, whereby individual semiconductors having the CSP structure of the first embodiment are obtained. Device 1 is obtained.

  As described above, in the method of manufacturing a semiconductor device according to the first embodiment, first, the external connection terminal pad 18 is formed on the temporary substrate 10 via the ultraviolet irradiation peeling adhesive layer 12 and the first seed layer 14. Then, the rewiring layer 3 composed of the wiring portion 20 and the connection pad 26 is formed. Thereafter, the connection pads 26 of the temporary substrate 10 are bonded to the gold bumps 38 of the silicon wafer 30 on which the semiconductor circuit is formed. Further, by irradiating the ultraviolet irradiation peelable adhesive layer 12 with ultraviolet rays from the temporary substrate 10 side, the ultraviolet irradiation peelable adhesive layer 12 is peeled from the interface with the first seed layer 14, and the ultraviolet irradiation peelable adhesive layer 12 and The temporary substrate 10 is removed. Thereafter, the first seed layer 14 is removed.

  As a result, the rewiring layer 3 is transferred and formed on the silicon wafer 30 in a state where the connection pads 26 of the rewiring layer 3 are electrically connected to the gold bumps 38 of the silicon wafer 30. Thereafter, the external connection terminals 39 are provided on the exposed external connection pads 18 and then divided to obtain the individual semiconductor devices 1.

  In this embodiment, since the ultraviolet irradiation peelable adhesive layer 12 is used as the peelable layer and the ultraviolet radiation peelable adhesive layer 12 is peeled off by ultraviolet irradiation, there is no problem that the temporary substrate 10 cannot be removed well. Therefore, the temporary substrate 10 can be removed stably. In addition, since the temporary substrate 10 (glass or resin) that transmits ultraviolet rays can be selected to approximate the thermal expansion coefficient of the silicon wafer 30, when joining the connection pads 26 of the temporary substrate 10 to the gold bumps 38 of the silicon wafer 30. In addition, the generation of thermal stress is suppressed, and bonding can be performed without being displaced.

  Further, since a method of forming the rewiring layer 3 on the temporary substrate 10 and transferring the rewiring layer 3 onto the silicon wafer 30 is adopted, a technique (for example, laser) that adversely affects the semiconductor circuit of the silicon wafer 30 is adopted. Even if it exists, it can be used and a manufacturing method is not restrict | limited.

  Further, for the same reason, it is not necessary to perform a film forming process or a plating process for forming the rewiring layer 3 on the silicon wafer 30, so that the cleanliness can be adjusted to the specifications of the silicon wafer 30 in these processes, It is not necessary to consider countermeasures against static electricity of the silicon wafer 30, and process management becomes easy.

  Furthermore, even when the silicon wafer 30 is thinned and weak in strength, it is not necessary to perform a film forming process or a plating process for forming the rewiring layer 3 on the silicon wafer 30. The problem that handling becomes difficult in the process is also solved.

(Second Embodiment)
8 to 10 are sectional views showing a method for manufacturing a semiconductor device according to the second embodiment of the present invention. The second embodiment is different from the first embodiment in that a wiring layer is formed on the temporary substrate 10 by an imprint method. In the second embodiment, detailed description of the same steps as those in the first embodiment is omitted.

  As shown in FIG. 8A, first, after forming the ultraviolet irradiation peeling adhesive layer 12 on the temporary substrate 10 by the same method as in the first embodiment, the first seed layer 14 is formed. Thereafter, as shown in FIG. 8B, a semi-cured first resin layer 16 is formed on the seed layer 14. Next, as shown in FIG. 8C, by pressing (pressing) the semi-cured first resin layer 16 with a mold (not shown) having a required shape, the opening 16x and the first resin layer 16 are opened. A recess 16y communicating with it is formed. The opening 16x and the recess 16y are formed by embedding a metal layer to form a wiring layer, and are formed so that the external connection terminal pad 18 and the wiring part 20 of the first embodiment are formed simultaneously. That is, the opening 16x is formed in the first resin layer 16 so that the seed layer 14 is exposed in the portion where the external connection terminal pad 18 is formed, and the first resin layer 16 is formed in the portion where the wiring portion 20 is formed. A recess 16 y is formed so as to remain on seed layer 14. Thereafter, the first resin layer 16 is heat-treated to be completely cured.

  Next, as shown in FIG. 9A, a Cu layer is formed by sputtering or electroless plating on the first resin layer 16 in which the opening 16x and the recess 16y are formed to form the second seed layer 20a. Further, as shown in FIG. 9B, a metal layer 20b for embedding the openings 16x and the recesses 16y of the first resin layer 16 by electrolytic plating using the first and second seed layers 14 and 20a as plating power feeding layers. It is formed on the second seed layer 20a. Thereafter, as shown in FIG. 9C, the metal layer 20b and the second seed layer 20a are polished until the upper surface of the first resin layer 16 is exposed, whereby the openings 16x and the recesses of the first resin layer 16 are obtained. The second seed layer 20a and the metal layer 20b are embedded in 16y.

  As a result, the external connection terminal pad 18 is formed below the opening 16x of the first resin layer 16, and the wiring portion 20 connected to the external connection terminal pad is formed in the recess 16y.

  Next, as shown in FIG. 10A, as in the first embodiment, after the second resin layer 24 having the opening 24a is formed on the wiring portion 20, the second resin layer 24 is formed by electrolytic plating. A Ni / Au layer is formed in the opening 24 a of the contact pad 26. As a result, as in the first embodiment, the external connection terminal pad 18, the wiring portion 20, and the connection pad 26 are disposed on the temporary substrate 10 via the ultraviolet irradiation peelable adhesive layer 12 and the first seed layer 14. The rewiring layer 3 to be configured is formed.

  Subsequently, as shown in FIG. 10B, after the gold bumps 38 of the silicon wafer 30 on which the semiconductor circuit is formed are bonded to the connection pads 26 of the temporary substrate 10 as in the first embodiment, Ultraviolet radiation is applied to the ultraviolet radiation peelable adhesive layer 12 from the side. Thereby, as shown in FIG. 11A, the temporary substrate 10 and the ultraviolet irradiation peelable adhesive layer 12 are peeled, and the first seed layer 14 is exposed on the lower surface.

  Next, as shown in FIG. 11B, as in the first embodiment, after the first seed layer 14 is removed, external connection terminals 39 are provided on the exposed external connection pads 18. Thereafter, as shown in FIG. 11C, the individual semiconductor device 1a having the CSP structure of the second embodiment is obtained by cutting the structure of FIG. 11B.

  The second embodiment has the same effects as the first embodiment.

(Third embodiment)
12 and 13 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the third embodiment of the present invention. In the third embodiment, an electronic component is formed or mounted on a temporary substrate, and transferred and formed on a silicon wafer simultaneously with the rewiring layer. In the third embodiment, detailed description of the same steps as those in the first embodiment is omitted.

  As shown in FIG. 12A, first, a structure similar to that in FIG. 2B is created by the same method as in the first embodiment, and then the electronic component 25 connected to the wiring portion 20 is formed or formed. Implement. As the electronic component, a capacitor (C), a reactance (L), a resistor (R), or a semiconductor chip is used, and may be formed by processing a thin film in a series of manufacturing steps of this embodiment. The electronic component may be mounted with solder or the like. In the example of FIG. 12A, a form in which an electronic component 25 such as a capacitor (C), reactance (L), or resistance (R) is built is shown.

  Next, as shown in FIG. 12B, after the electronic component 25 is covered and the second insulating layer 24 provided with the opening 24a is formed on the wiring part 20, the Ni / N in the opening 24a is formed. An Au layer is formed by electrolytic plating to obtain the connection pad 26. Thereby, the rewiring layer 3 in which the electronic component 25 is incorporated is formed on the temporary substrate 10.

  Subsequently, from the step of bonding the gold bumps 38 of the silicon wafer 30 to the connection pads 26 of the temporary substrate 10 of the first embodiment (FIG. 3A) to the step of providing the external connection terminals 39 (FIG. 4C). Perform the process. As a result, as shown in FIG. 13A, the electronic component 25 is connected on the silicon wafer 30 with the connection pads 26 of the rewiring layer 3 being electrically connected to the gold bumps 38 of the silicon wafer 30. The rewiring layer 3 is transferred and formed. Thereafter, as shown in FIG. 13B, the individual semiconductor device 1b having the CSP structure of the third embodiment is obtained by cutting the structure shown in FIG. 13A.

  The third embodiment has the same effect as the first embodiment, and can incorporate the electronic component 25 in the rewiring layer 3 formed on the silicon wafer 30 without adversely affecting the silicon wafer 30. .

(Fourth embodiment)
14 to 16 are sectional views showing a method for manufacturing a semiconductor device according to the fourth embodiment of the present invention. The feature of the fourth embodiment is that an external connection terminal connected to the temporary substrate is formed on the temporary substrate before forming the wiring layer on the temporary substrate, and is transferred and formed on the silicon wafer simultaneously with the wiring layer. is there. In the fourth embodiment, detailed description of the same steps as those in the first embodiment is omitted.

  As shown in FIG. 14 (a), first, after the ultraviolet irradiation peelable adhesive layer 12 is formed on the temporary substrate 10 as in the first embodiment, the copper foil 40 (metal made of the first metal) is formed thereon. Paste the foil. Subsequently, as shown in FIG. 14B, after forming the first resin layer 16 provided with the opening 16a on the copper foil 40, the concave portion is obtained by wet etching the copper foil 40 through the opening 16a. 40a is formed. Next, as shown in FIG. 14C, after forming the solder layer 42a (metal layer made of the second metal) in the recess 40a of the copper foil 40 by electrolytic plating using the copper foil 40 as a plating power feeding layer, A copper layer is formed in the opening 16a of the first resin layer 16 to form an external connection terminal pad 18 similar to that of the first embodiment.

  Next, as shown in FIG. 15A, the process of forming the connection pad 26 (FIG. 2C) is performed from the process of forming the second seed layer 20a of the first embodiment (FIG. 2A). To do. As a result, the rewiring layer 3 including the external connection terminal pads 18 connected to the solder layer 42 a, the wiring portion 20, and the connection pads 26 is formed above the temporary substrate 10.

  Further, as shown in FIG. 15B, as in the first embodiment, after the gold bumps 38 of the silicon wafer 30 are bonded to the connection pads 26 of the temporary substrate 10, ultraviolet rays are applied to the ultraviolet irradiation peelable adhesive layer 12. Irradiation removes the temporary substrate 10 and the ultraviolet irradiation peelable adhesive layer 12. Thereby, in 4th Embodiment, as shown to Fig.16 (a), it will be in the state which the copper foil 40 exposed to the lower side.

  Subsequently, as shown in FIG. 16B, the copper foil 40 is selectively removed with respect to the solder layer 42 a and the first resin layer 16. For example, the copper foil 40 is selectively etched and removed from the solder layer 42a and the first resin layer 16 by wet etching using a ferric chloride aqueous solution, a cupric chloride aqueous solution, an ammonium persulfate aqueous solution, or the like. Can do.

  Thereby, the solder layer 42a is exposed in a state of protruding from the lower surface of the first resin layer 16.

  Next, as shown in FIG. 16C, the solder layer 42a is reflow heated to form the external connection terminal 42, and then the structure is cut. Thereby, individual semiconductor devices 1c having the CSP structure of the fourth embodiment are obtained.

  As described above, in the fourth embodiment, the copper foil 40 is used on the temporary substrate 10 instead of the first seed layer 14, and the solder layer 42 a serving as the external connection terminal 42 is formed in the recess 40 a provided thereon. Later, simultaneously with the rewiring layer 3, the solder layer 42 a is transferred onto the silicon wafer 30. Therefore, unlike the first embodiment, it is not necessary to specially form the external connection terminals 39 after the rewiring layer 3 is transferred to the silicon wafer 30.

  The fourth embodiment has the same effects as the first embodiment.

1A to 1C are cross-sectional views (No. 1) showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention. 2A to 2C are cross-sectional views (part 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention. 3A and 3B are sectional views (No. 3) showing the method for manufacturing the semiconductor device according to the first embodiment of the invention. 4A to 4C are cross-sectional views (part 4) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the invention. FIG. 5 is a sectional view (No. 5) showing the method for manufacturing the semiconductor device according to the first embodiment of the invention. 6A to 6D are cross-sectional views showing a method for forming gold bumps on a silicon wafer. 7A and 7B are cross-sectional views showing a method for forming solder bumps on a silicon wafer. 8A to 8C are cross-sectional views (part 1) showing the method for manufacturing the semiconductor device according to the second embodiment of the present invention. 9A to 9C are cross-sectional views (part 2) illustrating the method for manufacturing the semiconductor device according to the second embodiment of the present invention. FIGS. 10A and 10B are sectional views (No. 3) showing the method for manufacturing the semiconductor device according to the second embodiment of the invention. 11A to 11C are cross-sectional views (part 4) illustrating the method for manufacturing the semiconductor device according to the second embodiment of the invention. 12A and 12B are sectional views (No. 1) showing the method for manufacturing the semiconductor device according to the third embodiment of the invention. 13A and 13B are sectional views (No. 2) showing the method for manufacturing a semiconductor device according to the third embodiment of the present invention. 14A to 14C are sectional views (No. 1) showing the method for manufacturing a semiconductor device according to the fourth embodiment of the invention. 15A and 15B are sectional views (No. 2) showing the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention. 16A to 16C are cross-sectional views (part 3) illustrating the method for manufacturing the semiconductor device according to the fourth embodiment of the invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,1a, 1b, 1c ... Semiconductor device, 3 ... Redistribution layer, 10 ... Temporary board | substrate, 12 ... Ultraviolet irradiation peelable adhesive layer, 14 ... 1st seed layer, 16 ... 1st resin layer, 16a, 16x, 22a , 24a, 36a ... opening, 16y, 40a ... recess, 18 ... external connection terminal pad, 20a ... second seed layer, 20b ... metal layer, 20 ... wiring part, 22, 36 ... resist film, 24 ... second Resin layer, 26, 32 ... connection pad, 30 ... silicon wafer (semiconductor substrate), 34 ... seed layer, 35a ... copper (Cu) / nickel (Ni) / gold (Au) layer, 35b, 42a ... solder layer, 35 ... solder bumps, 38a ... gold layer, 38 ... gold bumps, 39, 42 ... external connection terminals, 40 ... copper foil.

Claims (12)

Forming an ultraviolet irradiation peelable adhesive layer on the temporary substrate;
A step of forming a wiring layer having a connection portion at the top on the ultraviolet radiation peeling type adhesive layer;
Bonding the connection portion of the wiring layer on the temporary substrate and the connection portion of the semiconductor substrate on which a semiconductor circuit is formed;
A step of detaching and removing the ultraviolet radiation peelable adhesive layer and the temporary substrate by irradiating the ultraviolet radiation peelable adhesive layer with ultraviolet rays from the temporary substrate side. Method.   The method of manufacturing a semiconductor device according to claim 1, wherein the wiring layer includes an external connection terminal pad at the bottom. The step of forming the wiring layer includes:
Forming the external connection terminal pad in the opening of the first resin layer provided on the ultraviolet radiation peelable adhesive layer;
Forming a wiring portion electrically connected to the external connection terminal pad on the first resin layer;
And a step of covering the part of the wiring part and forming the connection part in the opening part of the second resin layer provided with an opening part on the wiring part. The manufacturing method of the semiconductor device as described in any one of Claims 1-3. The step of forming the external connection terminal pad includes:
Forming a seed layer on the ultraviolet radiation peelable adhesive layer;
Forming the first resin layer provided with the opening on the seed layer;
Forming a metal layer in the opening of the first resin layer by electrolytic plating using the seed layer as a plating power feeding layer to obtain the external connection terminal pad,
The method for manufacturing a semiconductor device according to claim 3, further comprising a step of removing the seed layer after the step of peeling and removing the ultraviolet radiation peelable adhesive layer and the temporary substrate. After the step of peeling and removing the ultraviolet irradiation peelable adhesive layer and the temporary substrate,
5. The method of manufacturing a semiconductor device according to claim 2, further comprising a step of providing an external connection terminal on the exposed external connection terminal pad. The step of forming the wiring layer includes:
Forming a first resin layer on the ultraviolet radiation peelable adhesive layer;
Forming an opening in the first resin layer and a recess communicating with the first resin layer by pressing the first resin layer with a mold;
Forming a metal layer that fills the opening and the recess on the first resin layer;
The metal layer is polished until the upper surface of the first resin layer is exposed, and the metal layer is embedded in the opening and recess of the resin layer, whereby the external connection terminal pad is obtained below the opening. And a step of obtaining a wiring portion connected to the external connection terminal pad in the concave portion;
The method of manufacturing a semiconductor device according to claim 2, further comprising: forming the connection portion in the opening portion of the second resin layer in which the opening portion is provided on the wiring portion.   The semiconductor device according to claim 1, wherein in the step of forming the wiring layer, an electronic component electrically connected to a predetermined portion of the wiring layer is formed or mounted. Production method. Before the step of forming the wiring layer,
Forming a metal foil made of a first metal on the ultraviolet radiation peelable adhesive layer;
Forming a resin layer provided with an opening on the metal foil;
Forming a recess in the portion of the metal foil in the opening of the resin layer;
Forming a metal layer made of a second metal different from the metal foil in the concave portion of the metal foil by electrolytic plating,
The external connection terminal pad is formed in the opening of the resin layer on the metal layer,
After the step of peeling and removing the ultraviolet irradiation peelable adhesive layer and the temporary substrate,
4. The method of manufacturing a semiconductor device according to claim 2, further comprising a step of exposing the metal layer serving as an external connection terminal by selectively removing the metal foil with respect to the metal layer. .   9. The method of manufacturing a semiconductor device according to claim 1, wherein the connection portion of the temporary substrate is a connection pad, and the connection portion of the semiconductor substrate is a metal bump.   10. The semiconductor device according to claim 1, wherein the temporary substrate is made of any one selected from the group consisting of borosilicate glass, silica glass, acrylic resin, and polytetrafluoroethylene. Production method.   10. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate is a silicon wafer.   10. The method of manufacturing a semiconductor device according to claim 1, wherein the ultraviolet irradiation peelable adhesive layer is an ultraviolet curable resin having a characteristic that adhesive strength is reduced by ultraviolet irradiation. 11.

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