JP2007027368A - Multilayer interconnection board - Google Patents

Multilayer interconnection board Download PDF

Info

Publication number
JP2007027368A
JP2007027368A JP2005206710A JP2005206710A JP2007027368A JP 2007027368 A JP2007027368 A JP 2007027368A JP 2005206710 A JP2005206710 A JP 2005206710A JP 2005206710 A JP2005206710 A JP 2005206710A JP 2007027368 A JP2007027368 A JP 2007027368A
Authority
JP
Japan
Prior art keywords
land
wiring pattern
solder
pattern
conductive layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2005206710A
Other languages
Japanese (ja)
Other versions
JP4752367B2 (en
Inventor
Hisao Hoshino
久雄 星野
Yoshihiko Minamitani
佳彦 南谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Aisin AW Co Ltd
Original Assignee
Aisin AW Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Aisin AW Co Ltd filed Critical Aisin AW Co Ltd
Priority to JP2005206710A priority Critical patent/JP4752367B2/en
Publication of JP2007027368A publication Critical patent/JP2007027368A/en
Application granted granted Critical
Publication of JP4752367B2 publication Critical patent/JP4752367B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To improve reliability in electronic components by preventing solder-up failure from occurring. <P>SOLUTION: A multilayer interconnection board comprises a plurality of base materials, a plurality of conductive layers that are laminated to each base material for formation and have a prescribed wiring pattern, and a land 16 arranged at a through hole 15 penetrating the base materials and the conductive layers. The leads of electronic components are inserted into the through hole 15, the leads and the land 16 are connected by a jointing material, and a component surface Sa and a solder surface Sb are formed on one surface and the other, respectively. Then, a wiring pattern having a large heat capacity in the wiring patterns is connected to the land 16 at the side of the solder surface Sb by a wiring pattern having a small heat capacity. When soldering electronic components to the multilayer interconnection board 11, much amount of heat in solder cannot be transmitted to the wiring pattern having a large heat capacity. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、多層配線基板に関するものである。   The present invention relates to a multilayer wiring board.

従来、複数の基材及び導電層を積層して形成された多層の配線構造を有する基板、すなわち、多層配線基板に各種の電子部品を取り付け、かつ、電気的に接続するに当たり、例えば、ポイントフロー(スポットフロー)式の半田付けが行われるようになっている。   Conventionally, a substrate having a multilayer wiring structure formed by laminating a plurality of base materials and conductive layers, that is, when various electronic components are attached to and electrically connected to a multilayer wiring substrate, for example, a point flow (Spot flow) type soldering is performed.

そのために、前記多層配線基板は、一方の面に部品面が、他方の面に半田面が形成され、部品面と半田面との間にスルーホールが貫通させて形成され、該スルーホールに前記電子部品のリードが挿入される。そして、前記各導電層が有する配設パターンのうちの所定の配設パターンと前記リードとを電気的に接続するために、スルーホールにランドが配設される。   For this purpose, the multilayer wiring board has a component surface formed on one surface and a solder surface formed on the other surface, and a through hole is formed between the component surface and the solder surface. Electronic component leads are inserted. A land is disposed in the through hole in order to electrically connect a predetermined arrangement pattern of the arrangement patterns of each conductive layer and the lead.

前記ポイントフロー式の半田付けにおいては、半田面上の半田付けをする各点(以下「半田付けポイント」という。)を含む所定の領域にわたって半田付けエリアが設定され、該半田付けエリアの各半田付けポイントに、溶融させられた半田を同時に供給するようにしている。   In the point flow type soldering, a soldering area is set over a predetermined area including each point to be soldered on the solder surface (hereinafter referred to as “soldering point”), and each solder in the soldering area is set. The melted solder is simultaneously supplied to the attachment point.

そのために、半田付けエリアの全体を包囲するだけの面積を有するノズルが、半田ロボットによって前進させられ、半田付けエリアとほぼ接触する位置、すなわち、半田付け位置に置かれ、ノズル内の溶融させられた半田が、各半田付けポイントに向けて吐出させられ、塗布される。   For this purpose, a nozzle having an area sufficient to enclose the entire soldering area is advanced by the solder robot, placed in a position almost in contact with the soldering area, that is, the soldering position, and melted in the nozzle. The solder is discharged and applied toward each soldering point.

そして、前記半田面において、リードの先端側からスルーホールに向けて吐出された前記半田は、スルーホールの内周面とリードの外周面との間の隙(すき)間を、半田面側から部品面側に向けて流れ、部品面側からスルーホール外に出る。その結果、半田は、スルーホール内を満たし、半田面及び部品面に円錐(すい)形の半田フィレットが形成される。   In the solder surface, the solder discharged from the leading end side of the lead toward the through hole has a gap (clearance) between the inner peripheral surface of the through hole and the outer peripheral surface of the lead from the solder surface side. Flows toward the component surface and exits from the through hole from the component surface. As a result, the solder fills the through hole, and a conical solder fillet is formed on the solder surface and the component surface.

しかしながら、前記従来のポイントフロー式の半田付けにおいては、通常のフロー式の半田付けと比較すると、半田の熱容量が小さいので、前記導電層に熱が奪われてしまうことがある。例えば、電子部品としてのコネクタを多層配線基板に取り付けるに当たり、前記コネクタのリードと配設パターンとがスルーホール内で接続されることになるが、所定の配設パターンの熱容量が大きい場合に、前記配設パターンに半田の熱量の多くが伝達されると、半田面側から部品面側に向けて溶融させられた半田を十分に供給することができなくなり、半田上り不良が発生しやすい。   However, in the conventional point flow type soldering, the heat capacity of the solder may be smaller than that of the normal flow type soldering, so that heat may be lost to the conductive layer. For example, when attaching a connector as an electronic component to a multilayer wiring board, the lead of the connector and the arrangement pattern are connected in a through hole. When the heat capacity of the predetermined arrangement pattern is large, When a large amount of heat of the solder is transmitted to the arrangement pattern, it is not possible to sufficiently supply the melted solder from the solder surface side to the component surface side, and a solder rise failure is likely to occur.

この種の半田上り不良が発生すると、振動等が加わることによって断線が発生することがあるので、手作業で半田付けを修正するようにしている。ところが、手作業で半田付けを修正する場合、フロー式の半田付けより高温(通常は300〔℃〕以上)で行う必要があるので、長時間(例えば、5秒以上)修正作業を行うと、電子部品の信頼性が低下することがある。   When this kind of soldering failure occurs, disconnection may occur due to vibrations and the like, so soldering is corrected manually. However, when correcting the soldering manually, it is necessary to perform it at a higher temperature (usually 300 [° C.] or higher) than the flow type soldering. The reliability of electronic components may be reduced.

本発明は、前記従来の多層配線基板の問題点を解決して、半田上り不良が発生するのを防止することができ、電子部品の信頼性を向上させることができる多層配線基板を提供することを目的とする。   The present invention provides a multilayer wiring board capable of solving the problems of the conventional multilayer wiring board, preventing the occurrence of defective soldering, and improving the reliability of electronic components. With the goal.

そのために、本発明の多層配線基板においては、複数の基材と、該各基材に積層させて形成され、所定の配線パターンを有する複数の導電層と、前記基材及び前記導電層を貫通するスルーホールに配設されたランドとを有するとともに、電子部品のリードが前記スルーホールに挿入され、前記リードと前記ランドとが接合材によって接続され、一方の面に前記電子部品を取り付けるための部品面が、他方の面に半田付けを行うための半田面が形成されるようになっている。   Therefore, in the multilayer wiring board of the present invention, a plurality of base materials, a plurality of conductive layers formed by being laminated on the respective base materials and having a predetermined wiring pattern, and penetrating the base material and the conductive layers And a land of the electronic component is inserted into the through hole, the lead and the land are connected by a bonding material, and the electronic component is attached to one surface. The component surface is formed with a solder surface for soldering to the other surface.

そして、前記配線パターンのうちの熱容量の大きい配線パターンが、熱容量の小さい配線パターンより半田面側で前記ランドと接続される。   A wiring pattern having a large heat capacity among the wiring patterns is connected to the land on the solder surface side of the wiring pattern having a small heat capacity.

本発明の他の多層配線基板においては、さらに、前記配線パターンのうちの面積の大きい配線パターンが、面積の小さい配線パターンより半田面側で前記ランドと接続される。   In another multilayer wiring board of the present invention, the wiring pattern having a larger area among the wiring patterns is connected to the land on the solder surface side than the wiring pattern having a smaller area.

本発明の更に他の多層配線基板においては、さらに、前記各導電層のうちの厚い導電層が、薄い導電層より半田面側に配設される。   In still another multilayer wiring board of the present invention, a thick conductive layer among the conductive layers is further disposed on the solder surface side than the thin conductive layer.

本発明の更に他の多層配線基板においては、複数の基材と、該各基材に積層させて形成され、所定の配線パターンを有する複数の導電層と、前記基材及び前記導電層を貫通するスルーホールに配設されたランドとを有するとともに、電子部品のリードが前記スルーホールに挿入され、前記リードと前記ランドとが接合材によって接続され、一方の面に前記電子部品を取り付けるための部品面が、他方の面に半田付けを行うための半田面が形成されるようになっている。   In yet another multilayer wiring board of the present invention, a plurality of base materials, a plurality of conductive layers formed on each base material and having a predetermined wiring pattern, and penetrating the base material and the conductive layers And a land of the electronic component is inserted into the through hole, the lead and the land are connected by a bonding material, and the electronic component is attached to one surface. The component surface is formed with a solder surface for soldering to the other surface.

そして、前記配線パターンのうちの熱伝導率の高い配線パターンが、熱伝導率の低い配線パターンより半田面側で前記ランドと接続される。   A wiring pattern having a high thermal conductivity among the wiring patterns is connected to the land on the solder surface side of the wiring pattern having a low thermal conductivity.

本発明の更に他の多層配線基板においては、さらに、前記配線パターンの熱伝導率は、導電層を構成する材質を異ならせることによって調整される。   In still another multilayer wiring board of the present invention, the thermal conductivity of the wiring pattern is further adjusted by changing the material constituting the conductive layer.

本発明の更に他の多層配線基板においては、さらに、前記半田面側で前記ランドと接続される配線パターンは、べたパターンで形成される。   In still another multilayer wiring board of the present invention, the wiring pattern connected to the land on the solder surface side is formed as a solid pattern.

本発明の更に他の多層配線基板においては、さらに、前記半田面側で前記ランドと接続される配線パターンは、電力供給用の太い配線で形成される。   In still another multilayer wiring board of the present invention, the wiring pattern connected to the land on the solder surface side is formed by a thick wiring for supplying power.

本発明の更に他の多層配線基板においては、さらに、前記ランドと配線パターンとの間に、ランドから配線パターンに伝わる熱量を少なくするための溝が形成される。   In still another multilayer wiring board of the present invention, a groove for reducing the amount of heat transmitted from the land to the wiring pattern is formed between the land and the wiring pattern.

本発明によれば、多層配線基板においては、複数の基材と、該各基材に積層させて形成され、所定の配線パターンを有する複数の導電層と、前記基材及び前記導電層を貫通するスルーホールに配設されたランドとを有するとともに、電子部品のリードが前記スルーホールに挿入され、前記リードと前記ランドとが接合材によって接続され、一方の面に前記電子部品を取り付けるための部品面が、他方の面に半田付けを行うための半田面が形成されるようになっている。   According to the present invention, in a multilayer wiring board, a plurality of base materials, a plurality of conductive layers formed by being laminated on the respective base materials and having a predetermined wiring pattern, and penetrating the base material and the conductive layers And a land of the electronic component is inserted into the through hole, the lead and the land are connected by a bonding material, and the electronic component is attached to one surface. The component surface is formed with a solder surface for soldering to the other surface.

そして、前記配線パターンのうちの熱容量の大きい配線パターンが、熱容量の小さい配線パターンより半田面側で前記ランドと接続される。   A wiring pattern having a large heat capacity among the wiring patterns is connected to the land on the solder surface side of the wiring pattern having a small heat capacity.

この場合、配線パターンのうちの熱容量の大きい配線パターンが、熱容量の小さい配線パターンより半田面側で前記ランドと接続されるので、電子部品を多層配線基板に半田付けする際に、半田の熱量の多くが熱容量の大きい配設パターンに伝達されることはない。したがって、半田面側から部品面側に向けて溶融させられた半田を十分に供給することができ、半田上り不良が発生するのを防止することができる。   In this case, the wiring pattern having a large heat capacity among the wiring patterns is connected to the land on the solder surface side of the wiring pattern having a small heat capacity. Therefore, when the electronic component is soldered to the multilayer wiring board, the amount of heat of the solder is reduced. Many are not transferred to the arrangement pattern with a large heat capacity. Therefore, it is possible to sufficiently supply the melted solder from the solder surface side toward the component surface side, and it is possible to prevent occurrence of defective soldering.

その結果、振動等が加わることによって断線が発生することがなくなるので、手作業で半田付けを修正する必要がなくなる。また、仮に、手作業で半田付けを修正する必要が生じても、長時間修正作業を行う必要がなくなるので、電子部品の信頼性を向上させることができる。   As a result, disconnection does not occur due to vibration or the like, so there is no need to manually correct the soldering. Further, even if it is necessary to correct the soldering manually, it is not necessary to perform the correction work for a long time, so that the reliability of the electronic component can be improved.

以下、本発明の実施の形態について図面を参照しながら詳細に説明する。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

図1は本発明の実施の形態における多層配線基板の要部を示す断面図、図2は本発明の実施の形態におけるコネクタの取付状態を示す断面図、図3は本発明の実施の形態におけるランド部と第1の導電層の配設パターンとの関係を示す第1の図、図4は本発明の実施の形態におけるランド部と第2の導電層の配設パターンとの関係を示す第1の図、図5は本発明の実施の形態におけるランド部と第3の導電層の配設パターンとの関係を示す第1の図、図6は本発明の実施の形態におけるランド部と第4の導電層の配設パターンとの関係を示す第1の図である。   FIG. 1 is a cross-sectional view showing a main part of a multilayer wiring board according to an embodiment of the present invention, FIG. 2 is a cross-sectional view showing an attachment state of a connector in the embodiment of the present invention, and FIG. FIG. 4 is a first diagram showing the relationship between the land portion and the arrangement pattern of the first conductive layer, and FIG. 4 is a first diagram showing the relationship between the land portion and the arrangement pattern of the second conductive layer in the embodiment of the present invention. FIG. 1 is a first view showing the relationship between the land portion and the arrangement pattern of the third conductive layer in the embodiment of the present invention, and FIG. 6 is a view showing the relationship between the land portion and the third conductive layer in the embodiment of the present invention. It is a 1st figure which shows the relationship with the arrangement | positioning pattern of 4 conductive layers.

図において、11は多層配線基板であり、該多層配線基板11の一方の面に、コネクタ21等の部品面Saが、他方の面に、半田付けを行うための半田面Sbが形成される。前記多層配線基板11は、複数の、本実施の形態においては、3個のベース材としての第1〜第3の基材Bi(i=1〜3)、該第1〜第3の基材Biの両面に所定の厚さで積層して形成された第1〜第4の導電層εj(j=1〜4)、及び第1、第4の導電層ε1、ε4を被覆する図示されない被覆層を備える。   In the figure, reference numeral 11 denotes a multilayer wiring board. A component surface Sa such as a connector 21 is formed on one surface of the multilayer wiring substrate 11, and a solder surface Sb for soldering is formed on the other surface. In the present embodiment, the multilayer wiring board 11 includes a plurality of first to third base materials Bi (i = 1 to 3) as the base material, and the first to third base materials. The first to fourth conductive layers εj (j = 1 to 4) formed by laminating on both sides of Bi with a predetermined thickness, and the first and fourth conductive layers ε1 and ε4, not shown With layers.

前記各第1〜第3の基材Biは、樹脂、セラミックス、紙フェノール等の絶縁性の高い材料(以下「絶縁体」という。)、本実施の形態においては、ガラスエポシキ樹脂によって所定の厚さで形成され、前記第1〜第4の導電層εjは、銅、タングステン等の導電性の高い材料(以下「導電体」という。)によって、めっきにより形成され、所定の配線パターンを有する。また、前記被覆層は絶縁体、本実施の形態においては、ソルダレジストによって形成される。   Each of the first to third base materials Bi is made of a highly insulating material (hereinafter referred to as “insulator”) such as resin, ceramics, paper phenol, etc., and in this embodiment, glass epoxy resin has a predetermined thickness. The first to fourth conductive layers εj are formed by plating with a highly conductive material such as copper or tungsten (hereinafter referred to as “conductor”) and have a predetermined wiring pattern. The covering layer is formed of an insulator, in the present embodiment, a solder resist.

なお、前記部品面Saに、前記コネクタ21のほか、図示されない集積回路チップ、半導体パッケージ、チップトランジスタ、チップダイオード、チップ抵抗、チップキャパシタ、チップコイル等の電子部品が取り付けられる。また、前記半田面Sbにも所定の電子部品が取り付けられる。   In addition to the connector 21, electronic components such as an integrated circuit chip, a semiconductor package, a chip transistor, a chip diode, a chip resistor, a chip capacitor, and a chip coil are attached to the component surface Sa. A predetermined electronic component is also attached to the solder surface Sb.

そして、スルーホール15が部品面Saから半田面Sbに向けて貫通させて形成され、前記スルーホール15にコネクタ21の複数のリードtuk(k=1、2、…)、tdm(m=1、2、…)が挿入される。   The through hole 15 is formed so as to penetrate from the component surface Sa toward the solder surface Sb, and a plurality of leads tuk (k = 1, 2,...), Tdm (m = 1, 2, ...) is inserted.

また、該リードtuk、tdmと前記各第1〜第4の導電層εjの配設パターンのうちの所定の配設パターンとの間を、互いに電気的に接続するために、スルーホール15に、円柱状のランド16が配設される。該ランド16は、銅、タングステン等の導電性の高い材料によって、めっきにより形成され、部品面Saから半田面Sbに向けて延びる筒状部17、及び第1〜第3の基材Biの両面に、各第1〜第4の導電層εjと対応させて、かつ、筒状部17から径方向外方に向けて突出させて形成されたフランジ部としての、かつ、環状の、第1〜第4のランド部Lj(j=1〜4)を備え、該各第1〜第4のランド部Ljのうちの所定のランド部と対応する配設パターンとが電気的に接続される。   Further, in order to electrically connect the leads tuk, tdm and a predetermined arrangement pattern among the arrangement patterns of the first to fourth conductive layers εj, A cylindrical land 16 is disposed. The land 16 is formed by plating with a highly conductive material such as copper or tungsten, and extends from the component surface Sa toward the solder surface Sb, and both surfaces of the first to third base materials Bi. The first to fourth conductive layers εj corresponding to each of the first and fourth conductive layers εj and projecting from the cylindrical portion 17 outward in the radial direction. A fourth land portion Lj (j = 1 to 4) is provided, and a predetermined land portion of each of the first to fourth land portions Lj is electrically connected to a corresponding arrangement pattern.

そして、前記半田面Sbにおいて、溶融させられた接合材としての半田がリードtuk、tdmの先端側からスルーホール15に向けて吐出されると、半田は、スルーホール15の内周面とリードtuk、tdmの外周面との間の隙間を、半田面Sb側から部品面Sa側に向けて流れ、部品面Sa側からスルーホール15外に出る。その結果、半田は、スルーホール15内を満たし、半田面Sb及び部品面Saに円錐形の半田フィレットf1、f2が形成される。   Then, when the molten solder as the bonding material is discharged from the tip side of the leads tuk and tdm toward the through hole 15 on the solder surface Sb, the solder is connected to the inner peripheral surface of the through hole 15 and the lead tuk. , Tdm, and the outer peripheral surface, flows from the solder surface Sb side toward the component surface Sa side, and comes out of the through hole 15 from the component surface Sa side. As a result, the solder fills the through hole 15, and conical solder fillets f1 and f2 are formed on the solder surface Sb and the component surface Sa.

ところで、ポイントフロー式の半田付けにおいては、通常のフロー式の半田付けと比較すると、半田の熱容量が小さいので、前記第1〜第4の導電層εjの配設パターンに熱が奪われてしまうことがある。すなわち、第1〜第4の導電層εjの配設パターンのうちの所定の配設パターンの熱容量が大きい場合に、前記配設パターンに半田の熱量の多くが伝達されると、半田面Sb側から部品面Sa側に向けて溶融させられた半田を十分に供給することができなくなり、半田上り不良が発生しやすい。   By the way, in the point flow type soldering, the heat capacity of the solder is smaller than that in the normal flow type soldering, so that heat is taken away by the arrangement pattern of the first to fourth conductive layers εj. Sometimes. That is, when the heat capacity of a predetermined arrangement pattern among the arrangement patterns of the first to fourth conductive layers εj is large, when a large amount of heat of solder is transmitted to the arrangement pattern, the solder surface Sb side Therefore, it becomes impossible to sufficiently supply the solder melted from the side toward the component surface Sa, and a solder rise failure is likely to occur.

そこで、本実施の形態においては、面積が大きく、熱容量が大きい配設パターンほど半田面Sb側に、面積が小さく、熱容量が小さい配設パターンほど部品面Sa側に配設するようにしている。すなわち、各配設パターンのうちの熱容量の大きい配設パターンが、熱容量の小さい配設パターンより半田面Sb側で前記ランド16と接続される。また、熱容量の小さい配設パターンが、熱容量の大きい配設パターンより部品面Sa側で前記ランド16と接続される。部品面Sa側において、配設パターンとランド16とが接続されないようにすることができる。   Therefore, in the present embodiment, an arrangement pattern having a larger area and a larger heat capacity is arranged on the solder surface Sb side, and an arrangement pattern having a smaller area and a smaller heat capacity is arranged on the component surface Sa side. That is, of the arrangement patterns, the arrangement pattern having a large heat capacity is connected to the land 16 on the solder surface Sb side than the arrangement pattern having a small heat capacity. In addition, the arrangement pattern having a smaller heat capacity is connected to the land 16 on the component surface Sa side than the arrangement pattern having a larger heat capacity. The arrangement pattern and the land 16 can be prevented from being connected on the component surface Sa side.

例えば、コネクタ21を多層配線基板11に取り付けるに当たり、各リードtuk、tdmのうちの接地用のリードをtd1としたとき、第2〜第4の導電層ε2〜ε4のうちの一つの導電層の配設パターンを、好ましくは、第3の導電層ε3又は第4の導電層ε4の配設パターンを接地用として使用し、該配線パターンをべたパターンで形成する。本実施の形態においては、第3の導電層ε3の配設パターンが接地用として使用され、前記リードtd1と第3の導電層ε3の配設パターンとが接続される。   For example, when attaching the connector 21 to the multilayer wiring board 11, when the ground lead of the leads tuk and tdm is td1, the conductive layer of one of the second to fourth conductive layers ε2 to ε4 As the arrangement pattern, the arrangement pattern of the third conductive layer ε3 or the fourth conductive layer ε4 is preferably used for grounding, and the wiring pattern is formed as a solid pattern. In the present embodiment, the arrangement pattern of the third conductive layer ε3 is used for grounding, and the lead td1 and the arrangement pattern of the third conductive layer ε3 are connected.

この場合、第3の導電層ε3の配設パターンは、べたパターンで形成されるので、熱容量が大きいが、半田面Sbに近い位置に形成されるので、半田の熱量の多くが第3の導電層ε3の配設パターンに伝達されることはない。したがって、半田面Sb側から部品面Sa側に向けて溶融させられた半田を十分に供給することができ、半田上り不良が発生するのを防止することができる。   In this case, since the arrangement pattern of the third conductive layer ε3 is formed as a solid pattern, it has a large heat capacity, but is formed at a position close to the solder surface Sb. It is not transmitted to the arrangement pattern of the layer ε3. Therefore, it is possible to sufficiently supply the melted solder from the solder surface Sb side to the component surface Sa side, and it is possible to prevent the occurrence of defective soldering.

また、前記第3のランド部L3を内側ランド部とし、第3の導電層ε3の配設パターンを外側ランド部としたとき、内側ランド部と外側ランド部とが、周方向における複数箇所、本実施の形態においては、4箇所に形成された架橋部cn1〜cn4を介して接続される。   In addition, when the third land portion L3 is an inner land portion and the arrangement pattern of the third conductive layer ε3 is an outer land portion, the inner land portion and the outer land portion have a plurality of locations in the circumferential direction. In the embodiment, they are connected via the bridging portions cn1 to cn4 formed at four locations.

そして、架橋部cn1、cn2間に扇状の溝d1が、架橋部cn2、cn3間に扇状の溝d2が、架橋部cn3、cn4間に扇状の溝d3が、架橋部cn4、cn1間に扇状の溝d4が形成され、前記第3のランド部L3、第3の導電層ε3の配設パターン、架橋部cn1〜cn4及び溝d1〜d4によって、サーマルランドが構成される。   A fan-shaped groove d1 is formed between the bridging portions cn1 and cn2, a fan-shaped groove d2 is formed between the bridging portions cn2 and cn3, a fan-shaped groove d3 is formed between the bridging portions cn3 and cn4, and a fan-shaped groove d3 is formed between the bridging portions cn4 and cn1. A groove d4 is formed, and a thermal land is configured by the third land portion L3, the arrangement pattern of the third conductive layer ε3, the bridging portions cn1 to cn4, and the grooves d1 to d4.

該サーマルランドとは、ランドとベタパターンとを接続し、かつ、熱的に分離することによって、ランドからべたパターンに移動する熱量を少なくするためのものであり、内側ランド部と外側ランド部とのクリアランス、すなわち、溝d1〜d4の径方向長さが大きいほど、ランドからべたパターンに移動する熱量が少なくなり、溝d1〜d4の径方向長さが小さいほど、ランドからべたパターンに移動する熱量が多くなる。本実施の形態において、溝d1〜d4の径方向長さは0.5〔mm〕以上にされる。   The thermal land is used to reduce the amount of heat transferred from the land to the solid pattern by connecting the land and the solid pattern and thermally separating the land and the solid land pattern. The greater the clearance, that is, the larger the radial length of the grooves d1 to d4, the less the amount of heat that moves from the land to the solid pattern, and the smaller the radial length of the grooves d1 to d4, the smaller the distance to the solid pattern that moves. The amount of heat increases. In the present embodiment, the lengths in the radial direction of the grooves d1 to d4 are 0.5 [mm] or more.

したがって、半田の熱量が第3の導電層ε3の配設パターンに伝達されるのを一層抑制することができるので、半田面Sb側から部品面Sa側に向けて溶融させられた半田を一層十分に供給することができ、半田上り不良が発生するのを一層防止することができる。   Therefore, since it is possible to further suppress the amount of heat of the solder from being transferred to the arrangement pattern of the third conductive layer ε3, the solder melted from the solder surface Sb side toward the component surface Sa side can be more sufficiently obtained. Therefore, it is possible to further prevent the occurrence of defective soldering.

ところで、べたパターン以外の太い配線(例えば、パターン幅が1〔mm〕以上)で形成された配線パターンを有する導電層についても、半田面Sb側に形成するのが好ましい。次に、太い配線で形成された配線パターンを半田面Sb側に形成するようにした多層配線基板11について説明する。   By the way, it is preferable that a conductive layer having a wiring pattern formed of a thick wiring (for example, a pattern width of 1 [mm] or more) other than the solid pattern is also formed on the solder surface Sb side. Next, the multilayer wiring substrate 11 in which a wiring pattern formed of thick wiring is formed on the solder surface Sb side will be described.

図7は本発明の実施の形態におけるランド部と第1の導電層の配設パターンとの関係を示す第2の図、図8は本発明の実施の形態におけるランド部と第2の導電層の配設パターンとの関係を示す第2の図、図9は本発明の実施の形態におけるランド部と第3の導電層の配設パターンとの関係を示す第2の図、図10は本発明の実施の形態におけるランド部と第4の導電層の配設パターンとの関係を示す第2の図である。   FIG. 7 is a second view showing the relationship between the land portion and the arrangement pattern of the first conductive layer in the embodiment of the present invention, and FIG. 8 is the land portion and the second conductive layer in the embodiment of the present invention. FIG. 9 is a second view showing the relationship between the land portion and the third conductive layer placement pattern in the embodiment of the present invention, and FIG. It is a 2nd figure which shows the relationship between the land part and arrangement | positioning pattern of a 4th conductive layer in embodiment of invention.

この場合、図示されない電源回路と、多層配線基板11に形成された所定の回路との間にコネクタ21(図2)を配設し、該コネクタ21を介して電力を供給する場合、各リードtuk、tdmのうち、所定のリードを電力供給用の太い配線で形成された配線パターンと接続する必要が生じる。そして、各第1〜第4の導電層εjのうちの、例えば、第3、第4の導電層ε3、ε4のうちの一つの導電層の配設パターンが太い配線で形成され、本実施の形態においては、第4の導電層ε4の配設パターンが太い配線で形成され、前記所定のリードと第4の導電層ε4の配設パターンとが接続される。   In this case, when the connector 21 (FIG. 2) is disposed between a power supply circuit (not shown) and a predetermined circuit formed on the multilayer wiring board 11 and power is supplied through the connector 21, each lead tuk , Tdm, it is necessary to connect a predetermined lead to a wiring pattern formed of a thick wiring for power supply. Then, of each of the first to fourth conductive layers εj, for example, the arrangement pattern of one of the third and fourth conductive layers ε3 and ε4 is formed by a thick wiring, and this embodiment In the embodiment, the arrangement pattern of the fourth conductive layer ε4 is formed by a thick wiring, and the predetermined lead and the arrangement pattern of the fourth conductive layer ε4 are connected.

この場合、第4の導電層ε4の配設パターンは、太い配線で形成されるので、熱容量が大きいが、半田面Sbに近い位置に形成されるので、半田の熱量の多くが第4の導電層ε4の配設パターンに伝達されることはない。したがって、半田面Sb側から部品面Sa側に向けて溶融させられた半田を十分に供給することができ、半田上り不良が発生するのを防止することができる。   In this case, since the arrangement pattern of the fourth conductive layer ε4 is formed of thick wiring, it has a large heat capacity, but is formed at a position close to the solder surface Sb. It is not transmitted to the arrangement pattern of the layer ε4. Therefore, it is possible to sufficiently supply the melted solder from the solder surface Sb side to the component surface Sa side, and it is possible to prevent the occurrence of defective soldering.

このように、第3、第4の導電層ε3、ε4の配設パターンを熱容量の大きい導電層として形成し、最も部品面Sa側の第1の導電層ε1の配設パターンを、熱容量の小さい導電層として形成し、熱容量の大きい導電層として形成しないようにしているので、コネクタ21を多層配線基板11に半田付けする際に、半田の熱量の多くが熱容量の大きい第3、第4の導電層ε3、ε4の配設パターンに伝達されることはない。したがって、半田面側Sbから部品面Sa側に向けて溶融させられた半田を十分に供給することができ、半田上り不良が発生するのを防止することができる。   Thus, the arrangement pattern of the third and fourth conductive layers ε3 and ε4 is formed as a conductive layer having a large heat capacity, and the arrangement pattern of the first conductive layer ε1 on the component surface Sa side is the smallest in the heat capacity. The conductive layer is formed as a conductive layer and is not formed as a conductive layer having a large heat capacity. Therefore, when the connector 21 is soldered to the multilayer wiring board 11, the third and fourth conductive materials having a large amount of heat in the solder have a large heat capacity. It is not transmitted to the arrangement pattern of the layers ε3 and ε4. Therefore, it is possible to sufficiently supply the melted solder from the solder surface side Sb toward the component surface Sa side, and it is possible to prevent the occurrence of a soldering failure.

その結果、振動等が加わることによって断線が発生することがなくなるので、手作業で半田付けを修正する必要がなくなる。また、仮に、手作業で半田付けを修正する必要が生じても、長時間修正作業を行う必要がなくなるので、コネクタ21等の各電子部品の信頼性を向上させることができる。   As a result, disconnection does not occur due to vibration or the like, so there is no need to manually correct the soldering. Further, even if it is necessary to correct the soldering manually, it is not necessary to perform the correction work for a long time, so that the reliability of each electronic component such as the connector 21 can be improved.

本実施の形態においては、第1〜第4の導電層εjの配設パターンのうちの面積が大きく、熱容量の大きい配設パターンが、面積が小さく、熱容量の小さい配設パターンより半田面Sb側で前記ランド16と接続されるようになっているが、第1〜第4の導電層εjのうちの厚い導電層を、薄い導電層より半田面Sb側に配設したり、第1〜第4の導電層εjのうちの熱伝導率の高い導電層を、熱伝導率の低い導電層より半田面Sb側に配設したりすることができる。   In the present embodiment, the arrangement pattern of the first to fourth conductive layers εj having a large area and having a large heat capacity is smaller in the area and having a smaller heat capacity than the arrangement pattern having a small heat capacity. The thick conductive layer of the first to fourth conductive layers εj is disposed closer to the solder surface Sb than the thin conductive layer, or is connected to the land 16. Among the four conductive layers εj, a conductive layer having a high thermal conductivity can be disposed closer to the solder surface Sb than a conductive layer having a low thermal conductivity.

なお、前記熱伝導率は、第1〜第4の導電層εjを構成する材質を異ならせることによって調整され、基準の熱伝導率を有する導電層を銅によって形成したとき、銅より熱伝導率の高い材料を添加することによって導電層の伝導率を高くしたり、銅より熱伝導率の低い材料を添加することによって導電層の伝導率を低くしたりすることができる。   The thermal conductivity is adjusted by changing the materials constituting the first to fourth conductive layers εj, and when the conductive layer having the reference thermal conductivity is formed of copper, the thermal conductivity is higher than that of copper. The conductivity of the conductive layer can be increased by adding a material having a higher conductivity, or the conductivity of the conductive layer can be decreased by adding a material having a lower thermal conductivity than copper.

なお、本発明は前記実施の形態に限定されるものではなく、本発明の趣旨に基づいて種々変形させることが可能であり、それらを本発明の範囲から排除するものではない。   In addition, this invention is not limited to the said embodiment, It can change variously based on the meaning of this invention, and does not exclude them from the scope of the present invention.

本発明の実施の形態における多層配線基板の要部を示す断面図である。It is sectional drawing which shows the principal part of the multilayer wiring board in embodiment of this invention. 本発明の実施の形態におけるコネクタの取付状態を示す断面図である。It is sectional drawing which shows the attachment state of the connector in embodiment of this invention. 本発明の実施の形態におけるランド部と第1の導電層の配設パターンとの関係を示す第1の図である。It is a 1st figure which shows the relationship between the land part in the embodiment of this invention, and the arrangement | positioning pattern of a 1st conductive layer. 本発明の実施の形態におけるランド部と第2の導電層の配設パターンとの関係を示す第1の図である。It is a 1st figure which shows the relationship between the land part in the embodiment of this invention, and the arrangement | positioning pattern of a 2nd conductive layer. 本発明の実施の形態におけるランド部と第3の導電層の配設パターンとの関係を示す第1の図である。It is a 1st figure which shows the relationship between the land part and arrangement | positioning pattern of a 3rd conductive layer in embodiment of this invention. 本発明の実施の形態におけるランド部と第4の導電層の配設パターンとの関係を示す第1の図である。It is a 1st figure which shows the relationship between the land part in the embodiment of this invention, and the arrangement | positioning pattern of a 4th conductive layer. 本発明の実施の形態におけるランド部と第1の導電層の配設パターンとの関係を示す第2の図である。It is a 2nd figure which shows the relationship between the land part and arrangement | positioning pattern of a 1st conductive layer in embodiment of this invention. 本発明の実施の形態におけるランド部と第2の導電層の配設パターンとの関係を示す第2の図である。It is a 2nd figure which shows the relationship between the land part and arrangement | positioning pattern of a 2nd conductive layer in embodiment of this invention. 本発明の実施の形態におけるランド部と第3の導電層の配設パターンとの関係を示す第2の図である。It is a 2nd figure which shows the relationship between the land part in the embodiment of this invention, and the arrangement pattern of the 3rd conductive layer. 本発明の実施の形態におけるランド部と第4の導電層の配設パターンとの関係を示す第2の図である。It is a 2nd figure which shows the relationship between the land part in the embodiment of this invention, and the arrangement | positioning pattern of a 4th conductive layer.

符号の説明Explanation of symbols

11 多層配線基板
15 スルーホール
16 ランド
17 筒状部
21 コネクタ
Bi 第1〜第3の基材
d1〜d4 溝
Lj 第1〜第4のランド部
Sa 部品面
Sb 半田面
εj 第1〜第4の導電層
DESCRIPTION OF SYMBOLS 11 Multilayer wiring board 15 Through hole 16 Land 17 Cylindrical part 21 Connector Bi 1st-3rd base material d1-d4 Groove Lj 1st-4th land part Sa Component surface Sb Solder surface (epsilon) j 1st-4th Conductive layer

Claims (8)

複数の基材と、該各基材に積層させて形成され、所定の配線パターンを有する複数の導電層と、前記基材及び前記導電層を貫通するスルーホールに配設されたランドとを有するとともに、電子部品のリードが前記スルーホールに挿入され、前記リードと前記ランドとが接合材によって接続され、一方の面に前記電子部品を取り付けるための部品面が、他方の面に半田付けを行うための半田面が形成された多層配線基板において、前記配線パターンのうちの熱容量の大きい配線パターンが、熱容量の小さい配線パターンより半田面側で前記ランドと接続されることを特徴とする多層配線基板。   A plurality of base materials, a plurality of conductive layers formed on each base material and having a predetermined wiring pattern, and lands disposed in through holes penetrating the base materials and the conductive layers. At the same time, the lead of the electronic component is inserted into the through hole, the lead and the land are connected by a bonding material, and the component surface for mounting the electronic component on one surface is soldered to the other surface A multilayer wiring board having a solder surface for forming the wiring pattern, wherein a wiring pattern having a large heat capacity among the wiring patterns is connected to the land on the solder surface side of the wiring pattern having a small heat capacity. . 前記配線パターンのうちの面積の大きい配線パターンが、面積の小さい配線パターンより半田面側で前記ランドと接続される請求項1に記載の多層配線基板。   The multilayer wiring board according to claim 1, wherein a wiring pattern having a large area among the wiring patterns is connected to the land on a solder surface side of a wiring pattern having a small area. 前記各導電層のうちの厚い導電層が、薄い導電層より半田面側に配設される請求項1に記載の多層配線基板。   The multilayer wiring board according to claim 1, wherein a thick conductive layer among the conductive layers is disposed closer to a solder surface than a thin conductive layer. 複数の基材と、該各基材に積層させて形成され、所定の配線パターンを有する複数の導電層と、前記基材及び前記導電層を貫通するスルーホールに配設されたランドとを有するとともに、電子部品のリードが前記スルーホールに挿入され、前記リードと前記ランドとが接合材によって接続され、一方の面に前記電子部品を取り付けるための部品面が、他方の面に半田付けを行うための半田面が形成された多層配線基板において、前記配線パターンのうちの熱伝導率の高い配線パターンが、熱伝導率の低い配線パターンより半田面側で前記ランドと接続されることを特徴とする多層配線基板。   A plurality of base materials, a plurality of conductive layers formed on each base material and having a predetermined wiring pattern, and lands disposed in through holes penetrating the base materials and the conductive layers. At the same time, the lead of the electronic component is inserted into the through hole, the lead and the land are connected by a bonding material, and the component surface for mounting the electronic component on one surface is soldered to the other surface In the multilayer wiring board on which the solder surface for forming is formed, the wiring pattern having high thermal conductivity among the wiring patterns is connected to the land on the solder surface side than the wiring pattern having low thermal conductivity. Multilayer wiring board. 前記配線パターンの熱伝導率は、導電層を構成する材質を異ならせることによって調整される請求項4に記載の多層配線基板。   The multilayer wiring board according to claim 4, wherein the thermal conductivity of the wiring pattern is adjusted by changing a material constituting the conductive layer. 前記半田面側で前記ランドと接続される配線パターンは、べたパターンで形成される請求項1〜5のいずれか1項に記載の多層配線基板。   The multilayer wiring board according to claim 1, wherein the wiring pattern connected to the land on the solder surface side is formed as a solid pattern. 前記半田面側で前記ランドと接続される配線パターンは、電力供給用の太い配線で形成される請求項1〜5のいずれか1項に記載の多層配線基板。   The multilayer wiring board according to claim 1, wherein the wiring pattern connected to the land on the solder surface side is formed by a thick wiring for supplying power. 前記ランドと配線パターンとの間に、ランドから配線パターンに伝わる熱量を少なくするための溝が形成される請求項1〜5のいずれか1項に記載の多層配線基板。
The multilayer wiring board according to claim 1, wherein a groove is formed between the land and the wiring pattern for reducing the amount of heat transferred from the land to the wiring pattern.
JP2005206710A 2005-07-15 2005-07-15 Multilayer wiring board Active JP4752367B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005206710A JP4752367B2 (en) 2005-07-15 2005-07-15 Multilayer wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005206710A JP4752367B2 (en) 2005-07-15 2005-07-15 Multilayer wiring board

Publications (2)

Publication Number Publication Date
JP2007027368A true JP2007027368A (en) 2007-02-01
JP4752367B2 JP4752367B2 (en) 2011-08-17

Family

ID=37787755

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005206710A Active JP4752367B2 (en) 2005-07-15 2005-07-15 Multilayer wiring board

Country Status (1)

Country Link
JP (1) JP4752367B2 (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009164404A (en) * 2008-01-08 2009-07-23 Fujitsu Ltd Repair method of electronic component, repair device, and wiring board unit
JP2010109020A (en) * 2008-10-28 2010-05-13 Sumitomo Wiring Syst Ltd Printed board
KR101373963B1 (en) 2011-03-29 2014-03-12 제이엑스 닛코 닛세키 킨조쿠 가부시키가이샤 Method for production of positive electrode active material for a lithium-ion battery and positive electrode active material for a lithium-ion battery
JP2014146619A (en) * 2013-01-25 2014-08-14 Keihin Corp Printed circuit board
WO2015001938A1 (en) * 2013-07-03 2015-01-08 住友電装株式会社 Printed circuit board
WO2017169504A1 (en) * 2016-03-30 2017-10-05 サンデン・オートモーティブコンポーネント株式会社 Multilayered circuit board
WO2023128363A1 (en) * 2021-12-27 2023-07-06 엘지이노텍 주식회사 Motor

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0364990A (en) * 1989-08-02 1991-03-20 Mitsubishi Electric Corp Printed wiring board
JPH08195566A (en) * 1995-01-12 1996-07-30 Hitachi Ltd Multilayer electronic board, method of manufacture and arithmetic processing board
JP2005012088A (en) * 2003-06-20 2005-01-13 Toshiba Corp Multilayered circuit board and electronic equipment

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0364990A (en) * 1989-08-02 1991-03-20 Mitsubishi Electric Corp Printed wiring board
JPH08195566A (en) * 1995-01-12 1996-07-30 Hitachi Ltd Multilayer electronic board, method of manufacture and arithmetic processing board
JP2005012088A (en) * 2003-06-20 2005-01-13 Toshiba Corp Multilayered circuit board and electronic equipment

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009164404A (en) * 2008-01-08 2009-07-23 Fujitsu Ltd Repair method of electronic component, repair device, and wiring board unit
JP2010109020A (en) * 2008-10-28 2010-05-13 Sumitomo Wiring Syst Ltd Printed board
KR101373963B1 (en) 2011-03-29 2014-03-12 제이엑스 닛코 닛세키 킨조쿠 가부시키가이샤 Method for production of positive electrode active material for a lithium-ion battery and positive electrode active material for a lithium-ion battery
JP2014146619A (en) * 2013-01-25 2014-08-14 Keihin Corp Printed circuit board
WO2015001938A1 (en) * 2013-07-03 2015-01-08 住友電装株式会社 Printed circuit board
WO2017169504A1 (en) * 2016-03-30 2017-10-05 サンデン・オートモーティブコンポーネント株式会社 Multilayered circuit board
WO2023128363A1 (en) * 2021-12-27 2023-07-06 엘지이노텍 주식회사 Motor

Also Published As

Publication number Publication date
JP4752367B2 (en) 2011-08-17

Similar Documents

Publication Publication Date Title
US6509530B2 (en) Via intersect pad for electronic components and methods of manufacture
US7087988B2 (en) Semiconductor packaging apparatus
JP4752367B2 (en) Multilayer wiring board
US20020084105A1 (en) Via -in-pad with off-center geometry and methods of manufacture
TWI430724B (en) Connection structure between printed circuit board and electronic component
WO2016181628A1 (en) Printed-wiring board, printed-circuit board and electronic apparatus
JP2011071220A (en) Ceramic capacitor with metal terminal, and method of manufacturing the same
US7968800B2 (en) Passive component incorporating interposer
JP2005129663A (en) Multilayer circuit board
JP2009206327A (en) Wiring structure and multilayer printed wiring board
JP2007294735A (en) Mounting substrate
US11096285B2 (en) Electronic circuit substrate
US20050253258A1 (en) Solder flow stops for semiconductor die substrates
CN115066985A (en) Wiring board
JP4760393B2 (en) Printed wiring board and semiconductor device
JP3959266B2 (en) Wiring board
JP2007027242A (en) Substrate
JP2019125746A (en) Electronic component mounting substrate, circuit board, and manufacturing method of electronic component mounting substrate
JP2006173337A (en) Electronic module structure
JP2007258654A (en) Circuit board land connection method and the circuit board
JP6487315B2 (en) Electronic control unit
JP2023161397A (en) circuit board
JP2022122467A (en) printed wiring board
JP2024507296A (en) Thermally modified PCBs for power semiconductor die connected by via technology and assemblies using such PCBs
JP2020155694A (en) Double-sided wiring board

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20071107

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20100512

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100518

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110201

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110401

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20110426

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20110509

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140603

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Ref document number: 4752367

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150