JP2007026592A - Data reproducing circuit and data reproducing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To simplify the configuration of an adaptive equalizer in each processing system and to reduce a circuit scale when performing reproduced data parallelly in a plurality of processing systems. <P>SOLUTION: Tap values of digital equalizers 511 and 521 are updated by a common tap value updating part 518. Equalization errors e<SB>1</SB>(n) and e<SB>2</SB>(n) that occur in adaptive equalizers 51 and 52 are added by an adding part 514 and multiplied by an adjustment factor μ by a ratio adjusting part 515. On the other hand, sets X<SB>1</SB>(n) and and X<SB>2</SB>(n) of resample data input from the digital equalizers 511 and 521 are added by an adding part 516 to generate a set X(n). Then, μ e(n) output from the ratio adjusting part 515 is multiplied by the set X(n) by a multiplying part 517. The tap value updating part 518 adds μe(n)X(n) to the present tap value H(n) to generate a tap value H(n+1) of the next clock timing. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a data reproduction circuit and a data reproduction device, and is particularly suitable for use in performing waveform equalization processing in parallel using a plurality of adaptive waveform equalizers (Adaptive Equalizers). .

  In a high-density optical disc such as a DVD (Digital Versatile Disc) or a next-generation DVD, a so-called intersymbol interference phenomenon occurs in which signals before and after interfere with each other during reproduction. In order to solve such a problem, in a drive apparatus that handles these discs, a waveform equalizer (equalizer) is arranged in the reproduction transmission path to improve the frequency characteristics of the reproduction signal.

  However, in these high-density optical discs, the frequency characteristics of the reproduction signal are different for each disc or each manufacturer. Therefore, if equalization processing is performed on these discs uniformly, an equalization error occurs between the discs. Causes a problem that the error rate increases. Therefore, in order to solve this problem, an adaptive equalizer that can adjust the equalization coefficient appropriately according to the frequency characteristics of the reproduction signal of each disk has been used recently.

  FIG. 8 shows an example of the configuration of a disc playback apparatus using an adaptive equalizer.

  Data recorded on the disk 1 is read by the optical pickup 2. The optical pickup 2 receives reflected light from the disk 1 with a photodetector to generate a reproduction RF signal, and outputs the generated reproduction RF signal to the amplifier circuit 10.

  The amplifier circuit 10 amplifies the reproduction RF signal supplied from the optical pickup 2 and outputs the amplified signal to the analog BPF 20. The analog BPF 20 removes the noise component of the reproduction RF signal and outputs it to the ADC 30. The ADC 30 samples the reproduction RF signal according to a fixed clock (frequency: f1), converts the sample value into digital data, and outputs the digital data to the digital PLL 40.

  The digital PLL 40 performs interpolation processing on the digital data input from the ADC 30 to generate digital data (resampled data) at an appropriate sampling timing, and outputs the generated resampled data to the adaptive equalizer 50.

  The adaptive equalizer 50 performs waveform equalization processing on the resampled data supplied from the digital PLL 40 and outputs the result to the binarization circuit 60. The binarization circuit 60 decodes the resampled data supplied from the digital equalizer 50 to generate and output binary data of 1 and 0. Here, the binarization circuit 60 performs, for example, a Viterbi decoding process as the decoding process.

  FIG. 9 shows a configuration example of the adaptive equalizer 50.

  The adaptive equalizer 50 includes a digital equalizer 501, an ideal sample value calculation unit 502, a subtraction unit 503, a ratio adjustment unit 504, a multiplication unit 505, and a tap value update unit 506.

  The digital equalizer 501 performs waveform equalization processing on the resampled data input from the digital PLL 40 according to the tap value updated by the tap value update unit 505.

  The ideal sample value calculation unit 502 outputs the ideal sample value p (n) of the resampled data q (n) after waveform equalization output from the digital equalizer 501, and the binarized data output from the binarization circuit 60. Generate based on

  The subtraction unit 503 subtracts the resampled data q (n) waveform-equalized by the digital equalizer 501 from the ideal sample value p (n) generated by the ideal sample value calculation unit 502, and the subtraction result e ( n) is output to the adjustment unit 504.

  The ratio adjustment unit 504 multiplies the subtraction result e (n) input from the subtraction unit 503 by the adjustment coefficient μ and outputs the multiplication result to the multiplication unit 505.

  The multiplication unit 505 uses the subtraction result μ · e (n) whose ratio is adjusted by the ratio adjustment unit 504 as a set of resampled data X (n) = (x (n), x () input from the digital equalizer 501. n−1),..., x (n−k + 1)) and outputs the result to the tap value update unit 506. Note that x (n−k) is resample data that arrives before the k resample timing from the resample data x (n).

  The tap value updating unit 506 adds the multiplication result μ · e (n) · from the multiplication unit 505 to the current tap value H (n) = (h1 (n), h2 (n),..., Hk (n)). X (n) is added to generate tap values H (n + 1) = (h1 (n + 1), h2 (n + 1),..., Hk (n + 1)) at the next clock timing. Then, the generated tap value H (n + 1) is supplied to the digital equalizer 501.

  FIG. 10 shows a configuration example of the digital equalizer 501.

  The resample data input to the digital equalizer 501 is delayed by one resample timing by the k−1 delay units 501a. Resampled data at each sample timing is multiplied by tap values h1 (n), h2 (n),..., Hk (n) in the corresponding multipliers 501b, and then added in the adder 501c. The

Tap values h1 (n), h2 (n),..., Hk (n) multiplied by the multiplication unit 501b are updated by the tap value update unit 506. That is, tap values h1 (n + 1), h2 (n + 1),..., Hk (n + 1) at the next resample timing are the subtraction result e (n) in the subtraction unit 503, the coefficient μ in the ratio adjustment unit 504, and , H1 (n + 1) = h1 (n) + μ · e (n) · x (n) from resampled data x (n), x (n−1),..., X (n−k + 1), respectively. , H2 (n + 1) = h2 (n) + μ · e (n) · x (n−1),..., Hk (n + 1) = hk (n) + μ · e (n) · x (n−k + 1) Is done. By this update, the tap value of the digital equalizer 501 is adjusted as appropriate, and waveform equalization processing according to the frequency characteristics of the disc is performed.
Japanese Patent Laid-Open No. 10-261205 JP 2000-182330 A JP 2000-199753 A

  2. Description of the Related Art In recent years, optical discs and drive devices thereof have been demanded to increase the reproduction speed (4 × speed, 8 × speed, etc.) as well as increase the density and capacity of the disc. Increasing the reproduction speed gives high added value particularly when a drive device is used for PC (Personal Computer) applications.

  As means for realizing a high reproduction speed, parallel processing of reproduction data can be an effective means. That is, a plurality of processing systems for processing reproduction data are prepared, and a series of reproduction data is processed in each processing system alternately in time series. This makes it possible to increase the playback speed and double the speed without increasing the processing speed of each processing system. Such parallel processing is also required for processing in an adaptive equalizer.

Therefore, when preparing a plurality of processing systems and increasing the reproduction speed in this way, the present invention can appropriately simplify the configuration of the adaptive equalizer and reduce the circuit scale in each processing system. It is an object of the present invention to provide a data reproduction circuit and a data reproduction device.

  According to a first aspect of the present invention, in the data reproduction circuit, a plurality of adaptive equalizers in which reproduction data is sequentially distributed and supplied for each predetermined data unit, and a coefficient setting circuit for setting a coefficient for waveform equalization in the adaptive equalizer One coefficient setting circuit corresponding to two or more adaptive equalizers among the plurality of adaptive equalizers, and the coefficient setting circuit generates the coefficient common to the corresponding adaptive equalizers. Thus, these adaptive equalizers are set.

  According to a second aspect of the present invention, in the data recovery circuit according to the first aspect, the coefficient setting circuit generates the coefficient based on a waveform equalization error generated in a preset adaptive equalizer among the corresponding adaptive equalizers. The generated coefficients are set in all corresponding adaptive equalizers.

  A third invention is the data reproduction circuit according to the second invention, wherein the coefficient setting circuit generates the coefficient based on a waveform equalization error generated in each of the corresponding adaptive equalizers, and the generated coefficient is It is characterized in that it is set for each of all corresponding adaptive equalizers.

  According to a fourth invention, in the data reproduction circuit according to the second invention, the coefficient setting circuit generates the coefficient based on a waveform equalization error generated in any one of the corresponding adaptive equalizers, The generated coefficient is set in each of the corresponding adaptive equalizers.

  According to a fifth aspect of the present invention, in the data reproduction circuit according to any one of the first to fourth aspects, the coefficient setting circuit includes a circuit for obtaining an ideal value of the reproduction data, and the ideal value obtained by the circuit The waveform equalization error is obtained by comparing the data value after waveform equalization.

A sixth invention is a data reproducing device comprising a data reproducing circuit according to any one of the first to fifth inventions.

  According to the present invention, since one coefficient setting circuit is arranged for a plurality of adaptive equalizers, the configuration is simplified and the circuit scale is compared with the case where the coefficient setting circuits are individually arranged for each adaptive equalizer. Can be reduced.

  At this time, if the coefficient is generated based on the waveform equalization error generated in each corresponding adaptive equalizer as in the third invention, the waveform equalization error generated in each adaptive equalizer is integrated. Can be reflected in the coefficient. This makes it possible to perform coefficient adjustment that closely follows the waveform equalization error.

  Further, if the coefficient is generated based on the waveform equalization error generated in any one of the corresponding adaptive equalizers as in the fourth invention, the waveform equalization error in the one adaptive equalizer is generated. Therefore, the configuration can be further simplified.

  The features of the present invention will become more apparent from the following description of embodiments.

  In the following embodiment, an embodiment in which parallel processing is performed using two adaptive equalizers is shown. In the following embodiments, the coefficient setting circuit according to the present invention includes ideal sample value calculation units 512 and 522, subtraction units 513 and 523, an addition unit 514, a ratio adjustment unit 515, an addition unit 516, a multiplication unit 517, and a tap. It is embodied in the value update unit 518.

However, the following embodiment is merely an example for embodying the present invention, and the meaning of the term of the present invention or each constituent element is limited to that described in the following embodiment. Is not to be done.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 shows a configuration of a disc reproducing apparatus according to the embodiment. The same parts as those of the configuration of FIG. 8 shown in the above conventional example are denoted by the same reference numerals, and the description thereof is omitted.

  In the figure, a memory 70 sequentially stores digital data input from the ADC 30 under the control of the memory controller 80. The stored digital data is output to either the digital PLL 41 or the digital PLL 42 for each predetermined data unit.

  The memory controller 80 performs write control on the memory 70 and performs read control on the memory 70 in response to a command from the timing controller 90.

  The timing controller 90 outputs a command defining the digital data read timing to the digital PLLs 41 and 42 to the memory controller 80, and the first signal processing including the digital PLL 41, the adaptive equalizer 51, and the binarization circuit 61. A command for defining the operation timing is output to the second signal processing system including the system, the digital PLL 42, the adaptive equalizer 52, and the binarization circuit 62. Further, the timing controller 90 includes binarized data input from the first signal processing system (binarization circuit 61) and binarized data input from the second signal processing system (binarization circuit 62). A command for defining the data selection timing for selecting either one of them to make a system is output to the selector 100.

  The selector 100 buffers the binarized data input from the first signal processing system and the second processing system, and selects one of the data in response to a command from the timing controller 90, and selects these data. One system is made and output to a subsequent circuit (demodulation circuit, etc.).

  A first signal processing system composed of a digital PLL 41, an adaptive equalizer 51 and a binarization circuit 61, and a second signal processing system composed of a digital PLL 42, an adaptive equalizer 52 and a binarization circuit 62 are: Processing similar to that of the signal processing system including the digital PLL 40, the adaptive equalizer 50, and the binarization circuit 60 in FIG. 8 is performed. However, the tap values of the adaptive equalizers 51 and 52 are updated by a common tap value update unit.

  In the present embodiment, as will be described later, signal processing is performed in parallel by the first signal processing system and the second signal processing system. Therefore, the first signal processing system and the second signal processing system can be operated with an operation clock having a frequency several stages lower than the fixed clock for A / D sampling. That is, the frequency f2 of the operation clock input to the first signal processing system and the second signal processing system is f2 <f1 compared to the frequency f1 of the fixed clock. The frequency f2 of the operation clock can be a little over f1 / 2 at the lowest.

  FIG. 2 shows the configuration of the adaptive equalizers 51 and 52.

  As shown in the figure, the adaptive equalizer 51 arranged on the first signal processing system side includes a digital equalizer 511, an ideal sample value calculation unit 512, a subtraction unit 513, an addition unit 514, a ratio adjustment unit 515, An adder 516, a multiplier 517, and a tap value updater 518 are provided. The adaptive equalizer 52 arranged on the second signal processing system side includes a digital equalizer 521 and an ideal sample value calculation unit 522.

  The digital equalizers 511 and 521 perform waveform equalization processing on the resampled data input from the digital PLLs 41 and 42 according to the tap value updated by the tap value update unit 518.

The ideal sample value calculation units 512 and 522 are ideal sample values p ₁ (n) and p ₂ of the resampled data q ₁ (n) and q ₂ (n) after waveform equalization output from the digital equalizers 511 and 521, respectively. (N) is generated based on the binarized data output from the binarization circuits 61 and 62.

Subtraction units 513 and 523 resample the waveform equalized by digital equalizers 511 and 521 from ideal sample values p ₁ (n) and p ₂ (n) generated by ideal sample value calculation units 512 and 522, respectively. The data q ₁ (n) and q ₂ (n) are subtracted and the subtraction results e ₁ (n) and e ₂ (n) are output to the adder 514.

The adder 514 adds the subtraction results e ₁ (n) and e ₂ (n) input from the subtractors 513 and 523 and outputs the result to the ratio adjuster 515.

  The ratio adjustment unit 515 multiplies the addition result e (n) input from the addition unit 514 by the adjustment coefficient μ and outputs the multiplication result to the multiplication unit 517.

The adder 516 includes a set of resampled data X ₁ (n) = (x ₁ (n), x ₁ (n−1),..., X ₁ (n−k + 1)) input from the digital equalizer 511, A set X ₂ (n) = (x ₂ (n), x ₂ (n−1),..., X ₂ (n−k + 1)) of resampled data input from the digital equalizer 512 is added to obtain a set X (N) = (x ₁ (n) + x ₂ (n), x ₁ (n−1) + x ₂ (n−1),..., X ₁ (n−k + 1) + x ₂ (n−k + 1)) To do.

The multiplication unit 517 converts the μ · e (n) input from the ratio adjustment unit 515 into a set X (n) = (x ₁ (n) + x ₂ (n), x ₁ (n) input from the addition unit 516. −1) + x ₂ (n−1),..., X ₁ (n−k + 1) + x ₂ (n−k + 1)), and outputs the result to the tap value update unit 518.

  The tap value update unit 518 adds the current tap value H (n) = (h1 (n), h2 (n),..., Hk (n)) set in the digital equalizers 511 and 521 from the multiplication unit 517. And the tap values H (n + 1) = (h1 (n + 1), h2 (n + 1),..., Hk (n + 1)) at the next clock timing are added. Generate. Then, the generated tap value H (n + 1) is supplied to the digital equalizers 511 and 521.

Here, tap values h1 (n + 1), h2 (n + 1),..., Hk (n + 1) at the next resample timing are the addition result e (n) in the adder 514, the coefficient μ in the ratio adjuster 515, And a set X (n) = (x ₁ (n) + x ₂ (n), x ₁ (n−1) + x generated by adding the resampled data sets X ₁ (n) and X ₂ (n) _{2 (n-1), ...} , x 1 from (n-k + 1) + x 2 (n-k + 1)), respectively, h1 (n + 1) = h1 (n) + μ · e (n) · (x 1 (n) + X ₂ (n)), h2 (n + 1) = h2 (n) + μ · e (n) · (x ₁ (n−1) + x ₂ (n−1)),..., Hk (n + 1) = hk (n ) + Μ · e (n) · (x ₁ (n−k + 1) + x ₂ (n−k + 1)).

  Next, parallel processing in the first processing system and the second processing system will be described with reference to FIGS.

  In the following, a set of AD data of a certain size processed in each processing system is referred to as a data unit. For convenience, each data unit is provided with a symbol (n) for indicating a processing order. In the following, the digital PLL 41 in the first processing system is indicated as D-PLL (1), and the digital PLL 42 in the second processing system is indicated as D-PLL (2).

  When data reading from the disk 1 is started, the reproduction RF signal is sequentially A / D converted, and data writing to the memory 70 is started as shown in FIG. When a certain amount of data is stored in the memory 70 by such writing, the AD data of the data unit (0) is sequentially output from the memory 70 to the D-PLL (1), and processing by the first processing system is started. The

  Thereafter, when a certain amount of data is further written in the memory 70, the AD data of the data unit (1) following the data unit (0) is sequentially transferred from the memory 70 as shown in (2) of FIG. 2), and the processing by the second processing system is started. At this time, the AD data of the data unit (0) is continuously output to the D-PLL (1) and processed in parallel by the first processing system. The AD data of the data unit (0) is sequentially output to the D-PLL (1) and processed until all the AD data of the unit is processed as shown in (3) of FIG.

  Then, when the processing for the AD data of the data unit (0) is completed, as shown in (4) of FIG. 4, a part of the data unit (1) is used as a run-up period of processing for the next data unit (2). The data is output from the memory 70 to the D-PLL (1) and processed by the first processing system. The processing in the run-up period is performed using, for example, AD data at the end of the data unit (1). By the processing in the run-up period, phase pull-in in D-PLL (1) is performed, and processing for the next data unit (2) is stably performed. At this time, the processing of the second processing system for the data unit (1) is performed in parallel.

  When this run-up period ends, as shown in (5) of FIG. 4, the AD data of the data unit (2) is sequentially output from the memory 70 to the D-PLL (1), and the processing by the first processing system is started. The At this time, the AD data of the data unit (1) is continuously output to the D-PLL (2) and processed in parallel by the second processing system. This parallel processing is performed until the processing for the data unit (1) is completed as shown in (6) of FIG.

  When the processing for the AD data of the data unit (1) is completed, as shown in (7) of FIG. 5, a part of the data unit (2) is used as a running period for the processing for the next data unit (3). The data is output from the memory 70 to the D-PLL (2) and processed by the second processing system. As described above, the processing in the run-up period is performed using, for example, AD data at the end of the data unit (2). By the processing in the run-up period, phase pull-in in the D-PLL (2) is performed, and processing for the next data unit (3) is stably performed. At this time, the processing of the first processing system for the data unit (2) is performed in parallel.

  When this run-up period ends, as shown in (8) of FIG. 5, the AD data of the data unit (3) is sequentially output from the memory 70 to the D-PLL (2), and the processing by the second processing system is started. The At this time, the AD data of the data unit (2) is continuously output to the D-PLL (1) and processed in parallel by the first processing system. This parallel processing is performed until the processing for the data unit (2) is completed as shown in (9) of FIG.

  Thereafter, parallel processing in the first processing system and the second processing system is performed in the same manner. Thereafter, when the AD data is written up to the final address of the memory 70, the AD data is sequentially overwritten by returning to the head address. Similarly, when processing is performed up to a predetermined address in the memory 70 by parallel processing in the first processing system and the second processing system, the processing returns to the top address and parallel processing is performed on the overwritten AD data.

In such parallel processing, the tap values applied to the digital equalizer 511 of the first processing system and the digital equalizer 512 of the second processing system are both tap value updating units 518 arranged on the first processing system side. Adjusted by. As described above, this adjustment is performed by the amount of deviation e ₁ (n) between the resampled data after waveform equalization on the first processing system side and the ideal sample value, and after waveform equalization on the second processing system side. This is performed based on a value e (n) obtained by adding a deviation amount e ₂ (n) between the resampled data and the ideal sample value.

As described above, according to the present embodiment, since the configuration for updating the tap value is shared by the first and second processing systems, the configuration for updating the tap value is individually allocated to each processing system. Compared to the case, the configuration can be simplified and the circuit scale can be reduced. Also, the deviation e ₁ (n) between the resampled data after waveform equalization detected on the first processing system side and the ideal sample value, and the waveform equalization detected on the second processing system side Since the tap value is updated based on the value e (n) obtained by adding the deviation e ₂ (n) between the resampled data and the ideal sample value, the tap value closely follows the waveform equalization error. Adjustment can be realized.

  In addition, this invention is not limited to the said embodiment, A various change is possible for others.

For example, in the above embodiment, the shift amount e ₁ (n) between the resampled data after waveform equalization detected on the first processing system side and the ideal sample value is detected on the second processing system side. The tap value is updated based on the value e (n) obtained by adding the deviation e ₂ (n) between the resampled data after waveform equalization and the ideal sample value. It is also possible to update the tap value using only the deviation amount detected in the processing system.

FIG. 6 shows a configuration example in such a case. In the figure, the tap value is updated based on the the deviation amount e ₁ (n) of detection by the first processing system.

In this case, the subtraction result e ₁ (n) in the subtraction unit 513 is subjected to the ratio adjustment by the ratio adjustment unit 515 and then the set of resampled data X ₁ (n) = (x ₁ (n) input from the digital equalizer 511. ), X ₁ (n−1),..., X ₁ (n−k + 1)) and is input to the tap value update unit 518. The tap value updating unit 518 adds the multiplication result μ · e ₁ (multiplied by the multiplication unit 517 to the current tap value H (n) = (h1 (n), h2 (n),..., Hk (n)). n) · X ₁ (n) is added to generate tap values H (n + 1) = (h1 (n + 1), h2 (n + 1),..., hk (n + 1)) at the next clock timing. Then, the generated tap value H (n + 1) is supplied to the digital equalizers 511 and 512.

In this case, tap values h1 (n + 1), h2 (n + 1),..., Hk (n + 1) at the next resample timing are the subtraction result e ₁ (n) in the subtraction unit 513 and the coefficient μ in the ratio adjustment unit 515, From the resampled data x ₁ (n), x ₁ (n−1),..., X ₁ (n−k + 1) from the digital equalizer 511, h1 (n + 1) = h1 (n) + μ · e ₁ (N) · x ₁ (n), h2 (n + 1) = h2 (n) + μ · e ₁ (n) · x ₁ (n−1),..., Hk (n + 1) = hk (n) + μ · e ₁ (N) · x ₁ (n−k + 1).

According to this modification, as compared to the configuration shown in FIG. 2, can be omitted configuration and for detecting a deviation amount e ₂ (n), the configuration to reflect the deviation amount e ₂ (n) to the tap value update Therefore, it is possible to further simplify the configuration and reduce the circuit scale.

  In the above embodiment, the digital PLL is arranged in each of the first processing system and the second processing system. However, as shown in FIG. 7, for example, an analog PLL 43 is arranged in the preceding stage of the memory 70. It can also be configured.

  In the configuration of FIG. 7, the analog PLL 43 detects the phase difference between the sampling timing based on the PLL clock and the appropriate sampling timing relative to the reproduction RF signal based on the signal input from the analog BPF 20, and the PLL clock so as to eliminate this phase difference. Adjust the frequency. That is, the edge of the reproduction signal waveform is determined based on the signal input from the analog BPF 20, and the phase difference between this edge and the PLL clock is detected. Then, this phase difference is supplied as a voltage value to a VCO (Voltage Controlled Oscillator), and the period of the PLL clock oscillated from the VCO is changed.

  The ADC 30 performs sampling and A / D conversion on the reproduction RF signal supplied from the analog BPF 20 in accordance with the PLL clock supplied from the analog PLL 43, performs sampling, and sequentially writes AD data to the memory 70.

  The memory 70 sequentially outputs the stored AD data to either the adaptive equalizer 51 or 52 in units of data in accordance with control from the memory controller 80. Hereinafter, the processing after the adaptive equalizers 51 and 52 is performed in the same manner as in the above embodiment.

  Furthermore, in the above embodiment, the signal processing systems from the digital PLL to the binarization circuit are two systems, but it is also possible to prepare three or more signal processing systems and perform parallel processing. In this way, it becomes possible to cope with further increase in reproduction speed / double speed.

  In this case, when the tap value applied to each adaptive equalizer follows the configuration example of FIG. 2, the deviation ei (n) with respect to the ideal sample value detected by each adaptive equalizer is shown in FIG. 2 is added to the tap value update unit 518 by adding the resampled data set Xi (n) from the digital equalizer of each series to the adder 516 in FIG. Generated. In this case, the adder 514 and the adder 516 add the set deviation amount and the resample data set in advance without adding the deviation amounts and resample data sets of all the sequences. It can also be.

  In the case of following the configuration example of FIG. 6 described above, the tap value obtained in any one series is set in common to the digital equalizers in each series.

  In addition, in the above-described embodiment, the data is buffered by the selector 100 and sequentially read out so that the data is integrated into one system. However, the data is written back to another area of the memory 70, and sequentially from here. Data can be integrated into one system by reading.

The embodiment of the present invention can be appropriately modified in various ways within the scope of the technical idea shown in the claims.

The figure which shows the structure of the disc reproducing | regenerating apparatus concerning embodiment The figure which shows the structure of the adaptive equalizer which concerns on embodiment The figure explaining the flow of parallel processing concerning an embodiment The figure explaining the flow of parallel processing concerning an embodiment The figure explaining the flow of parallel processing concerning an embodiment The figure which shows the example of a change of the adaptive equalizer which concerns on embodiment The figure which shows the example of a change of the disc reproducing | regenerating apparatus concerning embodiment The figure which shows the structure of the disc player concerning a prior art example The figure which shows the structure of the adaptive equalizer which concerns on a prior art example The figure which shows the structure of the digital equalizer which concerns on a prior art example

Explanation of symbols

51, 52 ... Adaptive equalizer 511, 521 ... Digital equalizer 512, 522 ... Ideal sample value calculation unit 513, 523 ... Subtraction unit 514 ... Addition unit 515 ... Ratio adjustment unit 516 ... Addition unit 517 ... Multiplication unit 518 ... Tap value update Part

Claims (10)

A plurality of adaptive equalizers in which reproduction data is sequentially distributed and supplied by predetermined data units, and a coefficient setting circuit for setting coefficients for waveform equalization in the adaptive equalizers,
One coefficient setting circuit is arranged corresponding to two or more adaptive equalizers among the plurality of adaptive equalizers, and the coefficient setting circuit generates the coefficients common to the corresponding adaptive equalizers and adapts them. Set to type equalizer,
A data reproduction circuit characterized by the above. The data reproduction circuit according to claim 1, wherein
The coefficient setting circuit generates the coefficient based on a waveform equalization error generated in a preset adaptive equalizer among the corresponding adaptive equalizers, and sets the generated coefficient in all corresponding adaptive equalizers. ,
A data reproduction circuit characterized by the above. The data reproduction circuit according to claim 2, wherein
The coefficient setting circuit generates the coefficient based on a waveform equalization error occurring in each corresponding adaptive equalizer, and sets the generated coefficient in all corresponding adaptive equalizers,
A data reproduction circuit characterized by the above. The data reproduction circuit according to claim 2, wherein
The coefficient setting circuit generates the coefficient based on a waveform equalization error occurring in any one of the corresponding adaptive equalizers, and sets the generated coefficient to all corresponding adaptive equalizers,
A data reproduction circuit characterized by the above. In the data reproduction circuit according to any one of claims 1 to 4,
The coefficient setting circuit includes a circuit for obtaining an ideal value of the reproduction data, and compares the ideal value obtained by the circuit with a data value after waveform equalization to obtain the waveform equalization error.
A data reproduction circuit characterized by the above. A plurality of adaptive equalizers in which reproduced data is sequentially distributed and supplied by predetermined data units, and a coefficient setting circuit for setting coefficients for waveform equalization in the adaptive equalizers,
One coefficient setting circuit is arranged corresponding to two or more adaptive equalizers among the plurality of adaptive equalizers, and the coefficient setting circuit generates the coefficients common to the corresponding adaptive equalizers and adapts them. Set to type equalizer,
A data reproducing apparatus characterized by that. The data reproducing apparatus according to claim 6, wherein
The coefficient setting circuit generates the coefficient based on a waveform equalization error generated in a preset adaptive equalizer among the corresponding adaptive equalizers, and sets the generated coefficient in all corresponding adaptive equalizers. ,
A data reproducing apparatus characterized by that. The data reproducing apparatus according to claim 7, wherein
The coefficient setting circuit generates the coefficient based on a waveform equalization error occurring in each corresponding adaptive equalizer, and sets the generated coefficient in all corresponding adaptive equalizers,
A data reproducing apparatus characterized by that. The data reproducing apparatus according to claim 7, wherein
The coefficient setting circuit generates the coefficient based on a waveform equalization error occurring in any one of the corresponding adaptive equalizers, and sets the generated coefficient to all corresponding adaptive equalizers,
A data reproducing apparatus characterized by that. In the data reproducing device according to any one of claims 6 to 9,
The coefficient setting circuit includes a circuit for obtaining an ideal value of the reproduction data, and compares the ideal value obtained by the circuit with a data value after waveform equalization to obtain the waveform equalization error.
A data reproducing apparatus characterized by that.

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