JP2007026365A - Memory controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform efficient priority control over memory access by a memory controller in a computer system in which a plurality of processing units share a single or a plurality of memories. <P>SOLUTION: The memory controller has a reorderable memory access command issue queue and a priority address setting register inside. The memory access command issue queue is reordered based upon priority address settings to determine the order of access to a main storage. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a memory controller in a computer system in which a plurality of masters share a single memory or a plurality of memories, and relates to an access priority control method between a plurality of masters or within a single master.

  FIG. 2 is a block diagram of a system for controlling memory access from a plurality of masters by a conventional memory controller. Reference numeral 1 denotes an ASIC (Application Specific Integrated Circuit), and the memory 2 is, for example, a large capacity DRAM (Dynamic Random Access Memory). The ASIC 1 and the memory 2 are connected by a three memory bus. The ASIC 1 includes four memory controllers, a plurality of processing units 7-0 to 7-n, and a shared bus 5 that connects the memory controller and the plurality of processing units. The memory controller 4 has a memory access command issue queue 6 inside. Memory access requests from the processing units (7-0 to 7-n) are transmitted to the memory controller 4 via the shared bus 5. When there are simultaneous access requests from a plurality of processing units, the shared bus 5 arbitrates access requests from the processing units (7-0 to 7-n). This access request is temporarily held in the memory access command issue queue 6. The memory access command in the memory access command issue queue is reordered according to the state of the memory bus 3 and the contents of the memory access command held in the memory access command issue queue 6, and the head in the command issue queue The memory access command at is issued to the memory 2. The command issue queue is usually designed to maximize the memory bandwidth.

Further, the number of processing units mounted on the ASIC 1 is increasing with the progress of semiconductor processes. On the other hand, the memory 2 that can be connected to the outside of the ASIC 1 is limited due to restrictions on the semiconductor package, and the number of processing units sharing one memory is increasing.
Moreover, as a prior art example, patent document 1, patent document 2, and patent document 3 can be mention | raise | lifted, for example.
Japanese Patent Laid-Open No. 11-53257 JP 2004-355435 A Japanese Patent Laid-Open No. 2001-34530

  In a computer system including a plurality of processing units, when the real time property of an application program becomes a problem, it is necessary to set the priority order of memory access from the plurality of processing units by software.

  By giving priority to a specific processing unit, it is possible to set the priority of memory access. However, when multiple processing units are mounted in the same ASIC, it becomes difficult to set the priority order of memory access according to the priority order of applications executed by each CPU.

  Further, if priority setting is performed without limiting processing units by arbitration such as round robin on a bus connecting the memory controller and the processing units, it becomes difficult to guarantee real-time performance.

  Also, even when proper prioritization is made on the shared bus, it is reordered to maximize bandwidth when input to a memory controller that is intended to maximize bandwidth, It may be difficult to ensure real-time performance.

  Furthermore, because of load distribution, there is no method for giving priority to a corresponding processing unit group when processing is distributed among specific processing unit groups, and it is difficult to guarantee real-time performance.

  An object of the present invention is to measure improvements made in real time in an ASIC or multiprocessor computer system equipped with a plurality of processing units.

  In order to solve such a problem, a feature of the invention described in claim 1 of the present invention is that a memory controller for controlling memory access from a plurality of processing units has means for holding a priority address area set by software. And a memory access command issue queue capable of reordering memory access commands based on the priority address area.

  According to a second aspect of the present invention, there is provided an exclusive control mechanism for setting a priority address based on the master ID and the valid bit, wherein the means for holding the priority address area holds the master ID in which the priority address is set and the effective bit for setting the priority address. It is in the point.

  According to a third aspect of the present invention, the means for holding the priority address area holds the priority of each priority address, and the reorderable memory access command issue queue is reordered based on each priority address and its priority. It is in the point where a ring is possible.

  The feature of the invention described in claim 4 is that the features of claim 2 and claim 3 are provided.

  According to a fifth aspect of the present invention, the memory controller according to any one of the first to fourth aspects is provided with a reordering execution enable function based on a priority address.

  The feature of the invention described in claim 6 is that an element having a function of the memory controller is incorporated in the computer system.

  As is apparent from the above description, according to the present invention, it is possible to set the memory access priority based on the processing priority and the used address area of each processing unit including the CPU, and the memory access priority according to the processing content. Can be set easily.

  Further, even when processing is shared and executed by a plurality of CPUs or a plurality of processing units, the priority order of memory access can be easily set by specifying the used address space and setting it in the priority address setting register.

  Furthermore, in the case of an access where the memory bandwidth is important, the memory bandwidth can be prioritized by invalidating the reordering by the priority address setting.

  Embodiments of the present invention will be described below with reference to the drawings.

(First embodiment)
FIG. 1 shows an embodiment of the present invention. Reference numeral 10 denotes an ASIC (Application Specific Integrated Circuit), and 11 denotes a memory. The ASIC 10 and the memory 11 are connected by a memory bus 12. The ASIC 10 includes 13 memory controllers, 19-1 to 19-n CPUs, 20-1 to 20-n processing units, and a shared bus 18 that connects the memory controller, the CPU, and the processing units. The memory controller 13 has a memory access command issue queue 14 and a priority address holding register 15 inside. Further, the memory access command issuance queue includes 17-1 to 17-n queues for holding memory access commands and a queue reordering control unit 16. The CPU (19-1 to 19-n) can access the priority address holding register (15) via the internal path (18) and update the register information. Memory access requests from the processing units (20-1 to 20-n) and the CPUs (19-1 to 19-n) are transmitted to the memory controller (13) via the shared bus (18). When there are simultaneous access requests from a plurality of processing units and a plurality of CPUs, access requests from the processing units (10-1 to 10-n) and CPUs (19-1 to 19-n) are shared on the shared bus (18). Mediation takes place. This access request is temporarily held in the access command queue (17-1 to 17-n) in the memory access command issue queue (14).

  The priority address holding register 15 has a configuration indicating the start and end point of the priority address as shown in FIG. 3, or a configuration indicating the start and range of the priority address as shown in FIG.

  The memory access command is registered in the memory access command issue queue (14) based on the flow of FIG. If the address of the request command does not correspond to the setting of the priority address register (15), the request command is added to the end of the registered command. When the address of the request command corresponds to the setting of the priority address setting register (15), the command corresponding to the setting of the priority setting register (15) is searched from the registered commands, and the request is requested at the end of the corresponding command. Insert a command.

  If a memory access command can be issued, the memory access command is issued to the memory in order from the top of the access command queue (17-1).

  Next, an actual processing flow will be described using an example. Consider a case in which a CPU 19-1 and a CPU 19-2 execute a process having a high real-time property while executing another process at the same time. The software secures a memory area for processing the target data. For example, assume that a memory area as shown in FIG. 6 is secured. Thereafter, in consideration of real-time processing of the CPU 19-1 and CPU 19-2, this memory area (0x2000_0000-0x6000_0000 in FIG. 6) is stored in the priority address setting register (15). Thereafter, the CPU 19-1 and the CPU 19-2 issue an access request (a) to the memory when executing a process with high priority. At the same time, when there is a memory access request (b) from the CPU 19-3, the access request (b) is outside the priority address setting and has a lower priority than the access request (a). Priority is issued to memory.

  When the processing of the CPU 19-3 is completed and a new memory area as shown in FIG. 7 is secured in order to newly execute processing with high real-time by the CPU 19-3 alone, this memory area (0x6000_0000 in FIG. -0x8000_0000) is stored in the priority address register (15). In this case, by setting the two priority address registers, the priority address setting area becomes 0x2000_0000-0x8000_0000, and the memory access commands from the CPU 19-1 to the CPU 19-3 have the same priority.

(Second embodiment)
FIG. 8 shows the configuration of the priority address setting register (15). In this embodiment, the priority address setting register (15) includes a master ID and a valid bit simultaneously with the priority address. The priority address setting register (15) cannot be updated when the valid bit indicates 1 and the master ID is different from the master ID issuing the priority address update request.

  For example, when a set of priority address setting registers are mounted and the CPU 19-1, CPU 19-2, and CPU 19-3 are mounted as masters, priority addresses can be set from each CPU, but the CPU 19- When 1 is a priority address setting and the priority address setting is valid, only the CPU 19-1 can change the priority address setting, and the CPU 19-2 and CPU 19-3 cannot. Only after the CPU 19-1 disables the priority address setting, the CPU 19-2 and CPU 19-3 can set the priority address.

(Third embodiment)
FIG. 9 shows the configuration of the priority address setting register (15). In this embodiment, the priority address setting register (15) includes a priority address and priority, and the memory access command issue queue performs reordering based on the priority address and its priority.

It is a functional block diagram of a memory controller to which the present invention is applied. It is a functional block diagram of a conventional memory controller. It is a figure which shows the priority address setting register in a memory controller. It is a figure which shows the priority address setting register in a memory controller. It is a figure which shows the flow at the time of registering a memory access request command in a command issue queue. It is a figure which shows an example of a memory map and priority address setting. It is a figure which shows an example of a memory map and priority address setting. FIG. 3 is a diagram showing a priority address setting register in the memory controller according to claim 2. It is a figure which shows the priority address setting register in the memory controller of Claim 3.

Explanation of symbols

1 ASIC
2 Memory 3 Memory bus 4 Memory controller 5 Bus 6 Memory access command issue queue 7-0 to 7-n Processing unit 10 ASIC
11 Memory 12 Memory Bus 13 Memory Controller 14 Memory Access Command Issuing Queue 15 Priority Address Setting Register 16 Reordering Control Block 17-1 to 17-n Access Command Queue 18 Shared Bus 19-1 to 19-n CPU
20-1 to 20-n processing unit

Claims (6)

It has a memory access command issue queue that can be reordered and a means for holding a priority address.
A memory controller comprising means for reordering commands in the command issue queue based on the priority address setting information. The memory controller of claim 1.
The means for holding the priority address holds the master ID that sets the priority address and the valid bit for setting the priority address,
A memory controller comprising means for enabling only a master that matches a held master ID to set a valid bit or a priority address when the valid bit is set. The memory controller of claim 1.
The means for holding priority addresses holds a plurality of addresses and their priorities,
A memory controller comprising means for reordering commands in a memory access command issue queue based on the priority address setting information and address priority setting.   A memory controller comprising the second and third aspects.   5. The memory controller according to claim 1, further comprising a reordering enable function based on the priority address setting information.   A computer system equipped with one of claims 1 to 5.

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