JP2007025869A - Electronic equipment and image formation apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To put electronic equipment into an available state in the shortest time when power is supplied regardless of the type of a memory to be connected or the number of stages of connection. <P>SOLUTION: An SDRAM control part 43 configuring a memory controller 40 is connected through a bus(signal line) to each memory M1 and M2, and a signal is transmitted between the memories M1 and M2 according to the instruction content of a CPU 11. Also, control buses L1 to L3 are provided with buffer circuits 71, 72 and 73, respectively, and signal driving capability is switched by switching control circuits 81, 82 and 83. When power is supplied, the signal driving capability of each of the buffer circuits 71, 72 and 73 is set so as to be selected by the minimum signal driving capability. Thus, it is possible to make the overshoot of a signal smaller than that when the signal driving capability is large, and to instantaneously execute initialization without damaging the memories M1 and M2. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an electronic apparatus and an image forming apparatus using the same.

Conventionally, electronic devices including devices such as a CPU, a main memory, a ROM, and a memory controller are widely known. In this type of electronic device, the main memory can be expanded or a large-capacity memory can be mounted in advance. This is because the storage capacity of the main memory limits the execution speed of the system or the applications that can be used, so that it is necessary to increase the capacity according to the intended use.
On the other hand, when the storage capacity of the main memory increases, the number of memory chips mounted on the substrate increases, and the load capacity of the memory increases. As a result, the amount of current flowing through the signal line increases, so that the rise of the signal stops and a signal transmission delay occurs. Therefore, in order to minimize the signal transmission delay, it is necessary to change the drive capability (hereinafter referred to as signal drive capability) of the access line to the main memory in accordance with the load capacity of the main memory. Has already been disclosed (see Patent Document 1 below).
This includes a driver unit in which a plurality of buffers are connected in parallel and a selector unit for switching the buffer, and the selector unit switches the buffer based on the identification information of the added main memory. .
JP-A-8-305629

In the above configuration, when power is turned on, it is necessary to first perform processing for determining the signal transmission capability, and there is a problem that processing for initializing the memory cannot be started at an early stage.
As a measure to solve such a problem, in order to cope with a memory having a large load capacity, a buffer having the largest signal driving capability is selected as an initial setting, and at least the processing for determining the signal transmission capability is performed at the time of initialization. Can be abolished. However, a buffer having a large signal transmission capability also has a large signal driving capability. For this reason, when a memory with a small load capacity is connected, the overshoot of the transmitted signal increases, and the memory may be electrically damaged.
The present invention has been completed based on the above circumstances, and is intended to make an electronic device usable in the shortest time when the power is turned on, regardless of the type of connected memory and the number of connected stages. Objective.

  As means for achieving the above object, the invention of claim 1 is directed to control means, a plurality of types of memories that can be connected to the control means alternatively or simultaneously, the control means, and the control means. A buffer circuit that drives a signal output from the control unit and outputs the signal to the memory; and a switching unit that switches a signal driving capability of the buffer circuit. In some cases, the switching means selects the signal driving capability of the buffer circuit as the smallest signal driving capability, and the process of initializing the memory is performed with the smallest signal driving capability.

According to the second aspect of the present invention, there is a control means, a plurality of types of memories that can be connected to the control means alternatively or simultaneously, and between the control means and the memory and output from the control means. A buffer circuit that drives the signal to be output and outputs the signal to the memory, and a switching unit that switches a signal driving capability of the buffer circuit. A signal selected as a process for initializing the memory by selecting a driving capacity as the minimum signal driving capacity among the signal driving capacity capable of normally operating the smallest memory among the recommended memories. It is characterized in that it is performed depending on the driving ability.
In addition, the minimum memory said here is that load capacity is the smallest.

According to a third aspect of the present invention, there is provided a control means, a plurality of types of memories that can be connected to the control means alternatively or simultaneously, and between the control means and the memory, and output from the control means. A buffer circuit that drives the signal to be output and outputs the signal to the memory, and a switching unit that switches a signal driving capability of the buffer circuit. The process for initializing the memory is selected by selecting the drive capacity as the maximum signal drive capacity among the signal drive capacity capable of normally operating the smallest memory among the recommended memories. It is characterized in that it is performed by the signal driving capability.
In addition, the minimum memory said here is that load capacity is the smallest.

  A fourth aspect of the invention is characterized in that, in any one of the first to third aspects, the process of initializing the memory is performed prior to the activation of the CPU.

  According to a fifth aspect of the present invention, in the device according to any one of the first to fourth aspects, the acquisition means for acquiring, from the memory, identification information for specifying the type of the memory subject to the initialization. And specifying the type of memory based on the identification information acquired by the acquisition means, and determining whether or not the signal driving capability selected at that time is compatible with the specified type of memory And determining means for switching, when the determining means determines that the non-conforming is determined by the determining means, the signal driving ability is switched to a more suitable signal driving ability. It is characterized in that the memory is reinitialized with a signal driving capability.

  According to a sixth aspect of the present invention, in any one of the first to fifth aspects, the memory includes a built-in memory built in the device in advance and an additional memory that can be added later, and the built-in memory And the control means, and between the additional memory and the control means, dedicated signal lines are provided, respectively, and the buffer circuits are individually provided for these dedicated signal lines. Further, the present invention is characterized in that the signal drive capability can be switched independently for each memory.

  According to a seventh aspect of the present invention, in the method according to the sixth aspect, the process for initializing the memory by the control means is performed simultaneously for all the memories connected through the signal line. After the process of initializing the memory is completed, the acquisition unit accesses the additional memory and stores the identification information in the built-in memory.

  The invention according to an eighth aspect is the one according to the seventh aspect, wherein the determination means determines whether or not the additional memory is compatible with a signal driving capability of the buffer circuit selected at that time. Judgment is made based on the identification information stored in the memory, and the switching means is more adapted to the signal drive capability of the buffer circuit of the signal line connected to the additional memory when the determination means determines that it is incompatible. It is characterized in that it is changed to the signal driving capability.

  A ninth aspect of the present invention is an image forming apparatus having the electronic apparatus according to any one of the first to eighth aspects.

<Invention of Claim 1>
According to the invention of claim 1, the signal drive capability of the buffer circuit is selected to be the smallest signal drive capability. For this reason, even when a memory with a small load capacity is connected, signal overshoot can be reduced as compared with a memory having a large signal driving capability. Therefore, initialization can be performed immediately without damaging the memory.

<Invention of Claim 2>
According to the second aspect of the present invention, the signal drive capability of the buffer circuit is the minimum of the signal drive capability capable of normally operating the smallest memory (memory having the smallest load capacity) in the recommended memory. Since the signal driving capability is selected, the signal overshoot is smaller than that with a large signal driving capability. Therefore, if the recommended type of memory is used (in other words, a memory with a smaller load capacity than the recommended type is connected), the initialization can be performed immediately without damaging the memory. Can be executed.

<Invention of Claim 3>
According to the invention of claim 3, the signal drive capability of the buffer circuit is the signal drive capability capable of normally operating the smallest memory (memory having the smallest load capacity) in the recommended memory. The maximum signal drive capability is selected. Therefore, if the recommended type of memory is the same as in the case of claim 2, the memory is not damaged, and the number of types of memory that can be initialized appropriately and immediately increases.

<Invention of Claim 4>
According to the fourth aspect of the present invention, the process of initializing the memory is performed prior to the activation of the CPU. Therefore, when the CPU is activated, the process can be started immediately using the memory.

<Invention of Claim 5>
According to the fifth aspect of the present invention, after the initial initialization is performed, if the determination means determines that the signal drive capability is not appropriate, reinitialization is performed with a more suitable signal drive capability. It has become. In other words, if the determination means determines that it is suitable, the initialization of the memory is completed by the initial initialization process without switching the signal drive capability, so the initialization is performed compared to the existing one. It can be completed early.

<Invention of Claim 6>
According to the invention of claim 6, since the buffer circuit is provided exclusively for each memory, it becomes possible to individually switch the signal driving capability according to the type of each memory.

<Invention of Claim 7>
According to the seventh aspect of the invention, since the identification information is stored using the built-in memory, it is not necessary to separately provide a dedicated storage means, and the system can be simplified.

<Invention of Claim 8>
According to the eighth aspect of the present invention, when any of the memories is determined to be incompatible by the determining means, only the signal driving capability of the buffer circuit connected to the memory needs to be switched, and reinitialization is minimized. Processing is enough.

<Invention of Claim 9>
According to the ninth aspect of the present invention, the initialization of the main memory can be completed at an early stage after the power is turned on, so that the printing can be started at an early stage accordingly.

<Embodiment 1>
Embodiment 1 of the present invention will be described with reference to FIGS. FIG. 1 is a block diagram showing an electrical configuration of the printer apparatus. FIG. 2 is a diagram showing the configuration of the main board.
A printer apparatus (corresponding to an image forming apparatus of the present invention) 1 includes a CPU 11 that controls each part of the apparatus, a ROM 13 that stores various programs, parameters, and the like, and a RAM 15 that is used for storing image data and a work area of the CPU 11. , An ASIC 17 for inputting a control signal to each part of the apparatus according to a command from the CPU 11, an oscillator 19 for generating a reference clock signal CLK0 for synchronizing each part of the printer apparatus 1, and an external apparatus connected via a network transmission line Interface 21 that exchanges data with the printer apparatus 1, a USB terminal 23 that inputs and outputs data based on the USB (Universal Serial Bus) standard, and an external device via the network interface 21 and the USB terminal 23. Paper is printed according to the input image data It includes an image forming unit 25 for forming (printing), an operation unit 27 by the user consists operable various keys, display unit for displaying various information about the printer apparatus 1 (liquid crystal panel) 29, a.

  The image forming unit 25 is a laser unit, a charger, a photosensitive member, a developing unit, a transfer unit, a fixing unit, an engine board for operating these units in accordance with a control signal from the ASIC 17, etc. Consists of. The image forming unit 25 irradiates the photosensitive member charged by the charger with a laser in accordance with a control signal from the ASIC 17, thereby forming an electrostatic latent image on the photosensitive member, and developing the electrostatic latent image on the developing unit. Then, the developer image formed on the photosensitive member is transferred onto a sheet using a transfer unit, and the image is formed on the sheet by fixing the image on the sheet using a fixing unit.

  The ROM 13 of this embodiment is composed of a plurality of ROM chips (see FIG. 2). On the other hand, the RAM (corresponding to the memory of the present invention) 15 is composed of a memory module M (hereinafter simply referred to as a memory M) in which a plurality of SDRAM chips are mounted on one substrate.

  The CPU 11 is a CPU core that executes various arithmetic processes based on programs stored in the ROM 13, an interface circuit that relays various data and control signals transmitted between the ASIC 17 and the CPU core, and an input from the oscillator 19. A PLL circuit that multiplies the reference clock signal to be generated. The CPU core operates in synchronization with a clock whose frequency is increased by the PLL circuit.

  On the main board 10, the CPU 11, ASIC 17, ROM 13, oscillator 19, network interface 21, and USB terminal 23 are mounted, and a plurality of slots SL 1 to SL 3 are provided for mounting the memory M. At the time of product shipment, the built-in memory M1 is mounted in one of the plurality of slots SL1 to SL3, and the other slots SL2 and SL3 function as expansion slots for adding memory. The ASIC 17 is provided with a memory controller (corresponding to the control means of the present invention) 40.

FIG. 3 is a block diagram showing an electrical configuration of the memory controller.
The memory controller 40 includes a CPU instruction analysis unit 41, an SDRAM control unit 43, and the like, and controls the memory M in accordance with a control signal from the CPU 11.

  More specifically, the CPU instruction analysis unit 41 decodes the control signal from the CPU 11 to determine whether or not it is a control signal for the memory M, and the signal is a control signal for the memory M. If it is determined, the contents (command contents of the CPU 11) are input to the SDRAM control unit 43.

  The SDRAM control unit 43 includes a data control circuit 51, an address control circuit 53, a control signal generation circuit 55, and the like. The SDRAM control unit 43 communicates with the memory M by a data bus 61 for transmitting data signals, an address bus 63 for transmitting address signals ADR, and control buses L0 to L3 for transmitting control signals. The signals are transmitted to and from the memory M through the three buses according to the instruction contents of the CPU 11 input from the CPU instruction analysis unit 41, which are interconnected. The above data bus, address bus, and control bus are collectively referred to as a bus line.

Hereinafter, the control circuits 51, 53, and 55 of the SDRAM control unit 43 will be described.
The data control circuit 51 controls the output of the data signal input from the CPU 11 to the memory M, and controls the output of the data signal input from the memory M to the CPU 11.
The address control circuit 53 performs data reading or writing address designation in the memory M in accordance with a control signal input from the CPU 11.

  The control signal generation circuit 55 generates and outputs a control signal (command signal) for the memory M, and includes a first signal generation unit 57 and a second signal generation unit 59. The first signal generator 57 generates a known row address strobe (RAS #) signal, column address strobe (CAS #) signal, and write enable (WE #) signal as control signals for the memory M.

  In the present embodiment, the memory M includes an additional memory M2 in addition to the built-in memory M1, and a common control bus L0 is provided between the first signal generator 57 and the memories M1 and M2. Connected with.

On the other hand, the second signal generator 59 generates a known chip select (CS #) signal and clock (CLK) signal as control signals for the memories M1 and M2. The second signal generator 59 and each of the memories M1 and M2 are connected by dedicated control buses (corresponding to dedicated signal lines of the present invention) L1 and L2, and the control buses L1 and L2 are connected. Are provided with dedicated buffer circuits 71 to 72, respectively.
In the present embodiment, since it is possible to increase the number of additional memories up to two, a control bus L3 and a buffer circuit 73 are provided in advance corresponding thereto.

  These buffer circuits 71 to 73 all have the same structure, and are constituted by four buffer chips 77a to 77d connected in parallel to each other as shown in FIG. Each of these buffer chips 77a to 77d is for driving (amplifying and shaping a signal waveform) the control signal output from the second signal generating unit 59. In this embodiment, 77a, 77b and 77c are used. , 77d, the signal driving capability increases.

As described above, the plurality of buffer chips 77 having different signal driving capabilities (signal amplification factors and the like are changed) are provided in order to switch the signal driving capability according to the load capacity of the memory M and the control buses L1 to L3. is there.
The load capacity is a so-called memory access amount, and becomes large when a plurality of memory accesses occur simultaneously for one memory M (for example, when a large number of SDRAM chips are mounted on one substrate). .
In addition, the signal driving capability is to determine the amount of current that can flow to the control bus while keeping the signal transmission delay to a minimum (in other words, within an allowable range). You can take a large amount. Therefore, in this case, no delay occurs even when a memory having a large load capacity is connected. On the other hand, when the signal driving capability is low, the amount of current is limited, and if a memory having a large load capacity that exceeds the limit is connected, a delay occurs.

  Next, the setting / switching operation of the buffer chips 77a to 77d will be described in detail. Each buffer circuit 71, 72, 73 includes a dedicated switching control circuit connected to the CPU instruction analysis unit 41 (in the switching means of the present invention). Equivalent) 81 to 83 are provided. These switching control circuits 81 to 83 are connected to the output enable terminals 78 of the buffer chips 77a to 77d of the corresponding buffer circuits 71 to 73, respectively, and the voltage levels of the output enable terminals 78 can be individually switched. It is like that. Therefore, for example, when setting or switching is performed for the buffer chips 77 a to 77 d of the buffer circuit 71, the output enable terminal 78 of any one of the buffer chips 77 a to 77 d among the buffer circuits 71 is switched through the switching control circuit 81. By setting the output enable terminal 78 of the other buffer chips to the L level, only the buffer chip 77 set to the H level is enabled, and only the buffer chip 77 operates.

  The buffer circuits 71 to 73 are provided only on the bus lines L1 to L3 of the second signal generator 59. Originally, it is preferable to provide a dedicated buffer circuit for the bus lines of the first signal generation unit 57, the data control circuit 51, and the address control circuit 53, but the main circuit 10 on which the circuit elements are mounted is preferably provided. There is a limit to the size. Therefore, in this embodiment, the minimum necessary configuration, that is, the buffer circuits 71 to 73 are provided only on the bus lines L1 to L3 of the second signal generation unit 59 that has the greatest influence on the delay of the signal waveform.

  Reference numeral 91 shown in FIG. 3 is a reset IC, and reference numeral 93 is a RESET control unit. The RESET control unit 93 operates based on the signal Se output from the reset IC 91, outputs a reset signal Sra / Src to the CPU 11 and the SDRAM control unit 43 at a predetermined timing, and activates the CPU 11 and the SDRAM control unit 43. It is something to be made. That is, the CPU 11 and the SDRAM control unit 43 are not activated immediately after the power is turned on, but are activated only when the reset signal Sra / Src output from the RESET control unit 93 is received.

  In addition, as described above, in this embodiment, the additional memory M2 is expanded in addition to the built-in memory M1, and the SPD chip 97 is previously stored in the additional memory M2, as shown in FIG. Built in. The SPD chip 97 stores in advance SPD data (corresponding to the identification information of the present invention) as device information such as the number of banks and the chip configuration.

  Next, memory initialization processing by the SDRAM control unit 43 will be described with reference to FIGS. FIG. 6 is a flowchart showing a memory initialization processing procedure, FIG. 7 is a timing chart showing timings at which the ASIC and the CPU are activated, and FIG. 8 is a diagram showing buffer chip initialization and switching.

  As shown in FIG. 6, the processing is started when the printer apparatus 1 is turned on, and the reset Se 91 outputs a signal Se to the RESET control unit 93 (steps 10 and 20). As a result, the RESET control unit 93 is activated at time t1 shown in FIG.

  In step 30 and subsequent step 40, processing for initializing memories M1 and M2 is performed. First, in step 30, stable clock signals are simultaneously transmitted from the second signal generation unit 59 of the SDRAM control unit 43 to the memories M1 and M2 through the control buses L1 and L2, respectively.

  In this case, the buffer chip 77 of each of the buffer circuits 71 and 72 is set in advance so that the buffer chip 77a having the smallest signal driving capability is used in advance. That is, when the power is turned on, only the output enable terminal 78 of the buffer chip 77a is set to the H level by the switching control circuits 81 and 82, and the output enable terminals 78 of the other buffer chips 77b, 77c and 77d are set to the switching control circuit 81, Both are set to L level by 82. Then, when transmission of the clock signal is continued for about 200 μs with such signal driving capability, the process proceeds to step 40 thereafter.

  In step 40, the reset signal Sra is output to the ASIC 17 by the RESET control unit 93. Accordingly, since the entire ASIC 17 including the memory controller 40 is activated at time t2 shown in FIG. 7, various control commands can be transmitted through the control buses L0 to L3. As a result, a refresh command is transmitted eight times from the control signal generation circuit 55 to each of the memories M1 and M2, and both the memories M1 and M2 are refreshed simultaneously.

Even when refreshing is performed, the signal drive capability of the buffer circuits 71 and 72 is maintained at the initial setting. That is, the memory controller 40 controls the switching control circuits 81 and 82 through the CPU instruction analysis unit 41 so that only the output enable terminal 78 of the buffer chip 77a becomes H level.
As described above, only the output enable terminal 78 of the buffer chip 77a is set to the H level by the switching control circuits 81 and 82, and the other output enable terminals 78 of the buffer chips 77b, 77c and 77d are the switching control circuit. By setting both to 81 and 82 to the L level, “the signal driving capability of the buffer circuit is selected as the smallest signal driving capability by the switching means” of the present invention is realized.

  Thus, the stable transmission of the clock signal is continued for about 200 μs in step 30, and then the refresh process is performed eight times, whereby the initialization processing for both memories M1 and M2 is completed. Then, following the completion of initialization, the process proceeds to step 50.

  In step 50, the reset signal Src is output from the RESET control unit 93 to the CPU 11, and the CPU 11 is activated at time t3 shown in FIG. As described above, since the initialization of the memories M1 and M2 has already been completed at this time, the CPU 11 can immediately start the processing using the built-in memory M1 or the additional memory M2 as a working memory. is there.

In step 60, processing for specifying the type of the additional memory M2 by the CPU 11 is performed. That is, the CPU 11 accesses the SPD chip 97 of the expansion memory M2 and reads the SPD data (information such as the number of banks and the chip configuration) recorded on the SPD chip 97, and then reads the read SPD data into the memory controller 40. Through the internal memory M1.
The CPU 11 corresponds to the acquisition means of the present invention, and the function fulfilled by the acquisition means is realized by the processing of step 60.

Thereafter, the process proceeds to step 70, where the CPU 11 performs a process of determining the signal driving capability of the buffer circuit 72. That is, the CPU 11 accesses the built-in memory M1 and reads the stored SPD data, and calculates the total load capacity of the additional memory M2 based on the SPD data. Thereafter, it is determined whether the calculated load capacity of the additional memory M2 falls within the range of the signal driving capability of the buffer circuit 72 connected to the control bus L2.
The CPU 11 corresponds to the determination means of the present invention, and the function fulfilled by the determination means is realized by the processing of step 70. Further, the range of the signal driving capability described above is a range in which initialization abnormality due to signal delay does not occur.

  If it is determined in step 70 that the value is within the range, the process proceeds to step 80, that is, a series of initialization processes are all completed, and thereafter, the memories M1 and M2 are normally operated. As described above, when it is determined in step 70 that the value is within the range, the initialization of the memories M1 and M2 is completed without switching the buffer chip 77 as shown in FIG.

  On the other hand, if it is determined in step 70 that it is out of range, the process proceeds to step 73, and the buffer chip 77 having the most suitable signal driving capability is selected from the remaining three buffer chips 77b, 77c, 77d. The CPU 11 performs the processing to be performed. Here, as a result of comparing the magnitude of the load capacity of the additional memory M2 and the signal driving capability of each of the buffer chips 77b, 77c, 77d, it is assumed that the buffer chip 77c is selected as being more suitable.

  Then, a process of switching the buffer chip 77 is performed following the selection of the buffer chip 77c. That is, in response to a command from the CPU 11, the output enable terminal 78 of the buffer chip 77c of the buffer circuit 72 is switched from the L level to the H level by the switching control circuit 82. On the contrary, the output enable terminal 78 of the buffer chip 77a is The switching control circuit 82 switches from the H level to the L level.

Thus, when the effective buffer chip 77 of the buffer circuit 72 is switched from 77a to 77c as shown in FIG. 8, this time, the process proceeds to step 75, where the additional memory M2 is reinitialized by the signal driving capability after switching. That is, the process of step 30 and step 40 described above is performed again. When the re-initialization of the additional memory M2 is completed, the process proceeds to step 80, that is, all the series of initialization processes are completed, and thereafter, the memories M1 and M2 are normally operated.
The above-described initialization of the memory M is performed every time the power is turned on.

  As described above, according to this embodiment, the signal drive capabilities of the buffer circuits 71 and 72 are both set to the smallest signal drive capability in the initial setting. If the signal drive capability is set high, as shown in FIG. 9A, if a memory having a smaller load capacity than the signal drive capability (mainly an additional memory) is connected, overshoot occurs at the rise of the signal. Therefore, when initialization is performed, a voltage higher than specified may be applied to damage the memory M. However, in this embodiment, since the buffer chip 77a having a small signal driving capability is selected, signal overshoot is suppressed as shown in FIG. 9B.

  Therefore, even if a memory M having a relatively small load capacity is connected, the memory M is not damaged.

  On the other hand, if a memory M having a large load capacity is connected as compared with the signal driving capability of the buffer chip 77a that is initially set, a signal transmission delay may occur, and initialization may not be performed reliably. As for the built-in memory M1, since the chip configuration is determined in advance and the one that causes the signal delay is not connected, the initialization can be surely performed. Therefore, except for some cases described below, the initialization can be completed with the preset signal driving capability without switching the signal driving capability, so that printing can be started earlier by that amount. It becomes.

  Unlike the built-in memory M1, the expansion memory M2 is mounted in various manners depending on the intended use. Therefore, if the initial setting is performed with the signal driving capability described above, it exceeds the range of the selected signal driving capability. Such a load capacity may be mounted. However, in this case, after initial initialization with the initially set signal driving capability, the CPU 11 determines the signal driving capability (processing of S70), and it is determined that the signal driving capability is not appropriate. In this case, the additional memory M2 is reinitialized with a more suitable signal driving capability (processing of S75). Therefore, even in such a case, the initialization can be completed normally, so that the reliability of the system is improved.

  Then, when determining the signal driving capability, it is necessary to temporarily store the SPD data of the expansion memory M2, but this is stored using the built-in memory M1.

  Further, in the present embodiment, buffer circuits 71 to 73 are dedicatedly provided for the respective control buses L1 to L3 so that the signal driving capability can be switched independently. Therefore, when a plurality of expansion memories M having different load capacities are mounted on the main board 10 and only one of the expansion memories M is determined to be incompatible, only the signal drive capability of the buffer circuit connected to the memory M is switched. It is enough to re-initialize the process.

  In addition, in the present embodiment, the memories M1 and M2 are initialized before the CPU 11 is activated. With such a configuration, the processing can be started using the memories M1 and M2 simultaneously with the activation of the CPU 11.

<Embodiment 2>
Next, Embodiment 2 of the present invention will be described.
In the first embodiment, when the power is turned on, the signal drive capability of the buffer circuits 71 to 73 is set to the smallest signal drive capability. However, the present invention is not limited to this setting method, and may be set as follows. Good. In general, there are recommended types of memory M mounted on electronic devices. Therefore, the initial setting at the time of power-on is set to the minimum signal driving capability among the signal driving capabilities capable of normally operating the memory M having the smallest load capacity in the recommended memory M. is there.

For example, when the signal driving capability capable of normally operating the memory M having the smallest load capacity among the recommended memories M is 77b and 77c, the initial setting is set to 77b. In such a setting, except for the case where a memory M having a load capacity smaller than that in the recommended range is connected, the built-in device is not damaged after power is turned on as in the case of the first embodiment. The memory M1 and the additional memory M2 can be initialized immediately.
Note that the normal operation of the memory M means that the initialization is normally completed without causing a signal transmission delay.

<Embodiment 3>
Next, a third embodiment of the present invention will be described.
In the second embodiment, when the power is turned on, the signal driving capability of the buffer circuits 71 to 73 is the signal driving capability that allows the memory M having the smallest load capacity in the recommended memory M to operate normally. Although the minimum signal driving capability is set, the present invention is not limited to this setting method and may be set as follows. That is, the initial setting at power-on is set to the maximum signal driving capability among the signal driving capabilities capable of normally operating the memory M having the smallest load capacity in the recommended memory M. It is.

  With this setting, as in the case of the second embodiment, initialization is performed without damaging the memory M except when a memory M having a smaller load capacity than that in the recommended range is connected. Since the initialization can be performed with a higher signal driving capability than in the case of the second embodiment, the number of types of memories M that can be appropriately and immediately initialized increases.

<Other embodiments>
The present invention is not limited to the embodiments described with reference to the above description and drawings. For example, the following embodiments are also included in the technical scope of the present invention, and further, within the scope not departing from the gist of the invention other than the following. Various modifications can be made.

  (1) In the first to third embodiments described above, the case where the built-in memory M1 is mounted in advance has been described as an example. However, the scope of application of the present invention is limited to an electronic device having the built-in memory M1. is not. In other words, the built-in memory M1 is not mounted at the time of manufacture or sale, but can be applied to a case where the memory M1 is attached and used at the use stage.

  (2) In the first to third embodiments, the data of the SPD chip 97 of the expansion memory M2 is stored in the built-in memory M1, but any storage location can be used if it can be used when the power is turned on. For example, it may be stored in a register or cache provided in the CPU 11.

  (3) In the first to third embodiments, four types of buffer chips are used. However, more buffer chips may be provided.

  (4) In the first to third embodiments, the printer device is exemplified as the electronic device. However, the usage is not limited to this, and a plurality of types of memories are alternatively or simultaneously used for the control circuit. Any device that can be connected is applicable (for example, a personal computer).

1 is a block diagram illustrating an electrical configuration of a printer apparatus applied to a first embodiment. Diagram showing the configuration of the main board Block diagram showing the electrical configuration of the memory controller Circuit diagram showing the configuration of the buffer circuit Explanatory drawing about the reading mode of SPD data The flowchart figure which shows the processing procedure of memory initialization Timing chart showing timing when ASIC and CPU are activated Diagram showing initial setting and switching of buffer chip (A) Diagram showing signal waveform when signal driving capability is too large (B) Diagram showing signal waveform when signal driving capability is appropriate

Explanation of symbols

1. Printer device (image forming device)
11 ... CPU
17 ... ASIC
40 ... Memory controller (control means)
71, 72, 73 ... buffer circuit 77a, 77b, 77c, 77d ... buffer chip 81, 82, 83 ... switching control circuit (switching means)
M1 ... Built-in memory M2 ... Additional memory L1, L2, L3 ... Control bus

Claims (9)

Control means;
A plurality of types of memories that can be connected to the control means alternatively or simultaneously;
A buffer circuit between the control means and the memory for driving a signal output from the control means to output to the memory;
Switching means for switching the signal drive capability of the buffer circuit,
The control means selects the signal driving ability of the buffer circuit to be the smallest signal driving ability by the switching means at the time of start-up, and performs the process of initializing the memory with the smallest signal driving ability. Electronics. Control means;
A plurality of types of memories that can be connected to the control means alternatively or simultaneously;
A buffer circuit between the control means and the memory for driving a signal output from the control means to output to the memory;
Switching means for switching the signal drive capability of the buffer circuit,
The control means has a signal driving ability of the buffer circuit by the switching means at start-up, and a minimum signal driving ability among signal driving ability capable of normally operating a minimum memory among recommended memories. The electronic apparatus is characterized in that the processing for initializing the memory is performed with the selected signal driving capability. Control means;
A plurality of types of memories that can be connected to the control means alternatively or simultaneously;
A buffer circuit between the control means and the memory for driving a signal output from the control means to output to the memory;
Switching means for switching the signal drive capability of the buffer circuit,
The control means is configured such that, at the time of start-up, the switching means causes the signal drive capability of the buffer circuit to be the maximum signal drive among the signal drive capabilities capable of normally operating the smallest memory among the recommended memories. An electronic apparatus characterized in that the processing for initializing the memory is performed according to the selected signal driving capability by selecting the capability. 4. The electronic apparatus according to claim 1, wherein the process of initializing the memory is performed prior to starting of the CPU. Obtaining means for obtaining identification information for identifying the type of memory to be initialized from the memory;
Determination that specifies the type of memory based on the identification information acquired by the acquisition unit, and determines whether or not the signal driving capability selected at that time is compatible with the specified type of memory Means, and
The switching means switches the signal driving capability to a more suitable signal driving capability when it is determined as non-conforming by the determining unit,
5. The electronic device according to claim 1, wherein the control unit reinitializes the memory with the signal driving capability after the switching. 6. The memory consists of a built-in memory built in the device in advance and an additional memory that can be expanded later,
A dedicated signal line is provided between the built-in memory and the control unit, and between the additional memory and the control unit, and the buffer circuit is provided for each of the dedicated signal lines. It is provided individually,
6. The electronic apparatus according to claim 1, wherein the switching of the signal driving capability can be performed independently for each of the memories. The process for initializing the memory by the control means is configured to be performed simultaneously on all memories connected through the signal line,
The electronic device according to claim 6, wherein after the process of initializing the memory is completed, the acquisition unit accesses the additional memory and stores the identification information in the built-in memory. The determination means determines whether the additional memory is compatible with the signal drive capability of the buffer circuit selected at that time based on the identification information stored in the built-in memory,
8. The switching means, when it is judged as non-conforming by the judging means, the signal driving ability of the buffer circuit of the signal line connected to the additional memory is changed to a more suitable signal driving ability. The electronic device as described in. An image forming apparatus comprising the electronic device according to claim 1.

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