JP2007019551A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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JP2007019551A
JP2007019551A JP2006276723A JP2006276723A JP2007019551A JP 2007019551 A JP2007019551 A JP 2007019551A JP 2006276723 A JP2006276723 A JP 2006276723A JP 2006276723 A JP2006276723 A JP 2006276723A JP 2007019551 A JP2007019551 A JP 2007019551A
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semiconductor
semiconductor device
insulating film
base plate
rewiring
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JP4297154B2 (en
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Ichiro Mihara
一郎 三原
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Casio Computer Co Ltd
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Casio Computer Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

Abstract

<P>PROBLEM TO BE SOLVED: To achieve the conductive connections without passing through a bonding process of the semiconductor chips and solder balls in manufacturing of the semiconductor device called BGA for example. <P>SOLUTION: On a bonding layer 21 on a base plate 20 with a size corresponding to a plurality of semiconductor devices, a plurality of semiconductor configuration 22 are bonded which incorporate re-interconnection lines 30 on a silicon substrate (semiconductor chip) 21. Then, sealing films 31 are formed on the semiconductor configuration 22 and their surrounding bonding layers 22. Next, upper-layer re-interconnection lines 34 and insulating films 35, etc. are formed. Then, the base plate 20 is separated and removed from the semiconductor configuration 22, and a backside of the exposed semiconductor substrate is reduced in thickness. Subsequently, a plurality of semiconductor devices with solder ball 37 can be obtained by cutting each of the adjacent semiconductor configuration 22. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

この発明は半導体装置の製造方法に関する。   The present invention relates to a method for manufacturing a semiconductor device.

例えばＢＧＡ(ball grid array)と呼ばれる半導体装置には、ＬＳＩなどからなる半導体チップを該半導体チップのサイズよりもやや大きいサイズの中継基板(インターポーザ)の上面中央部に搭載し、中継基板の下面に半田ボールによる接続端子をマトリクス状に配置したものがある。   For example, in a semiconductor device called a BGA (ball grid array), a semiconductor chip made of LSI or the like is mounted on the center of the upper surface of a relay substrate (interposer) slightly larger than the size of the semiconductor chip, and is mounted on the lower surface of the relay substrate. There is one in which connection terminals by solder balls are arranged in a matrix.

図２６は従来のこのような半導体装置の一例の断面図を示したものである。半導体チップ１は、シリコン基板２の周辺部に銅などからなる複数のバンプ電極３が設けられた構造となっている。   FIG. 26 shows a sectional view of an example of such a conventional semiconductor device. The semiconductor chip 1 has a structure in which a plurality of bump electrodes 3 made of copper or the like are provided on the periphery of a silicon substrate 2.

中継基板４は、サイズが半導体チップ１のシリコン基板２のサイズよりもやや大きいベースフィルム５を備えている。ベースフィルム５の上面には、半導体チップ１のバンプ電極３に接続される再配線６が設けられている。   The relay substrate 4 includes a base film 5 whose size is slightly larger than the size of the silicon substrate 2 of the semiconductor chip 1. A rewiring 6 connected to the bump electrode 3 of the semiconductor chip 1 is provided on the upper surface of the base film 5.

再配線６は、半導体チップ１のバンプ電極３に対応して設けられた第１の接続パッド７と、マトリクス状に設けられた第２の接続パッド８と、第１と第２の接続パッド７、８を接続する引き回し線９とからなっている。第２の接続パッド８の中央部に対応する部分におけるベースフィルム５には円孔１０が設けられている。   The rewiring 6 includes a first connection pad 7 provided corresponding to the bump electrode 3 of the semiconductor chip 1, a second connection pad 8 provided in a matrix, and the first and second connection pads 7. , 8 and a lead-out line 9 connecting them. A circular hole 10 is provided in the base film 5 in a portion corresponding to the central portion of the second connection pad 8.

そして、半導体チップ１は中継基板４の上面中央部に異方性導電接着剤１１を介して搭載されている。異方性導電接着剤１１は、熱硬化性樹脂１２中に多数の導電性粒子１３を含有させたものからなっている。   The semiconductor chip 1 is mounted on the center of the upper surface of the relay substrate 4 via an anisotropic conductive adhesive 11. The anisotropic conductive adhesive 11 is made of a thermosetting resin 12 containing a large number of conductive particles 13.

半導体チップ１を中継基板４上に搭載する場合には、まず、中継基板４の上面中央部にシート状の異方性導電接着剤１１を介して半導体チップ１を位置合わせしてただ単に載置する。   When the semiconductor chip 1 is mounted on the relay substrate 4, first, the semiconductor chip 1 is simply placed on the center of the upper surface of the relay substrate 4 with the sheet-like anisotropic conductive adhesive 11 being positioned. To do.

次に、熱硬化性樹脂１２が硬化する温度にて所定の圧力を加えてボンディングする。すると、バンプ電極３が熱硬化性樹脂１２を押し退けて第１の接続パッド７の上面に導電性粒子１３を介して導電接続され、且つ、半導体チップ１の下面が中継基板４の上面に熱硬化性樹脂１２を介して接着される。   Next, bonding is performed by applying a predetermined pressure at a temperature at which the thermosetting resin 12 is cured. Then, the bump electrode 3 pushes away the thermosetting resin 12 and is conductively connected to the upper surface of the first connection pad 7 via the conductive particles 13, and the lower surface of the semiconductor chip 1 is thermoset to the upper surface of the relay substrate 4. It adheres via the adhesive resin 12.

次に、半導体チップ１を含む中継基板４の上面全体にエポキシ系樹脂からなる封止膜１４を形成する。次に、円孔１０内およびその下方に半田ボール１５を第２の接続パッド８に接続させて形成する。この場合、第２の接続パッド８はマトリクス状に配置されているため、半田ボール１５もマトリクス状に配置される。   Next, a sealing film 14 made of an epoxy resin is formed on the entire top surface of the relay substrate 4 including the semiconductor chip 1. Next, solder balls 15 are formed in the circular hole 10 and below the circular holes 10 by being connected to the second connection pads 8. In this case, since the second connection pads 8 are arranged in a matrix, the solder balls 15 are also arranged in a matrix.

ここで、半田ボール１５のサイズは半導体チップ１のバンプ電極３のサイズより大きく、また、各半田ボール１５相互の接触を避けるため、その配置間隔をバンプ電極３の配置間隔より大きくする必要がある。そこで、半導体チップ１のバンプ電極３の数が増大した場合、各半田ボール１５に必要な配置間隔を得るため、その配置領域を半導体チップ１のサイズより大きくすることが必要となり、そのために、中継基板４のサイズを半導体チップ１のサイズよりもやや大きくしている。したがって、マトリクス状に配置された半田ボール１５のうち、周辺部の半田ボール１５は半導体チップ１の周囲に配置されている。   Here, the size of the solder balls 15 is larger than the size of the bump electrodes 3 of the semiconductor chip 1, and it is necessary to make the arrangement interval larger than the arrangement interval of the bump electrodes 3 in order to avoid contact between the solder balls 15. . Therefore, when the number of bump electrodes 3 of the semiconductor chip 1 is increased, it is necessary to make the arrangement area larger than the size of the semiconductor chip 1 in order to obtain a necessary arrangement interval for each solder ball 15, and for this reason, The size of the substrate 4 is slightly larger than the size of the semiconductor chip 1. Therefore, among the solder balls 15 arranged in a matrix, the peripheral solder balls 15 are arranged around the semiconductor chip 1.

ところで、上記従来の半導体装置では、再配線６が形成された中継基板４を用い、位置合わせした後のボンディングにより、半導体チップ１のバンプ電極３の下面を中継基板４の再配線６の第１の接続パッド７の上面に導電接続する構成としているので、半導体チップ１のバンプ電極３の数が増大し、バンプ電極３のサイズおよび配置間隔が小さくなると、位置合わせが極めて大変であるという問題があった。この場合、半導体チップ１のサイズを大きくすれば、バンプ電極３のサイズおよび配置間隔を大きくすることができることは当然であるが、そのようにすると、ウエハ状態からの半導体チップの取り数が激減し、極めて高価なものとなってしまう。また、半導体チップ１を１つずつ中継基板４上にボンディングして搭載しなければならず、製造工程が煩雑であるという問題があった。このようなことは、半導体チップを複数個備えたマルチチップモジュール型の半導体装置の場合も同様である。   By the way, in the conventional semiconductor device described above, the relay substrate 4 on which the rewiring 6 is formed is used, and the lower surface of the bump electrode 3 of the semiconductor chip 1 is bonded to the first of the rewiring 6 of the relay substrate 4 by bonding after alignment. Since the number of bump electrodes 3 of the semiconductor chip 1 is increased and the size and arrangement interval of the bump electrodes 3 are reduced, the alignment is extremely difficult. there were. In this case, if the size of the semiconductor chip 1 is increased, it is natural that the size and the arrangement interval of the bump electrodes 3 can be increased. However, by doing so, the number of semiconductor chips taken from the wafer state is drastically reduced. It becomes extremely expensive. In addition, the semiconductor chips 1 must be bonded and mounted on the relay substrate 4 one by one, resulting in a problem that the manufacturing process is complicated. The same applies to a multi-chip module type semiconductor device having a plurality of semiconductor chips.

そこで、この発明は、ボンディングによることなく外部接続電極の配置間隔を大きくすることができる半導体装置の製造方法を提供することを目的とする。
また、この発明は、複数の半導体装置を一括して製造することができる半導体装置の製造方法を提供することを目的とする。 SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that can increase the arrangement interval of external connection electrodes without using bonding.
Another object of the present invention is to provide a semiconductor device manufacturing method capable of manufacturing a plurality of semiconductor devices at once.

請求項１に記載の発明は、半導体基板上に、それぞれ、パッド部を有する複数の再配線が形成された複数の半導体構成体を相互に離間してベース板上に配置する工程と、前記複数の半導体構成体上を含む前記ベース板の上面全体に絶縁膜を形成する工程と、前記絶縁膜の上面に、接続パッド部を有し且ついずれかの前記半導体構成体の対応する前記パッド部に接続される上層再配線を、少なくともいずれかの前記上層再配線の接続パッド部が前記半導体構成体間に形成された前記絶縁膜上に配置されるように形成する工程と、前記ベース板を前記半導体構成体から分離して取り除く工程と、前記半導体構成体を取り除いて露出された前記半導体構成体の前記半導体基板の裏面を薄くする工程と、前記各半導体構成体間における前記絶縁膜を切断して少なくともいずれかの前記上層再配線の接続パッド部が前記半導体構成体より外側の領域の前記絶縁膜上に形成された前記半導体構成体を少なくとも１つ有する半導体装置を複数個得る工程とを有することを特徴とするものである。
請求項２に記載の発明は、請求項１に記載の発明において、前記絶縁膜を切断する工程は、前記半導体構成体が複数個含まれるように切断することを特徴とするものである。
請求項３に記載の発明は、請求項１に記載の発明において、前記半導体構成体を相互に離間してベース板上に配置する工程は、前記半導体構成体間に埋込材を配置する工程を含むことを特徴とするものである。
請求項４に記載の発明は、請求項１に記載の発明において前記複数の再配線は、前記半導体基板上に設けられた保護膜上に形成されていることを特徴とするものである。
請求項５に記載の発明は、請求項１に記載の発明において、前記絶縁膜は複数層であり、その層間に、前記各半導体構成体の再配線とそれに対応する前記各組の上層再配線とを接続する複数組の層間再配線を形成する工程を有することを特徴とするものである。
請求項６に記載の発明は、請求項１に記載の発明において、前記上層再配線を含む前記絶縁膜の上面において前記上層再配線のパッド部を除く部分に最上層絶縁膜を形成する工程を有することを特徴とするものである。
請求項７に記載の発明は、請求項６に記載の発明において、前記上層再配線のパッド部上に突起状の接続端子を形成する工程を有することを特徴とするものである。
請求項８に記載の発明は、請求項７に記載の発明において、前記突起状の接続端子は半田ボールであることを特徴とするものである。
請求項９に記載の発明は、請求項１に記載の発明において、 前記半導体構成体を相互に離間してベース板上に配置する工程は、前記半導体構成体間に埋込材を配置する工程を含み、前記各半導体構成体間における前記絶縁膜を切断する工程は、前記埋込材を切断する工程を含むことを特徴とするものである。 According to a first aspect of the present invention, a plurality of semiconductor structures each having a plurality of rewirings each having a pad portion formed on a semiconductor substrate are disposed on a base plate at a distance from each other, and Forming an insulating film on the entire upper surface of the base plate including the semiconductor structure, and having a connection pad portion on the upper surface of the insulating film and corresponding pad portions of any of the semiconductor structures. Forming a connected upper layer rewiring so that at least one of the upper layer rewiring connection pad portions is disposed on the insulating film formed between the semiconductor structures; and Separating and removing the semiconductor structure from the semiconductor structure, removing the semiconductor structure, thinning a back surface of the semiconductor substrate of the semiconductor structure, and cutting the insulating film between the semiconductor structures. And obtaining a plurality of semiconductor devices having at least one semiconductor structure in which at least one of the upper layer rewiring connection pad portions is formed on the insulating film in a region outside the semiconductor structure. It is characterized by having.
According to a second aspect of the present invention, in the first aspect of the present invention, the step of cutting the insulating film is performed so as to include a plurality of the semiconductor components.
According to a third aspect of the present invention, in the first aspect of the present invention, the step of disposing the semiconductor structure on the base plate at a distance from each other includes disposing an embedded material between the semiconductor structures. It is characterized by including.
According to a fourth aspect of the present invention, in the first aspect of the present invention, the plurality of rewirings are formed on a protective film provided on the semiconductor substrate.
According to a fifth aspect of the present invention, in the first aspect of the present invention, the insulating film has a plurality of layers, and between the layers, the rewiring of each semiconductor structure and the upper rewiring of each set corresponding thereto And a step of forming a plurality of sets of inter-layer rewirings for connecting to each other.
According to a sixth aspect of the present invention, in the first aspect of the invention, a step of forming an uppermost layer insulating film on a portion of the upper surface of the insulating film including the upper layer rewiring except for a pad portion of the upper layer rewiring. It is characterized by having.
According to a seventh aspect of the present invention, in the sixth aspect of the present invention, the method includes a step of forming a protruding connection terminal on the pad portion of the upper layer rewiring.
The invention according to claim 8 is the invention according to claim 7, wherein the protruding connection terminals are solder balls.
The invention according to claim 9 is the invention according to claim 1, wherein the step of disposing the semiconductor structures on the base plate apart from each other includes disposing an embedded material between the semiconductor structures. And the step of cutting the insulating film between the semiconductor structures includes a step of cutting the embedded material.

そして、この発明によれば、半導体基板上に再配線を設けてなる複数または複数組の半導体構成体をベース板上に配置し、半導体構成体を含むベース板の上面全体に絶縁膜を形成し、絶縁膜の上面に上層再配線を半導体構成体の再配線に接続させて形成し、絶縁膜を少なくとも切断することにより、半導体構成体を１つまたは１組有し、その周囲に絶縁膜を有するとともに、周囲の絶縁膜上に上層再配線の一部が配置されてなる半導体装置を複数個一括して得ることができ、従来のようなボンディング工程がなく、したがってボンディングによることなく外部接続電極の配置間隔を大きくすることができ、また複数または複数組の半導体構成体に対して絶縁膜および上層再配線の形成を一括して行うことができるので、製造工程を簡略化することができる。また、絶縁膜を切断する前に半導体基板の裏面を薄くするので、薄型化された半導体装置を効率的に製造することができる。   According to the present invention, a plurality or a plurality of sets of semiconductor structures each having a rewiring provided on a semiconductor substrate are arranged on the base plate, and an insulating film is formed on the entire top surface of the base plate including the semiconductor structures. The upper layer rewiring is formed on the upper surface of the insulating film so as to be connected to the rewiring of the semiconductor structure, and at least the insulating film is cut to have one or one set of semiconductor structures, and the insulating film is formed around the semiconductor structure. In addition, a plurality of semiconductor devices in which a part of the upper layer rewiring is arranged on the surrounding insulating film can be obtained in a lump, and there is no conventional bonding process, so that the external connection electrode without using bonding The arrangement interval can be increased, and the insulating film and the upper layer rewiring can be collectively formed on a plurality or a plurality of sets of semiconductor structures, thereby simplifying the manufacturing process. Door can be. In addition, since the back surface of the semiconductor substrate is thinned before the insulating film is cut, a thinned semiconductor device can be efficiently manufactured.

（第１実施形態）
図１はこの発明の第１実施形態としての半導体装置の断面図を示したものである。この半導体装置は、シリコン、ガラス、セラミックス、樹脂、金属などからなる平面正方形状のベース板２０を備えている。ベース板２０の上面には、接着剤、粘着シート、両面接着テープなどからなる接着層２１が設けられている。接着層２１の上面中央部には、ベース板２０のサイズよりもやや小さいサイズの平面正方形状の半導体構成体２２の下面が接着されている。
半導体構成体２２は半導体チップ２３を含んでいる。半導体チップ２３は、接着層２１の上面中央部に接着されたシリコン基板２４の上面周辺部にアルミニウムなどからなる複数の接続パッド２５が設けられ、接続パッド２５の中央部を除くシリコン基板２４の上面に酸化シリコンなどからなる絶縁膜２６および感光性ポリイミドなどからなる保護膜２７が設けられ、接続パッド２５の中央部が絶縁膜２６および保護膜２７に形成された開口部２８を介して露出されたものからなっている。 (First embodiment)
FIG. 1 is a sectional view of a semiconductor device as a first embodiment of the present invention. The semiconductor device includes a planar square base plate 20 made of silicon, glass, ceramics, resin, metal, or the like. An adhesive layer 21 made of an adhesive, an adhesive sheet, a double-sided adhesive tape, or the like is provided on the upper surface of the base plate 20. The lower surface of the planar square semiconductor structure 22 having a size slightly smaller than the size of the base plate 20 is bonded to the center of the upper surface of the adhesive layer 21.
The semiconductor structure 22 includes a semiconductor chip 23. The semiconductor chip 23 is provided with a plurality of connection pads 25 made of aluminum or the like around the upper surface of the silicon substrate 24 bonded to the center of the upper surface of the adhesive layer 21, and the upper surface of the silicon substrate 24 excluding the center of the connection pad 25. An insulating film 26 made of silicon oxide or the like and a protective film 27 made of photosensitive polyimide or the like are provided, and the central portion of the connection pad 25 is exposed through an opening 28 formed in the insulating film 26 and the protective film 27. It consists of things.

ここで、半導体チップ２３は、通常、ウエハ状態の半導体基板をダイシングして個々の半導体チップとなした場合に得られるものである。しかしながら、この発明では、ウエハ状態の半導体基板上に接続パッド２５、絶縁膜２６および保護膜２７が形成された状態では、ダイシングを行わず、以下に説明するように、再配線を有する半導体構成体２２が得られる状態でウエハ状態の半導体基板をダイシングする。   Here, the semiconductor chip 23 is usually obtained when a semiconductor substrate in a wafer state is diced into individual semiconductor chips. However, in the present invention, in the state where the connection pad 25, the insulating film 26, and the protective film 27 are formed on the semiconductor substrate in the wafer state, the dicing is not performed and the semiconductor structure having rewiring as described below. The semiconductor substrate in the wafer state is diced in a state where 22 is obtained.

半導体チップ２３の保護膜２７上には、保護膜２７に形成された開口部２８を介して露出された接続パッド２５の上面から保護膜２７の上面の所定の箇所にかけて下地金属層２９ａが設けられている。下地金属層２９ａの上面には上層金属層２９ｂが設けられ、下地金属層２９ａおよび上層金属層２９ｂにより再配線３０が形成されている。   On the protective film 27 of the semiconductor chip 23, a base metal layer 29 a is provided from the upper surface of the connection pad 25 exposed through the opening 28 formed in the protective film 27 to a predetermined position on the upper surface of the protective film 27. ing. An upper metal layer 29b is provided on the upper surface of the base metal layer 29a, and the rewiring 30 is formed by the base metal layer 29a and the upper metal layer 29b.

このように、半導体構成体２２は、接続パッド２５、絶縁膜２６および保護膜２７を有する導体チップ２３を含み、さらに、下地金属層２９ａおよび上層金属層２９ｂからなる再配線３０を含んで構成されている。図１において、保護膜２７の開口部２８内には下地金属層２９ａのみが形成されているが、これは図示の都合上であって、実際には、上層金属層２９ｂも形成される。   As described above, the semiconductor structure 22 includes the conductor chip 23 having the connection pad 25, the insulating film 26, and the protective film 27, and further includes the rewiring 30 including the base metal layer 29a and the upper metal layer 29b. ing. In FIG. 1, only the base metal layer 29a is formed in the opening 28 of the protective film 27. However, this is for the convenience of illustration, and actually, the upper metal layer 29b is also formed.

半導体構成体２２の再配線３０を含む保護膜２７の上面および半導体構成体２２の周囲における接着層２１の上面にはエポキシ系樹脂からなる封止膜（絶縁膜）３１が設けられている。封止膜３１の再配線３０のパッド部に対応する部分には開口部３２が設けられている。開口部３２を介して露出された再配線３０のパッド部の上面から封止膜３１の上面の所定の箇所にかけて上層下地金属層３３ａが設けられている。上層下地金属層３３ａの上面全体には上層金属層３９ｂが設けられ、上層下地金属層３３ａおよび上層金属層３９ｂにより再配線３４が形成されている。   A sealing film (insulating film) 31 made of an epoxy resin is provided on the upper surface of the protective film 27 including the rewiring 30 of the semiconductor structure 22 and the upper surface of the adhesive layer 21 around the semiconductor structure 22. An opening 32 is provided in a portion of the sealing film 31 corresponding to the pad portion of the rewiring 30. An upper base metal layer 33 a is provided from the upper surface of the pad portion of the rewiring 30 exposed through the opening 32 to a predetermined position on the upper surface of the sealing film 31. An upper metal layer 39b is provided on the entire upper surface of the upper base metal layer 33a, and a rewiring 34 is formed by the upper base metal layer 33a and the upper metal layer 39b.

上層再配線３４を含む封止膜３１の上面全体にはソルダーレジストなどからなる絶縁膜３５が設けられている。絶縁膜３５の上層再配線３４の接続パッド部３４ａに対応する部分には開口部３６が設けられている。開口部３６内およびその上方には半田ボール（突起状の接続端子）３７が上層再配線３４の接続パッド部３４ａに接続されて設けられている。複数の半田ボール３７は、絶縁膜３５上にマトリクス状に配置されている。   An insulating film 35 made of solder resist or the like is provided on the entire upper surface of the sealing film 31 including the upper layer rewiring 34. An opening 36 is provided in a portion corresponding to the connection pad portion 34 a of the upper layer rewiring 34 of the insulating film 35. Solder balls (protruding connection terminals) 37 are provided in and above the opening 36 so as to be connected to the connection pad 34 a of the upper layer rewiring 34. The plurality of solder balls 37 are arranged in a matrix on the insulating film 35.

ところで、ベース板２０のサイズを半導体構成体２２のサイズよりもやや大きくしているのは、半導体チップ２３の接続パッド２５の数の増加に応じて、半田ボール３７の配置領域を半導体構成体２２のサイズよりもやや大きくし、これにより、接続パッド３４ａのサイズおよび配置間隔を接続パッド２５のサイズおよび配置間隔よりも大きくするためである。   By the way, the size of the base plate 20 is made slightly larger than the size of the semiconductor structure 22 because the arrangement area of the solder balls 37 is increased in accordance with the increase in the number of connection pads 25 of the semiconductor chip 23. This is because the size and arrangement interval of the connection pads 34a are made larger than the size and arrangement interval of the connection pads 25.

このため、マトリクス状に配置された上層再配線３４の接続パッド部３４ａは、半導体構成体２２に対応する領域のみでなく、半導体構成体２２の周側面に設けられた絶縁膜３１に対応する領域上にも配置されている。つまり、マトリクス状に配置された半田ボール４７のうち、少なくとも最外周の半田ボール４７は半導体構成体２２よりも外側に位置する周囲に配置されている。   For this reason, the connection pad portion 34 a of the upper layer rewiring 34 arranged in a matrix form not only the region corresponding to the semiconductor structure 22 but also the region corresponding to the insulating film 31 provided on the peripheral side surface of the semiconductor structure 22. It is also arranged on the top. That is, of the solder balls 47 arranged in a matrix, at least the outermost solder balls 47 are arranged around the semiconductor structure 22.

次に、この半導体装置の製造方法の一例について説明するに、まず、半導体構成体２２の製造方法の一例について説明する。まず、図２に示すように、ウエハ状態のシリコン基板（半導体基板）２４上にアルミニウムからなる接続パッド２５、酸化シリコンからなる絶縁膜２６および感光性ポリイミドからなる保護膜２７が設けられ、接続パッド２５の中央部が絶縁膜２６および保護膜２７に形成された開口部２８を介して露出されたものを用意する。   Next, an example of a method for manufacturing the semiconductor device 22 will be described. First, as shown in FIG. 2, a connection pad 25 made of aluminum, an insulating film 26 made of silicon oxide, and a protective film 27 made of photosensitive polyimide are provided on a silicon substrate (semiconductor substrate) 24 in a wafer state. 25 is prepared in which the central portion of 25 is exposed through an opening 28 formed in the insulating film 26 and the protective film 27.

次に、図３に示すように、開口部２８を介して露出された接続パッド２５の上面を含む保護膜２７の上面全体に下地金属層２９ａを形成する。この場合、下地金属層２９ａは、無電解メッキにより形成された銅層のみからなっているが、スパッタにより形成された銅層のみであってもよく、またスパッタにより形成されたチタンなどの薄膜層上にスパッタにより銅層を形成したものであってもよい。これは、後述する上層下地金属層３３ａの場合も同様である。   Next, as shown in FIG. 3, a base metal layer 29 a is formed on the entire upper surface of the protective film 27 including the upper surface of the connection pad 25 exposed through the opening 28. In this case, the base metal layer 29a is composed of only a copper layer formed by electroless plating, but may be only a copper layer formed by sputtering, or a thin film layer such as titanium formed by sputtering. A copper layer may be formed thereon by sputtering. The same applies to the case of the upper base metal layer 33a described later.

次に、下地金属層２９のａ上面にメッキレジスト膜４１をパターン形成する。この場合、再配線３０形成領域に対応する部分におけるメッキレジスト膜４１には開口部４２が形成されている。次に、下地金属層２９ａをメッキ電流路として銅の電解メッキを行うことにより、メッキレジスト膜４１の開口部４２内の下地金属層２９ａの上面に上層金属層２９ｂを形成する。   Next, a plating resist film 41 is formed on the upper surface of the base metal layer 29 by patterning. In this case, an opening 42 is formed in the plating resist film 41 in a portion corresponding to the rewiring 30 formation region. Next, the upper metal layer 29 b is formed on the upper surface of the base metal layer 29 a in the opening 42 of the plating resist film 41 by performing copper electroplating using the base metal layer 29 a as a plating current path.

次に、メッキレジスト膜４１を剥離し、次いで、上層金属層２９ｂをマスクとして下地金属層２９ａの不要な部分をエッチングして除去すると、図４に示すように、上層金属層２９ｂ下にのみ下地金属層２９ａが残存され再配線３０が形成される。次に、図５に示すように、ダンシング工程を経ると、半導体チップ２３上に再配線３０を設けてなる半導体構成体２２が複数個得られる。   Next, the plating resist film 41 is peeled off, and then unnecessary portions of the base metal layer 29a are removed by etching using the upper metal layer 29b as a mask. As shown in FIG. 4, the base metal layer 29b is only under the upper metal layer 29b. The metal layer 29a remains and the rewiring 30 is formed. Next, as shown in FIG. 5, a plurality of semiconductor structures 22 each having a rewiring 30 provided on the semiconductor chip 23 are obtained through a dancing process.

次に、このようにして得られた半導体構成体２２を用いて、図１に示す半導体装置を製造する場合の一例について説明する。まず、図６に示すように、図１に示すベース板２０を複数枚採取することができるベース板２０の上面全体に接着層２１が設けられたものを用意する。そして、接着層２１の上面の所定の複数箇所にそれぞれ半導体構成体２２のシリコン基板２４の下面を接着する。   Next, an example of manufacturing the semiconductor device shown in FIG. 1 using the semiconductor structure 22 obtained in this manner will be described. First, as shown in FIG. 6, one having an adhesive layer 21 provided on the entire top surface of the base plate 20 from which a plurality of the base plates 20 shown in FIG. 1 can be collected is prepared. Then, the lower surface of the silicon substrate 24 of the semiconductor structure 22 is bonded to a plurality of predetermined positions on the upper surface of the adhesive layer 21.

次に、図７に示すように、複数の半導体構成体２２を含む接着層２１の上面全体にエポキシ系樹脂からなる封止膜３１を印刷法やモールド法などによりその厚さが半導体構成体２２の高さよりもやや厚くなるように形成する。したがって、この状態では、半導体構成体２２の上面は封止膜３１によって覆われている。次に、必要に応じて、封止膜３１の上面側を適宜に研磨して、封止膜３１の上面を平滑化する。次に、封止膜３１の再配線３０のパッド部に対応する部分に、フォトリソグラフィあるいはＣＯ２レーザの照射により、開口部３２を形成する。   Next, as shown in FIG. 7, a sealing film 31 made of an epoxy resin is formed on the entire upper surface of the adhesive layer 21 including a plurality of semiconductor structures 22 by a printing method, a molding method, or the like so that the thickness of the semiconductor structure 22 is increased. It is formed so as to be slightly thicker than the height. Therefore, in this state, the upper surface of the semiconductor structure 22 is covered with the sealing film 31. Next, if necessary, the upper surface side of the sealing film 31 is appropriately polished to smooth the upper surface of the sealing film 31. Next, an opening 32 is formed in the portion of the sealing film 31 corresponding to the pad portion of the rewiring 30 by photolithography or CO2 laser irradiation.

次に、図８に示すように、開口部３２を介して露出された再配線３０のパッド部を含む封止膜３１の上面全体に銅の無電解メッキにより上層下地金属層３３ａを形成する。次に、上層下地金属層３３ａの上面にメッキレジスト膜４３をパターン形成する。この場合、上層再配線３４形成領域に対応する部分におけるメッキレジスト膜４３には開口部４４が形成されている。次に、上層下地金属層３３ａをメッキ電流路として銅の電解メッキを行うことにより、メッキレジスト膜４３の開口部４４内の上層下地金属層３３ａの上面に上層金属層３３ｂを形成する。   Next, as shown in FIG. 8, an upper base metal layer 33a is formed on the entire upper surface of the sealing film 31 including the pad portion of the rewiring 30 exposed through the opening 32 by electroless plating of copper. Next, a plating resist film 43 is formed on the upper surface of the upper base metal layer 33a. In this case, an opening 44 is formed in the plating resist film 43 in a portion corresponding to the upper layer rewiring 34 forming region. Next, by performing electrolytic plating of copper using the upper base metal layer 33a as a plating current path, the upper metal layer 33b is formed on the upper surface of the upper base metal layer 33a in the opening 44 of the plating resist film 43.

次に、メッキレジスト膜４３を剥離し、次いで、上層金属層３３ｂをマスクとして上層下地金属層３３ａの不要な部分をエッチングして除去すると、図９に示すように、上層金属層３３ｂ下にのみ上層下地金属層３３ａが残存された上層再配線３４が形成される。   Next, the plating resist film 43 is peeled off, and then unnecessary portions of the upper base metal layer 33a are removed by etching using the upper metal layer 33b as a mask. As shown in FIG. 9, only below the upper metal layer 33b. An upper layer rewiring 34 in which the upper base metal layer 33a remains is formed.

次に、図１０に示すように、上層再配線３４を含む封止膜３１の上面全体にソルダーレジストからなる絶縁膜３５をパターン形成する。この場合、絶縁膜３５の上層再配線３４の接続パッド部３４ａに対応する部分には開口部３６が形成されている。次に、開口部３６内およびその上方に半田ボール３７を上層再配線３４の接続パッド部３４ａに接続させて形成する。   Next, as shown in FIG. 10, an insulating film 35 made of a solder resist is patterned on the entire top surface of the sealing film 31 including the upper layer rewiring 34. In this case, an opening 36 is formed in a portion corresponding to the connection pad portion 34 a of the upper layer rewiring 34 of the insulating film 35. Next, a solder ball 37 is formed in and above the opening 36 by being connected to the connection pad portion 34 a of the upper layer rewiring 34.

次に、図１１に示すように、互いに隣接する半導体構成体２２間において、絶縁膜３５、封止膜３１、接着層２１およびベース板２０を切断すると、図１に示す半導体装置が複数個得られる。   Next, as shown in FIG. 11, when the insulating film 35, the sealing film 31, the adhesive layer 21, and the base plate 20 are cut between the adjacent semiconductor structures 22, a plurality of semiconductor devices shown in FIG. 1 are obtained. It is done.

このようにして得られた半導体装置では、半導体構成体２２の再配線３０に接続される上層下地金属層３３ａおよび上層金属層３３ｂを無電解メッキ（またはスパッタ）および電解メッキにより形成しているので、ボンディングによらないで、半導体構成体２２の再配線３０と上層再配線３４との間を導電接続することができる。   In the semiconductor device thus obtained, the upper base metal layer 33a and the upper metal layer 33b connected to the rewiring 30 of the semiconductor structure 22 are formed by electroless plating (or sputtering) and electrolytic plating. The rewiring 30 and the upper layer rewiring 34 of the semiconductor structure 22 can be conductively connected without using bonding.

このように、上層再配線３４が半導体構成体２２の再配線３０のパッド部にメッキにより直接接合されるものであるため、上層絶縁膜３１の開口部３２は、１０μｍ×１０μｍの方形または同面積の円形の面積を有していれば強度的に十分である。   Thus, since the upper layer rewiring 34 is directly bonded to the pad portion of the rewiring 30 of the semiconductor structure 22 by plating, the opening 32 of the upper layer insulating film 31 has a square shape or the same area of 10 μm × 10 μm. If it has a circular area, it is sufficient in strength.

これに対し、図２６に示す従来の半導体チップでは、バンプ電極３の直径は１００〜１５０μｍ程度（ピッチは、通常、この２倍）であるので、従来の、バンプ電極と再配線とをボンディングにより接合する方法と比較すると、接続パッド部３４ａのサイズおよび配置間隔が遙かにすることができ、且つ、プロセスも効率的である。   On the other hand, in the conventional semiconductor chip shown in FIG. 26, since the bump electrode 3 has a diameter of about 100 to 150 μm (the pitch is usually twice this), the conventional bump electrode and rewiring are bonded together. Compared with the method of joining, the size and arrangement interval of the connection pad portion 34a can be greatly reduced, and the process is also efficient.

このように、接続パッド部３４ａのサイズおよび配置間隔を小さいものとすることができるので、上層の再配線を有する本発明の半導体装置のサイズを小さいものとすることができる。   Thus, since the size and arrangement interval of the connection pad portion 34a can be made small, the size of the semiconductor device of the present invention having the upper layer rewiring can be made small.

また、上記製造方法では、ベース板２０上の接着層２１上の所定の複数箇所にそれぞれ半導体構成体２２を接着して配置し、複数の半導体構成体２２に対して封止膜３１、上層下地金属層３３、上層再配線３４、絶縁膜３５および半田ボール３７の形成を一括して行い、その後に分断して複数個の半導体装置を得ているので、製造工程を簡略化することができる。   Further, in the above manufacturing method, the semiconductor structure 22 is bonded and arranged at a plurality of predetermined positions on the adhesive layer 21 on the base plate 20, and the sealing film 31 and the upper layer base are attached to the plurality of semiconductor structures 22. Since the metal layer 33, the upper layer rewiring 34, the insulating film 35, and the solder ball 37 are formed in a lump and then divided to obtain a plurality of semiconductor devices, the manufacturing process can be simplified.

また、ベース板２０と共に複数の半導体構成体２２を搬送することができるので、これによっても製造工程を簡略化することができる。さらに、ベース板２０の外形寸法を一定にすると、製造すべき半導体装置の外形寸法に関係なく、搬送系を共有化することができる。   Further, since the plurality of semiconductor structures 22 can be transported together with the base plate 20, the manufacturing process can be simplified by this. Furthermore, if the outer dimensions of the base plate 20 are made constant, the transport system can be shared regardless of the outer dimensions of the semiconductor device to be manufactured.

さらに、図１に示す半導体装置では、シリコン基板２４上に感光性ポリイミドなどからなる保護膜２７、エポキシ系樹脂などからなる封止膜３１および感光性ポリイミドなどからなる絶縁膜３５を積層しているので、この３層の樹脂層により、この半導体装置を半田ボール３７を介して回路基板（図示せず）上に搭載した後において、シリコン基板２４と回路基板との熱膨張係数差に起因する応力をある程度緩和することができる。   Further, in the semiconductor device shown in FIG. 1, a protective film 27 made of photosensitive polyimide, a sealing film 31 made of epoxy resin, and an insulating film 35 made of photosensitive polyimide are laminated on a silicon substrate 24. Therefore, the stress caused by the difference in thermal expansion coefficient between the silicon substrate 24 and the circuit board after the semiconductor device is mounted on the circuit board (not shown) via the solder balls 37 by the three resin layers. Can be relaxed to some extent.

次に、図１に示す半導体装置の製造方法の他の例について説明する。まず、図１２に示すように、紫外線透過性の透明樹脂板やガラス板などからなる別のベース板５１の上面全体に紫外線硬化型の粘着シートなどからなる接着層５２を接着し、接着層５２の上面に上述のベース板２０および接着層２１を接着したものを用意する。   Next, another example of the method for manufacturing the semiconductor device shown in FIG. 1 will be described. First, as shown in FIG. 12, an adhesive layer 52 made of an ultraviolet curable pressure sensitive adhesive sheet or the like is adhered to the entire upper surface of another base plate 51 made of an ultraviolet transparent transparent resin plate or glass plate. Prepared by adhering the base plate 20 and the adhesive layer 21 to the upper surface.

そして、図６〜図１０にそれぞれ示す製造工程を経た後に、図１３に示すように、絶縁膜３５、封止膜３１、接着層２１、ベース板２０および接着層５２を切断し、別のベース板５１を切断しない。次に、別のベース板５１の下面側から紫外線を照射し、接着層５２を硬化させる。すると、分断されたベース板２０の下面に対する接着層５２による接着性が低下する。そこで、接着層５２上に存在する個片化されたものを１つずつ剥がしてピックアップすると、図１に示す半導体装置が複数個得られる。   Then, after the manufacturing steps shown in FIGS. 6 to 10, as shown in FIG. 13, the insulating film 35, the sealing film 31, the adhesive layer 21, the base plate 20, and the adhesive layer 52 are cut to obtain another base. The plate 51 is not cut. Next, the adhesive layer 52 is cured by irradiating ultraviolet rays from the lower surface side of another base plate 51. Then, the adhesiveness by the adhesive layer 52 with respect to the lower surface of the divided base plate 20 is lowered. Therefore, when the separated pieces existing on the adhesive layer 52 are peeled off one by one and picked up, a plurality of semiconductor devices shown in FIG. 1 are obtained.

この製造方法では、図１３に示す状態において、接着層５２上に存在する個片化された半導体装置がバラバラとならないので、専用の半導体装置載置用トレーを用いることなく、そのまま、図示しない回路基板上への実装時に１つずつ剥がしてピックアップすることができる。また、別のベース板５１の上面に残存する接着性が低下した接着層５２を剥離すると、別のベース板５１を再利用することができる。さらに、別のベース板５１の外形寸法を一定にすると、製造すべき半導体装置の外形寸法に関係なく、搬送系を共有化することができる。   In this manufacturing method, the individual semiconductor devices present on the adhesive layer 52 do not fall apart in the state shown in FIG. 13, so a circuit (not shown) is used as it is without using a dedicated semiconductor device mounting tray. When mounting on a substrate, it can be removed and picked up one by one. Further, when the adhesive layer 52 with reduced adhesion remaining on the upper surface of another base plate 51 is peeled off, the other base plate 51 can be reused. Furthermore, if the external dimensions of the other base plate 51 are made constant, the transport system can be shared regardless of the external dimensions of the semiconductor device to be manufactured.

なお、別のベース板５５として、膨張させることにより半導体装置を取り外す、通常のダイシングテープなどを用いることも可能であり、その場合には、接着層は紫外線硬化型でなくてもよい。また、別のベース板５５を研磨やエッチングにより除去するようにしてもよい。   In addition, it is also possible to use a normal dicing tape or the like in which the semiconductor device is removed by being expanded as another base plate 55. In this case, the adhesive layer may not be an ultraviolet curable type. Further, another base plate 55 may be removed by polishing or etching.

次に、図１に示す半導体装置の製造方法のさらに他の例について説明する。この製造方法では、図７に示す製造工程後に、図１４に示すように、開口部３２を介して露出された再配線３０の上面を含む封止膜３１の上面全体に銅の無電解メッキにより上層下地金属層３３ａを形成する。次に、上層下地金属層３３ａをメッキ電流路として銅の電解メッキを行うことにより、上層下地金属層３３の上面全体に上層金属層３３ｃを形成する。次に、上層金属層層３３ｃの上面の上層再配線形成領域に対応する部分にレジスト膜５３をパターン形成する。   Next, still another example of the method for manufacturing the semiconductor device shown in FIG. 1 will be described. In this manufacturing method, after the manufacturing process shown in FIG. 7, as shown in FIG. 14, the entire upper surface of the sealing film 31 including the upper surface of the rewiring 30 exposed through the opening 32 is electrolessly plated with copper. An upper base metal layer 33a is formed. Next, the upper metal layer 33 c is formed on the entire upper surface of the upper base metal layer 33 by performing electrolytic plating of copper using the upper base metal layer 33 a as a plating current path. Next, a resist film 53 is formed in a pattern corresponding to the upper layer rewiring formation region on the upper surface of the upper metal layer 33c.

次に、レジスト膜５３をマスクとして上層金属層３３ｃおよび上層下地金属層３３ａの不要な部分をエッチングして除去すると、図１５に示すように、レジスト膜５３下にのみ上層金属層３３ｃおよび上層下地金属層３３ａが残存され、上層再配線３４が形成される。この後、レジスト膜５３を剥離する。なお、これと同様の形成方法により、半導体構成体２２の上層金属層２９ｂおよび下地金属層２９ａを形成するようにしてもよい。   Next, when unnecessary portions of the upper metal layer 33c and the upper base metal layer 33a are removed by etching using the resist film 53 as a mask, the upper metal layer 33c and the upper base layer only under the resist film 53 as shown in FIG. The metal layer 33a remains, and the upper layer rewiring 34 is formed. Thereafter, the resist film 53 is peeled off. Note that the upper metal layer 29b and the base metal layer 29a of the semiconductor structure 22 may be formed by the same formation method.

（第２実施形態）
図６に示す製造工程において、接着層２１を半導体構成体２２のシリコン基板２４の下面に設け、この接着層２１をベース板２０の上面の各所定の箇所に接着した場合には、図１６に示すこの発明の第２実施形態としての半導体装置が得られる。 (Second Embodiment)
In the manufacturing process shown in FIG. 6, when the adhesive layer 21 is provided on the lower surface of the silicon substrate 24 of the semiconductor structure 22 and this adhesive layer 21 is adhered to each predetermined location on the upper surface of the base plate 20, FIG. The semiconductor device as the second embodiment of the present invention shown is obtained.

このようにして得られた半導体装置では、シリコン基板２４の下面が接着層２１を介してベース板２０の上面に接着されているほかに、シリコン基板２４の側面などが封止膜３６を介してベース板２０の上面に接続されているので、半導体構成体２２のベース板２０に対する接合強度をある程度強くすることができる。   In the semiconductor device thus obtained, the lower surface of the silicon substrate 24 is bonded to the upper surface of the base plate 20 via the adhesive layer 21, and the side surface of the silicon substrate 24 is interposed via the sealing film 36. Since it is connected to the upper surface of the base plate 20, the bonding strength of the semiconductor structure 22 to the base plate 20 can be increased to some extent.

（第３、第４実施形態）
図１７はこの発明の第３実施形態としての半導体装置の断面図を示したものである。この半導体装置において、図１に示す半導体装置と異なる点は、ベース板２０および接着層２１を備えていないことである。 (Third and fourth embodiments)
FIG. 17 shows a sectional view of a semiconductor device as a third embodiment of the present invention. This semiconductor device is different from the semiconductor device shown in FIG. 1 in that the base plate 20 and the adhesive layer 21 are not provided.

この第３実施形態の半導体装置を製造する場合には、例えば図１０に示すように、半田ボール３７を形成した後に、ベース板２０を接着層２１から剥がしたりまたはベース板２０および接着層２１を研磨やエッチングなどにより除去するなどして取り除いた後に、互いに隣接する半導体構成体２２間において、絶縁膜３５および封止膜３１を切断すると、図１７に示す半導体装置が複数個得られる。このようにして得られた半導体装置では、ベース板２０および接着層２１を備えていないので、その分だけ、薄型化することができる。   When manufacturing the semiconductor device of the third embodiment, for example, as shown in FIG. 10, after forming the solder balls 37, the base plate 20 is peeled off from the adhesive layer 21, or the base plate 20 and the adhesive layer 21 are removed. After removal by polishing or etching, the insulating film 35 and the sealing film 31 are cut between the adjacent semiconductor structures 22 to obtain a plurality of semiconductor devices shown in FIG. Since the semiconductor device thus obtained does not include the base plate 20 and the adhesive layer 21, the thickness can be reduced accordingly.

また、ベース板２０および接着層２１を取り除いた後に、シリコン基板２４および封止膜３１の下面側を適宜に研磨し、次いで互いに隣接する半導体構成体２２間において、絶縁膜３５および封止膜３１を切断すると、図１８に示すこの発明の第４実施形態としての半導体装置が複数個得られる。このようにして得られた半導体装置では、さらに薄型化することができる。   Further, after removing the base plate 20 and the adhesive layer 21, the lower surface side of the silicon substrate 24 and the sealing film 31 is appropriately polished, and then the insulating film 35 and the sealing film 31 between the adjacent semiconductor components 22. Is cut, a plurality of semiconductor devices as the fourth embodiment of the present invention shown in FIG. 18 are obtained. The semiconductor device thus obtained can be further reduced in thickness.

なお、半田ボール３７を形成する前に、ベース板２０および接着層２１を研磨やエッチングなどにより除去し（必要に応じてさらにシリコン基板２４および封止膜３１の下面側を適宜に研磨し）、次いで半田ボール３７を形成し、次いで互いに隣接する半導体構成体２２間において、絶縁膜３５および封止膜３１を切断するようにしてもよい。   Before forming the solder balls 37, the base plate 20 and the adhesive layer 21 are removed by polishing, etching, or the like (further, the lower surface side of the silicon substrate 24 and the sealing film 31 is appropriately polished). Next, the solder balls 37 may be formed, and then the insulating film 35 and the sealing film 31 may be cut between the adjacent semiconductor structures 22.

（第５実施形態）
図１９はこの発明の第５実施形態としての半導体装置の断面図を示したものである。この半導体装置において、図１に示す半導体装置と異なる点は、接着層２１の下面に放熱用の金属層６１が接着されていることである。金属層６１は、厚さ数十μｍの銅箔などからなっている。 (Fifth embodiment)
FIG. 19 is a sectional view of a semiconductor device as a fifth embodiment of the present invention. This semiconductor device differs from the semiconductor device shown in FIG. 1 in that a metal layer 61 for heat dissipation is bonded to the lower surface of the adhesive layer 21. The metal layer 61 is made of a copper foil having a thickness of several tens of μm.

この第５実施形態の半導体装置を製造する場合には、例えば図１０に示すように、半田ボール３７を形成した後に、ベース板２０を研磨やエッチングなどにより除去し、次いで接着層２１の下面全体に金属層６１を接着し、次いで互いに隣接する半導体構成体２２間において、絶縁膜３５、封止膜３１、接着層２１および金属層６１を切断すると、図１８に示す半導体装置が複数個得られる。   In the case of manufacturing the semiconductor device of the fifth embodiment, for example, as shown in FIG. 10, after forming the solder balls 37, the base plate 20 is removed by polishing or etching, and then the entire lower surface of the adhesive layer 21 is formed. 18 are bonded together, and then the insulating film 35, the sealing film 31, the adhesive layer 21 and the metal layer 61 are cut between the adjacent semiconductor structures 22 to obtain a plurality of semiconductor devices shown in FIG. .

なお、接着層２１も研磨やエッチングなどにより除去し（必要に応じてさらにシリコン基板２４および封止膜３１の下面側を適宜に研磨し）、シリコン基板２４および封止膜３１の下面に新たな接着層を介して金属層６１を接着するようにしてもよい。   The adhesive layer 21 is also removed by polishing, etching, or the like (further, the lower surface side of the silicon substrate 24 and the sealing film 31 is appropriately polished as necessary), and a new surface is added to the lower surface of the silicon substrate 24 and the sealing film 31. The metal layer 61 may be bonded through an adhesive layer.

（第６実施形態）
図１１に示す場合には、互いに隣接する半導体構成体２２間において切断したが、これに限らず、２個またはそれ以上の半導体構成体２２を１組として切断し、例えば、図２０に示すこの発明の第６実施形態のように、３個の半導体構成体２２を１組として切断し、マルチチップモジュール型の半導体装置を得るようにしてもよい。この場合、３個で１組の半導体構成体２２は同種、異種のいずれであってもよい。 (Sixth embodiment)
In the case shown in FIG. 11, the semiconductor structures 22 adjacent to each other are cut. However, the present invention is not limited to this, and two or more semiconductor structures 22 are cut as one set. As in the sixth embodiment of the invention, the three semiconductor structures 22 may be cut as a set to obtain a multichip module type semiconductor device. In this case, the set of three semiconductor structures 22 may be of the same type or different types.

（第７実施形態）
図２１はこの発明の第７実施形態としての半導体装置の断面図を示したものである。この半導体装置において、図１に示す半導体装置と異なる点は、半導体構成体２２は、再配線３０を含む保護膜２７の上面に感光性ポリイミドなどからなる上層保護膜６２が設けられ、上層保護膜６２の再配線３０のパッド部に対応する部分に開口部６３が設けられたものからなっていることである。 (Seventh embodiment)
FIG. 21 shows a sectional view of a semiconductor device as a seventh embodiment of the present invention. In this semiconductor device, the semiconductor device 22 is different from the semiconductor device shown in FIG. 1 in that the upper protective film 62 made of photosensitive polyimide or the like is provided on the upper surface of the protective film 27 including the rewiring 30. This is that an opening 63 is provided in a portion corresponding to the pad portion of the rewiring 30 of 62.

この第７実施形態の半導体装置を製造する場合には、図４に示す製造工程後に、図２２に示すように、再配線３０を含む保護膜２７の上面に感光性ポリイミドなどからなる上層保護膜６２を形成し、上層保護膜６２の再配線３０のパッド部に対応する部分に開口部６３を形成し、以下、図５〜図１１に示す場合と同様の製造工程を経ると、図２１に示す半導体装置が複数個得られる。   When manufacturing the semiconductor device of the seventh embodiment, after the manufacturing process shown in FIG. 4, as shown in FIG. 22, the upper protective film made of photosensitive polyimide or the like is formed on the upper surface of the protective film 27 including the rewiring 30. 62, and an opening 63 is formed in a portion corresponding to the pad portion of the rewiring 30 of the upper protective film 62. Thereafter, the same manufacturing steps as shown in FIGS. A plurality of the semiconductor devices shown are obtained.

このようにして得られた半導体装置では、シリコン基板２４上に感光性ポリイミドなどからなる保護膜２７、感光性ポリイミドなどからなる上層保護膜６２、エポキシ系樹脂などからなる封止膜３１および感光性ポリイミドなどからなる絶縁膜３５を積層しているので、この４層の樹脂層により、この半導体装置を半田ボール３７を介して回路基板（図示せず）上に搭載した後において、シリコン基板２４と回路基板との熱膨張係数差に起因する応力をより一層緩和することができる。なお、封止膜３１の上面が上層保護膜６２の上面と面一となるようにしてもよい。   In the semiconductor device thus obtained, the protective film 27 made of photosensitive polyimide or the like, the upper protective film 62 made of photosensitive polyimide or the like, the sealing film 31 made of epoxy resin, or the like on the silicon substrate 24. Since the insulating film 35 made of polyimide or the like is laminated, after the semiconductor device is mounted on the circuit substrate (not shown) via the solder balls 37 by the four resin layers, the silicon substrate 24 and The stress caused by the difference in thermal expansion coefficient with the circuit board can be further relaxed. Note that the upper surface of the sealing film 31 may be flush with the upper surface of the upper protective film 62.

（第８実施形態）
図２３はこの発明の第８実施形態としての半導体装置の断面図を示したものである。この半導体装置において、図１に示す半導体装置と異なる点は、半導体構成体２２の周囲における接着層２１の上面に方形枠状の埋込材７１が設けられていることである。 (Eighth embodiment)
FIG. 23 is a sectional view of a semiconductor device according to the eighth embodiment of the present invention. This semiconductor device is different from the semiconductor device shown in FIG. 1 in that a rectangular frame-shaped embedded material 71 is provided on the upper surface of the adhesive layer 21 around the semiconductor structure 22.

この場合、埋込材７１の厚さは、シリコン基板２４の厚さと同じであってもよく、さらに絶縁膜２５の厚さを加えた厚さと同じであってもよく、さらに保護膜２６の厚さを加えた厚さと同じであってもよく、さらに再配線３０の厚さを加えた厚さと同じであってもよい。したがって、埋込材７１の上面は封止膜３１によって覆われている。また、半導体構成体２２と埋込材７１との間には封止膜３１が充填されている。   In this case, the thickness of the embedding material 71 may be the same as the thickness of the silicon substrate 24, may be the same as the thickness of the insulating film 25, or may be the thickness of the protective film 26. The thickness may be the same as the added thickness, or may be the same as the added thickness of the rewiring 30. Therefore, the upper surface of the embedding material 71 is covered with the sealing film 31. Further, a sealing film 31 is filled between the semiconductor structure 22 and the filling material 71.

この第８実施形態の半導体装置を製造する場合には、図６に示す製造工程おいて、図２４に示すように、接着層２１の上面の所定の複数箇所にそれぞれ半導体構成体２２のシリコン基板２４の下面を接着するとともに、互いに隣接する半導体構成体２２間における接着層２１の上面に格子状の埋込材７１の下面を接着する。   In the case of manufacturing the semiconductor device of the eighth embodiment, in the manufacturing process shown in FIG. 6, as shown in FIG. 24, the silicon substrate of the semiconductor structure 22 is respectively formed at predetermined positions on the upper surface of the adhesive layer 21. In addition to bonding the lower surface of 24, the lower surface of the grid-like embedding material 71 is bonded to the upper surface of the adhesive layer 21 between the adjacent semiconductor structures 22.

埋込材７１の材料は、ベース板２０と同じであってもよく、また別であってもよい。また、ベース板２０および埋込材７１の材料が熱可塑性樹脂である場合、接着層２１を用いずに、両者を熱圧着し、次いで半導体構成体２２のシリコン基板２４の下面に設けられた接着層２１（図参照）をベース板２０の上面に接着するようにしてもよい。また、シート状の埋込材７１を接着層２１の上面全体に接着し（またはベース板２０上に熱圧着し）、座ぐり加工により、格子状の埋込材７１を形成するようにしてもよい。   The material of the embedding material 71 may be the same as that of the base plate 20 or may be different. Further, when the material of the base plate 20 and the embedding material 71 is a thermoplastic resin, both are bonded by thermocompression without using the adhesive layer 21, and then the adhesive provided on the lower surface of the silicon substrate 24 of the semiconductor structure 22. The layer 21 (see the figure) may be adhered to the upper surface of the base plate 20. Alternatively, the sheet-like embedding material 71 is bonded to the entire upper surface of the adhesive layer 21 (or thermocompression bonded onto the base plate 20), and the lattice-like embedding material 71 is formed by spot facing. Good.

次に、図２５に示すように、複数の半導体構成体２２および格子状の埋込材７１を含む接着層２１の上面全体にエポキシ系樹脂などからなる封止膜３１を印刷法やモールド法などにより、その厚さが半導体構成体２２の高さよりもやや厚くなるように形成する。次に、必要に応じて、封止膜３１の上面側を適宜に研磨して、封止膜３１の上面を平滑化する。次に、封止膜３１の再配線３０のパッド部に対応する部分に、フォトリソグラフィあるいはＣＯ２レーザの照射により、開口部３２を形成する。以下、図８〜図１１に示す場合と同様の製造工程を経ると、図２３に示す半導体装置が複数個得られる。   Next, as shown in FIG. 25, a sealing film 31 made of an epoxy-based resin or the like is applied to the entire upper surface of the adhesive layer 21 including the plurality of semiconductor structures 22 and the lattice-shaped embedding material 71. Thus, the thickness is formed to be slightly larger than the height of the semiconductor structure 22. Next, if necessary, the upper surface side of the sealing film 31 is appropriately polished to smooth the upper surface of the sealing film 31. Next, an opening 32 is formed in the portion of the sealing film 31 corresponding to the pad portion of the rewiring 30 by photolithography or CO2 laser irradiation. Thereafter, through the same manufacturing steps as shown in FIGS. 8 to 11, a plurality of semiconductor devices shown in FIG. 23 are obtained.

このようにして得られた半導体装置では、図２５に示すように、互いに隣接する半導体構成体２２間における封止膜３１の量を埋込材７１の体積の分だけ少なくすることができる。この結果、エポキシ系樹脂などからなる封止膜３１の硬化時の収縮による応力を小さくすることができる。   In the semiconductor device thus obtained, as shown in FIG. 25, the amount of the sealing film 31 between the semiconductor structures 22 adjacent to each other can be reduced by the volume of the embedding material 71. As a result, it is possible to reduce stress due to shrinkage when the sealing film 31 made of epoxy resin or the like is cured.

（その他の実施形態）
ところで、上記各実施形態では、封止膜３１上に設けた絶縁膜３５上に上層再配線３４を設けた場合について説明したが、これに限らず、封止膜３１上に設ける絶縁膜を複数層とし、その層間に、半導体構成体２２の再配線３０と上層再配線３４とを接続する層間再配線を設けるようにしてもよい。 (Other embodiments)
In the above embodiments, the case where the upper layer rewiring 34 is provided on the insulating film 35 provided on the sealing film 31 has been described. However, the present invention is not limited thereto, and a plurality of insulating films provided on the sealing film 31 are provided. Layers may be provided, and interlayer rewiring for connecting the rewiring 30 of the semiconductor structure 22 and the upper layer rewiring 34 may be provided between the layers.

この発明の第１実施形態としての半導体装置の断面図。1 is a cross-sectional view of a semiconductor device as a first embodiment of the present invention. 図１に示す半導体装置の製造方法の一例において、当初用意したものの断面図。Sectional drawing of what was prepared initially in an example of the manufacturing method of the semiconductor device shown in FIG. 図２に続く製造工程の断面図。Sectional drawing of the manufacturing process following FIG. 図３に続く製造工程の断面図。Sectional drawing of the manufacturing process following FIG. 図４に続く製造工程の断面図。Sectional drawing of the manufacturing process following FIG. 図５に続く製造工程の断面図。Sectional drawing of the manufacturing process following FIG. 図６に続く製造工程の断面図。Sectional drawing of the manufacturing process following FIG. 図７に続く製造工程の断面図。Sectional drawing of the manufacturing process following FIG. 図８に続く製造工程の断面図。Sectional drawing of the manufacturing process following FIG. 図９に続く製造工程の断面図。Sectional drawing of the manufacturing process following FIG. 図１０に続く製造工程の断面図。Sectional drawing of the manufacturing process following FIG. 図１に示す半導体装置の製造方法の他の例において、当初用意したものの断面図。Sectional drawing of what was initially prepared in the other example of the manufacturing method of the semiconductor device shown in FIG. 同他の例において、所定の製造工程の断面図。Sectional drawing of a predetermined manufacturing process in the other example. 図１に示す半導体装置の製造方法のさらに他の例において、所定の製造工程の断面図。Sectional drawing of a predetermined manufacturing process in the further another example of the manufacturing method of the semiconductor device shown in FIG. 図１４に続く製造工程の断面図。FIG. 15 is a cross-sectional view of the manufacturing process following FIG. 14. この発明の第２実施形態としての半導体装置の断面図。Sectional drawing of the semiconductor device as 2nd Embodiment of this invention. この発明の第３実施形態としての半導体装置の断面図。Sectional drawing of the semiconductor device as 3rd Embodiment of this invention. この発明の第４実施形態としての半導体装置の断面図。Sectional drawing of the semiconductor device as 4th Embodiment of this invention. この発明の第５実施形態としての半導体装置の断面図。Sectional drawing of the semiconductor device as 5th Embodiment of this invention. この発明の第６実施形態としての半導体装置の断面図。Sectional drawing of the semiconductor device as 6th Embodiment of this invention. この発明の第７実施形態としての半導体装置の断面図。Sectional drawing of the semiconductor device as 7th Embodiment of this invention. 図２１に示す半導体装置の製造方法の一例において、所定の製造工程の断面図。FIG. 22 is a cross-sectional view of a predetermined manufacturing process in the example of the method for manufacturing the semiconductor device shown in FIG. 21. この発明の第８実施形態としての半導体装置の断面図。Sectional drawing of the semiconductor device as 8th Embodiment of this invention. 図２３に示す半導体装置の製造方法の一例において、所定の製造工程の断面図。FIG. 24 is a cross-sectional view of a predetermined manufacturing process in the example of the method for manufacturing the semiconductor device shown in FIG. 23. 図２４に続く製造工程の断面図。FIG. 25 is a cross-sectional view of the manufacturing process following FIG. 24. 従来の半導体装置の一例の断面図。Sectional drawing of an example of the conventional semiconductor device.

符号の説明Explanation of symbols

２０ ベース板
２１ 接着層
２２ 半導体構成体
２３ 半導体チップ
２４ シリコン基板
２５ 接続パッド
２９ 下地金属層
３０ 再配線
３１ 封止膜
３３ 上層下地金属層
３４ 上層再配線
３５ 絶縁膜
３７ 半田ボール DESCRIPTION OF SYMBOLS 20 Base board 21 Adhesion layer 22 Semiconductor structure 23 Semiconductor chip 24 Silicon substrate 25 Connection pad 29 Base metal layer 30 Rewiring 31 Sealing film 33 Upper layer base metal layer 34 Upper layer rewiring 35 Insulating film 37 Solder ball

Claims (9)

半導体基板上に、それぞれ、パッド部を有する複数の再配線が形成された複数の半導体構成体を相互に離間してベース板上に配置する工程と、
前記複数の半導体構成体上を含む前記ベース板の上面全体に絶縁膜を形成する工程と、
前記絶縁膜の上面に、接続パッド部を有し且ついずれかの前記半導体構成体の対応する前記パッド部に接続される上層再配線を、少なくともいずれかの前記上層再配線の接続パッド部が前記半導体構成体間に形成された前記絶縁膜上に配置されるように形成する工程と、
前記ベース板を前記半導体構成体から分離して取り除く工程と、
前記半導体構成体を取り除いて露出された前記半導体構成体の前記半導体基板の裏面を薄くする工程と、
前記各半導体構成体間における前記絶縁膜を切断して少なくともいずれかの前記上層再配線の接続パッド部が前記半導体構成体より外側の領域の前記絶縁膜上に形成された前記半導体構成体を少なくとも１つ有する半導体装置を複数個得る工程とを有することを特徴とする半導体装置の製造方法。 A step of disposing a plurality of semiconductor constructs each having a plurality of rewirings each having a pad portion on a semiconductor substrate on a base plate on a semiconductor substrate;
Forming an insulating film on the entire upper surface of the base plate including the plurality of semiconductor structures;
An upper layer rewiring having a connection pad portion on the upper surface of the insulating film and connected to the corresponding pad portion of any one of the semiconductor structures, and at least any one of the upper layer rewiring connection pad portions is Forming to be disposed on the insulating film formed between the semiconductor structures;
Separating and removing the base plate from the semiconductor structure;
Thinning the back surface of the semiconductor substrate of the semiconductor structure exposed by removing the semiconductor structure;
At least the semiconductor structure in which the insulating film between the semiconductor structures is cut and at least one of the upper layer rewiring connection pad portions is formed on the insulating film in a region outside the semiconductor structure. And a step of obtaining a plurality of semiconductor devices having one semiconductor device. 請求項１に記載の発明において、前記絶縁膜を切断する工程は、前記半導体構成体が複数個含まれるように切断することを特徴とする半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, wherein the step of cutting the insulating film is performed so that a plurality of the semiconductor structures are included. 請求項１に記載の発明において、前記半導体構成体を相互に離間してベース板上に配置する工程は、前記半導体構成体間に埋込材を配置する工程を含むことを特徴とする半導体装置の製造方法。   2. The semiconductor device according to claim 1, wherein the step of disposing the semiconductor structure on the base plate at a distance from each other includes a step of disposing an embedded material between the semiconductor structures. Manufacturing method. 請求項１に記載の発明において前記複数の再配線は、前記半導体基板上に設けられた保護膜上に形成されていることを特徴とする半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, wherein the plurality of rewirings are formed on a protective film provided on the semiconductor substrate. 請求項１に記載の発明において、前記絶縁膜は複数層であり、その層間に、前記各半導体構成体の再配線とそれに対応する前記各組の上層再配線とを接続する複数組の層間再配線を形成する工程を有することを特徴とする半導体装置の製造方法。   In the first aspect of the present invention, the insulating film has a plurality of layers, and a plurality of sets of interlayer reconnections connecting the rewirings of the semiconductor structures and the corresponding upper rewirings of the sets to each other between the insulating films. A method for manufacturing a semiconductor device, comprising a step of forming a wiring. 請求項１に記載の発明において、前記上層再配線を含む前記絶縁膜の上面において前記上層再配線のパッド部を除く部分に最上層絶縁膜を形成する工程を有することを特徴とする半導体装置の製造方法。   2. The semiconductor device according to claim 1, further comprising a step of forming an uppermost insulating film on a portion of the upper surface of the insulating film including the upper layer rewiring except a pad portion of the upper layer rewiring. Production method. 請求項６に記載の発明において、前記上層再配線のパッド部上に突起状の接続端子を形成する工程を有することを特徴とする半導体装置の製造方法。   7. The method of manufacturing a semiconductor device according to claim 6, further comprising a step of forming a protruding connection terminal on the pad portion of the upper layer rewiring. 請求項７に記載の発明において、前記突起状の接続端子は半田ボールであることを特徴とする半導体装置の製造方法。   8. The method of manufacturing a semiconductor device according to claim 7, wherein the protruding connection terminal is a solder ball. 請求項１に記載の発明において、 前記半導体構成体を相互に離間してベース板上に配置する工程は、前記半導体構成体間に埋込材を配置する工程を含み、前記各半導体構成体間における前記絶縁膜を切断する工程は、前記埋込材を切断する工程を含むことを特徴とする半導体装置の製造方法。   2. The invention according to claim 1, wherein the step of disposing the semiconductor structures on the base plate apart from each other includes a step of disposing an embedding material between the semiconductor structures. The method of manufacturing a semiconductor device according to claim 1, wherein the step of cutting the insulating film includes a step of cutting the filling material.
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