JP2007017999A - Manufacturing method of digital-to-analog conversion circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a digital-to-analog conversion circuit, with which high-speed operation can be attained with low electric power consumption and which is simple in configuration, and can be realized on a substrate and the like. <P>SOLUTION: Charges are accumulated in a capacitor 2 by a pulse voltage to be input in a charging period, and the analog voltage of the capacitor provides an output voltage in a hold time. By controlling the pulse width of the input pulse, based on the digital signal, the charges of the amount meeting the pulse width are accumulated and thus, the potential of the output voltage meets the pulse width. There are no paths, where a DC current flows for its circuitry; and since there is no need for accumulating the charges more than necessary, the D/A conversion is enabled at the reduced electric power consumption. Also, the formation of circuits on the display panel of a liquid crystal display device and the like can be attained, because of the simple circuitry and the formability of nonlinear elements by a simple process, such as lamination of metal and insulator. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a digital / analog conversion circuit that outputs an analog voltage corresponding to an input voltage pulse width. In particular, the present invention relates to a digital / analog conversion circuit that is mainly used in an electro-optical device and converts an input pulse having a digitally controlled width into an analog voltage for pixel driving.

  In recent years, liquid crystal display devices and the like have been reduced in size, thickness, performance, and price, and are widely used in various applications. In particular, a reflective liquid crystal display device that does not require a light emitting means such as a backlight consumes little power, and is particularly suitable for portable information devices or communication devices, and reduces the frequency of device charging and battery replacement. There is an advantage that you can.

  In such a liquid crystal display device, various methods for reproducing the intermediate luminance of the pixel have been devised and put into practical use. One of the methods for realizing such gradation display is a method using D / A (digital / analog) conversion. In this method, image data input as a digital signal is converted into an analog voltage by D / A conversion and applied to a pixel electrode. A liquid crystal is sandwiched between the pixel electrode and the common electrode, and this liquid crystal has physical characteristics indicating a correlation between the applied voltage and the light transmittance in a predetermined voltage range. Therefore, pixel brightness corresponding to an input signal is obtained by combining with a reflecting plate that reflects light.

  In the conventional technique, the D / A conversion as described above includes a method using voltage division by resistance (R-DAC) and a method for obtaining a predetermined voltage by charge stored in a capacitor (C-DAC).

  The D / A conversion element described above has the following problems. First, in the case of the R-DAC method, the power is consumed by the current flowing through the resistor. Conventionally, in a display device incorporating a backlight or the like, the amount of power consumed by the D / A conversion element has been relatively small because it is relatively small. As the low power consumption type is developed, the power consumption ratio of the D / A conversion in the whole has increased, so it has become a problem to suppress the power consumption of this portion.

  Secondly, in the case of a C-DAC type capacity, although the power consumption is not so large, there is a problem that sufficient speed operation cannot be obtained because charging and discharging of the capacity takes time. In particular, in a high-definition display with a large number of pixels and a moving image display that requires smooth movement, the timing of the display rewrite cycle becomes more critical, and the influence of this problem becomes large.

  Thirdly, when a driver for driving a liquid crystal such as a TFT (thin film transistor) is built in a display panel having a pixel matrix, these conventional D / A conversion elements occupy a large area and are on the panel. There is a problem that it cannot be mounted and must be provided outside the display panel. If a D / A conversion circuit having a simpler configuration can be built on the display panel, the display device can be configured in a very compact manner and with a small number of parts. Is required.

  The present invention has been made in view of the above circumstances, operates with low power consumption, provides a sufficiently high operation speed, and can be realized on a display panel based on a glass substrate or the like. An object of the present invention is to provide an analog conversion circuit and an electro-optical device using the analog conversion circuit.

  In order to solve the above-described problems, the present invention converts a plurality of bits of digital data to be converted into a pulse signal corresponding to the digital data, and applies the pulse signal to a capacitor via a nonlinear element. The digital / analog conversion method is characterized in that the charging voltage of the capacitor is output as a post-conversion voltage.

  According to such a configuration of the present invention, when a pulse voltage having a width corresponding to the input digital data is applied, an amount of charge corresponding to the pulse width is accumulated in the capacitor, and the amount of charge is further increased. Since the voltage corresponding to is output as the converted voltage, digital / analog conversion can be realized.

  Further, the present invention provides a second pulse width corresponding to digital data to be converted, which is formed by a second voltage set in advance to a signal having a first pulse width of a first voltage set in advance. An offset formed by a preset third voltage after the charging signal is output by charging the capacitor by applying the charging signal to a capacitor through a non-linear element to superimpose the pulse signal of The gist of the digital / analog conversion method is that a signal is applied to the capacitor via the nonlinear element, and after switching to the offset signal, the terminal voltage of the capacitor is output as a converted voltage.

  According to such a configuration of the present invention, an amount of electric charge corresponding to the input digital data is accumulated in the capacitor, and a voltage corresponding to the amount of electric charge is output as a converted voltage, so that digital / analog conversion is performed. realizable.

  Further, the first pulse width signal of the first voltage acts so that a constant charge amount is accumulated in the capacitor regardless of the input digital data, and therefore the lower limit of the variable charge amount accumulated in the capacitor. The effect is that the minute can be charged in a certain time. Further, since the second pulse signal superimposed on the pulse width of the first voltage has a width corresponding to the input digital data, it acts to accumulate the variable portion of the variable charge amount in the capacitor. . In addition, since the first pulse signal and the second pulse signal are superimposed, it is not necessary to individually take the timing of applying each voltage, and this digital / analog conversion method is applied to a circuit or device whose charging time is critical. When applied, it is advantageous in terms of timing.

  In this method, it is assumed that the voltage of the charging signal and the voltage of the offset signal have the same sign. Therefore, no matter how small the amount of charge accumulated in the capacitor, the absolute value of the converted output voltage does not fall below the absolute value of the offset voltage. Therefore, by determining the voltage of this offset signal according to the desired output voltage range, the amount of charge accumulated in the capacitor can be minimized, and therefore the input pulse voltage and the capacitance of the capacitor can be reduced. As a result, the degree of freedom in designing a circuit or a device to which the present method is applied is increased.

  The present invention also provides a conversion means for converting a plurality of bits of digital data to be converted into a pulse signal corresponding to the digital data, a non-linear element to which the pulse signal is applied, and an output of the non-linear element. A capacitor, and the capacitor voltage charged by the pulse signal is output as a converted voltage, the voltage of the pulse signal is inverted, and the input / output characteristics of the nonlinear element is the voltage of the pulse signal. The gist of the present invention is a digital / analog conversion circuit characterized in that the characteristics are symmetrical regardless of the polarity.

  With this configuration of the present invention, the digital / analog conversion method described above can be realized as a circuit.

  In addition, since there is no path through which a direct current flows, the amount of current flowing through this circuit can be kept low, so that the amount of power consumption can be reduced as compared with a digital / analog conversion circuit using voltage division of resistors in the prior art. In addition, since there is no output delay due to a large number of capacitors, there is an effect that a high-speed operation can be realized as compared with a digital / analog conversion circuit based on voltage division of a conventional capacitor. In addition, the part of the circuit that converts the width of the pulse signal to the output voltage by charging / discharging has a simple configuration of a non-linear element and a capacitor, and has an effect that it can be realized on a substrate or the like with a relatively small area.

  Further, the present invention provides a second pulse width corresponding to digital data to be converted, which is formed by a second voltage set in advance to a signal having a first pulse width of a first voltage set in advance. A charge signal forming circuit that forms and outputs a charge signal by superimposing the pulse signal, outputs an offset signal formed by a preset third voltage after outputting the charge voltage, and the charge signal and A non-linear element to which the offset signal is applied; and a capacitor to which the output of the non-linear element is applied; after the charging signal forming circuit switches the output to the offset signal, the terminal voltage of the capacitor is converted The gist of the present invention is a digital / analog conversion circuit that outputs voltage.

  With this configuration of the present invention, the digital / analog conversion method described above can be realized as a circuit. Further, as described above, since the pulse signal based on the first voltage and the pulse signal based on the second voltage are superimposed, the variable charge amount in a desired range can be stored in the capacitor in the minimum necessary time. Further, as described above, since the offset signal is output after the charging signal is output, an output voltage in a desired range can be realized with a minimum necessary accumulated charge amount. As a result, there is a margin in the capacitance of the capacitor in circuit design, and there is an effect that it can be realized with a relatively small area on the substrate or the like.

  In the present invention, the nonlinear element has a metal-insulator-metal structure in which a chrome (Cr) or aluminum (Al) electrode is laminated on an anodized tantalum (Ta) or aluminum (Al). It is preferable to have it.

  With such a configuration of the present invention, a non-linear element having current-voltage characteristics suitable for digital / analog conversion with low power consumption can be realized. In addition, since such a structure can be formed on a substrate, when the digital / analog conversion circuit according to the present invention is used for an electro-optical display device or the like, the circuit may be incorporated on the display panel. There is an effect that the size can be reduced.

  In the present invention, the nonlinear element having a metal-insulator-metal structure preferably has a back-to-back structure.

  According to such a configuration of the present invention, since a nonlinear element having a symmetric structure of metal 1-insulator-metal 2-insulator-metal 1 is used in a circuit, a current-voltage symmetric with respect to the polarity of voltage application. Characteristics can be obtained.

  Therefore, when the digital / analog conversion circuit according to the present invention is used for an electro-optical display device or the like, even if AC driving is performed to invert the polarity of the applied voltage every horizontal scanning period, the difference in output voltage due to the difference in polarity occurs. Since it does not appear, the effect that the accuracy of gradation display can be improved is obtained.

  In the present invention, the nonlinear element is preferably a diode using p-type or n-type silicon (Si).

  With such a configuration of the present invention, a non-linear element having current-voltage characteristics suitable for digital / analog conversion with low power consumption can be realized. In addition, since such a structure can be formed on a substrate, when the digital / analog conversion circuit according to the present invention is used for an electro-optical display device or the like, the circuit may be incorporated on the display panel. There is an effect that the size can be reduced.

  In the present invention, it is preferable that the non-linear element is constituted by a parallel connection of two diodes arranged in opposite directions.

  According to such a configuration of the present invention, since a non-linear element having a symmetric polarity is used in the circuit, current-voltage characteristics that are symmetric with respect to the polarity of voltage application can be obtained.

  Therefore, when the digital / analog conversion circuit according to the present invention is used for an electro-optical display device or the like, even if AC driving is performed to invert the polarity of the applied voltage every horizontal scanning period, the difference in output voltage due to the difference in polarity occurs. Since it does not appear, the effect that the accuracy of gradation display can be improved is obtained.

  In the present invention, the capacitance of the capacitor is preferably in the range of 2 to 8 times the capacitance of the nonlinear element.

  According to such a configuration of the present invention, the dynamic range of the output voltage can be widened. Therefore, when an electro-optical display device or the like is configured using the digital / analog conversion circuit according to the present invention, it is advantageous in controlling gradation display. In addition, the resistance value of the nonlinear element can be made sufficiently large by such a configuration of the present invention, so that power consumption can be reduced.

  The present invention also relates to a plurality of pixels arranged in a matrix on a substrate, a plurality of intersecting data lines and a plurality of scanning lines arranged between the pixels on the substrate, and the pixels. A plurality of switching means for driving the pixels under the control of the scanning line and data line signals, a scanning line driving means for scanning the scanning lines, and at least one for each data line. Data line driving means for driving the data line, the data line driving means being adapted to convert the display data into a pulse signal having a width corresponding to the display data, and to which the pulse signal is applied. An electro-optical device comprising: a non-linear element, and a capacitor to which an output of the non-linear element is applied, and outputs a charging voltage of the capacitor to the data line. .

  According to such a configuration of the present invention, gradation is obtained by applying a voltage corresponding to display data to a pixel using a digital / analog conversion circuit that is relatively simple, capable of high-speed operation, and has low power consumption. An electro-optical device that performs display can be realized. Since the configuration of the digital / analog conversion circuit is simple, the configuration of the digital / analog conversion portion provided on the pixel panel or in the peripheral portion can be simplified. In addition, since a high-speed operation is possible, it is possible to have a margin in display timing, to enable high-definition display and to shorten a scanning cycle. Further, since the digital / analog conversion unit has low power consumption, an effect of further lowering power consumption can be obtained in a device with low power consumption of the entire device such as a reflective liquid crystal display device.

  The present invention also relates to a plurality of pixels arranged in a matrix on a substrate, a plurality of intersecting data lines and a plurality of scanning lines arranged between the pixels on the substrate, and the pixels. A plurality of switching means for driving the pixels under the control of the scanning line and data line signals, a scanning line driving means for scanning the scanning lines, and at least one for each data line. And a data line driving means for driving the data line, wherein the data line driving means applies a signal having a first pulse width of a preset first voltage to a signal having a preset second voltage. An offset voltage formed by a preset third voltage after forming and outputting a charge signal by superimposing a second voltage having a pulse width corresponding to display data, which is formed, and outputting the charge signal The A charging signal forming circuit to be applied, a nonlinear element to which the charging signal and the offset signal are applied, and a capacitor to which an output of the nonlinear element is applied, and outputting a terminal voltage of the capacitor to the data line. The gist of the electro-optical device is as follows.

  According to such a configuration of the present invention, as described above, by superimposing the pulses by the first and second voltages, the charging voltage application timing can be used effectively, and the offset voltage is applied. Thus, even when the digital / analog conversion unit is provided on the substrate, it can be realized with a small area. Thereby, there is an effect that high speed operation and downsizing of the entire apparatus can be realized.

  In the present invention, the data line driving means has a switching means at an output portion to the data line, and the switching means is turned off when the charging signal is applied to the nonlinear element. It is preferable that the capacitor terminal and the data line are electrically cut off and turned on when the offset signal is applied to electrically connect the capacitor terminal and the data line.

  According to such a configuration of the present invention, when charge is accumulated in the capacitor by the pulse signal generated according to the input digital signal, the influence of the wiring capacitance of the data line and other stray capacitance can be reduced. it can. Therefore, it is possible to obtain an effect that the circuit operation can be made efficient and the accuracy of digital / analog conversion can be improved.

  In the present invention, it is preferable that the capacitor is a wiring capacitance of the data line.

  With such a configuration of the present invention, it is not necessary to provide a capacitor in the data line driving means, and the circuit configuration can be further simplified and the device can be further downsized.

  The present invention also relates to a plurality of pixels arranged in a matrix on a substrate, a plurality of intersecting data lines and a plurality of scanning lines arranged between the pixels on the substrate, and the pixels. A plurality of switching means for driving the pixels under the control of the scanning line and data line signals, a scanning line driving means for scanning the scanning lines, and at least one for each data line. Data line driving means for driving the data line, the data line driving means converting the display data into a pulse signal corresponding to the display data, and a first to which the pulse signal is applied. , The second nonlinear element, the first and second capacitors to which the outputs of the first and second nonlinear elements are respectively applied, and the charging voltages of the first and second capacitors are set to the scanning line Run And gist an electro-optical device characterized by comprising a second switching means for outputting to the data lines alternately based on the timing.

  According to such a configuration of the present invention, since the charging signal and the offset signal of the first and second capacitors are output to one data line at different timings, the voltage of the digital / analog conversion result is applied to the data line. The output time can be taken longer.

  In the electro-optical device having such a configuration, a pulse signal of a charging signal is generated based on data for one pixel, the timing is shifted and the first and second capacitors are charged, and the output voltage is continuously generated at different timings. In particular, if the voltage is applied to one pixel, the driving time of one pixel can be extended. In addition, if the pulse signal of the charging signal is generated based on the data for two pixels, the first and second capacitors are charged respectively, and the output voltage is applied to different pixels at different timings, The number of drive pixels per unit time can be increased. As a result, it is possible to achieve an effect that a high-definition display and smooth moving image display by high-speed scanning can be realized.

  The present invention also relates to a plurality of pixels arranged in a matrix on a substrate, a plurality of intersecting data lines and a plurality of scanning lines arranged between the pixels on the substrate, and the pixels. A plurality of switching means for driving the pixels under the control of the scanning line and data line signals, a scanning line driving means for scanning the scanning lines, and at least one for each data line. And a data line driving means for driving the data line, wherein the data line driving means applies a signal having a first pulse width of a preset first voltage to a signal having a preset second voltage. An offset formed by a preset third voltage after the charge signal is formed and output by superimposing the second pulse signal having a pulse width corresponding to the display data to be formed, and outputting the charge signal. Output signals of the first and second charging signal forming circuits, the first and second nonlinear elements to which the output of the charging signal forming circuit is applied, and the outputs of the first and second nonlinear elements are First and second capacitors respectively applied, and second switching means for alternately outputting charging voltages of the first and second capacitors to the data lines based on the scanning timing of the scanning lines. The gist of the electro-optical device is as follows.

  According to such a configuration of the present invention, since the charging voltages of the first and second capacitors are output to one data line at different timings, the voltage of the digital / analog conversion result is output to the data line. You can take a long time. As a result, as described above, it is possible to achieve an effect that a high-resolution display and a smooth moving image display by high-speed scanning can be realized.

  In addition, according to such a configuration of the present invention, as described above, it is possible to effectively use the charging voltage application timing by superimposing the pulses of the first and second voltages, and the offset voltage. By applying this, even when the digital / analog conversion portion is provided on the substrate, it can be realized with a small area. Thereby, there is an effect that high speed operation and downsizing of the entire apparatus can be realized.

  In the present invention, it is preferable that the capacitance of the capacitor is at least three times the capacitance between the pixel electrode and the common electrode in the pixel.

  According to such a configuration of the present invention, charges are accumulated by a sufficiently large capacity compared to the capacity of the pixel, and the level of the output voltage is controlled by the amount of the charge, so that the accuracy of digital / analog conversion is improved, Therefore, an effect that the accuracy of gradation display of the electro-optical device can be improved is obtained.

  In the present invention, it is preferable that the capacitance of the capacitor is 10 times or more the capacitance between the pixel electrode and the common electrode in the pixel.

  According to such a configuration of the present invention, charges are accumulated by a larger capacity than the capacity of the pixel, and the level of the output voltage is controlled by the amount of the charge, so that the accuracy of digital / analog conversion is further increased. Therefore, there is an effect that the accuracy of gradation display of the electro-optical device can be further improved.

  The present invention also includes a first step of forming a pattern of input electrode wiring and output electrode wiring with tantalum (Ta) or aluminum (Al) on a substrate, and anodizing the input electrode wiring and the output electrode wiring. A second step of forming an oxide layer having a thickness in the range of 20 nanometers to 80 nanometers, and an annealing process at a temperature in the range of 300 degrees Celsius to 500 degrees Celsius. Step 4 and forming an electrode pattern that bridge-connects the oxide layer formed on the input electrode wiring and the oxide layer formed on the output electrode wiring by aluminum (Al) or chromium (Cr). And a digital / analog conversion circuit manufacturing method characterized by comprising:

  According to such a configuration of the present invention, the following nonlinear element can be formed on the substrate. That is, an electrode at one end formed in the first process, an insulating layer formed in the second and third processes, an intermediate electrode formed in the fourth process, and the second and again A non-linear element in which an insulating layer formed in the third process and an electrode at the other end formed in the first process are electrically connected in series. In addition, since such an element manufactured by the method of the present invention has a back-to-back structure, it has voltage-current characteristics that are symmetrical with respect to polarity. For example, in an electro-optic display device, the polarity of an applied voltage is different for each line. Suitable for AC drive circuit to be inverted.

The present invention also provides a first process of forming a pattern of input electrode wiring and output electrode wiring with a polysilicon film on a substrate, and a hydrogen treatment by a chemical vapor deposition apparatus on the input electrode wiring and the output electrode wiring. A second process of forming a silicon nitride (SiN _x : H) to a thickness in the range of 20 to 80 nanometers to form an insulating layer, and the insulation formed on the input electrode wiring And a third step of forming an electrode pattern that bridge-connects the insulating layer formed on the output electrode wiring and the output electrode wiring.

  According to such a configuration of the present invention, the following nonlinear element can be formed on the substrate. That is, one end electrode formed in the first process, an insulating layer formed in the second process, an intermediate electrode formed in the third process, and formed again in the second process. And a non-linear element in which an electrode at the other end formed in the first process is electrically connected in series. In addition, since such an element manufactured by the method of the present invention has a back-to-back structure, it has voltage-current characteristics that are symmetrical with respect to polarity. For example, in an electro-optic display device, the polarity of an applied voltage is different for each line. Suitable for AC drive circuit to be inverted.

  In the present invention, it is preferable to have a capacitor forming process in which a capacitor element is formed on the substrate with the same structure and process as the storage capacitor of the pixel.

  According to such a configuration of the present invention, it is possible to build in and provide a capacitor dedicated to the digital / analog conversion circuit in parallel with the process of forming the storage capacitor of the pixel portion, and form a capacitor dedicated to the digital / analog conversion circuit. This process and the process for forming the pixel electrode can be made common, so that the manufacturing cost and the manufacturing time can be reduced.

  In the present invention, it is preferable to have a switching means forming process for forming a switching element for turning on / off the digital / analog conversion output on the substrate with the same structure and process as the pixel switching thin film transistor.

  According to such a configuration of the present invention, it is possible to provide the output switching element of the digital / analog conversion circuit on the same panel as the pixel portion of the electro-optical device, and there is an effect that the size of the device can be reduced. In addition, since the process of forming the output switching element of the digital / analog conversion circuit and the process of forming the pixel switching element can be made common, the manufacturing cost and manufacturing time can be reduced.

  An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a basic configuration of a D / A (digital / analog) conversion circuit according to the embodiment. In this figure, reference numeral 1 is an equivalent circuit of a nonlinear element, and reference numeral 2 is a capacitor. The non-linear element 1 and the capacitor 2 are connected in series, and an input voltage pulse Vin is applied to one end of the non-linear element 1, and the potential Vout of the connection portion between the non-linear element 1 and the capacitor 2 Is output.

  FIG. 2 is a graph showing current-voltage characteristics of the nonlinear element 1. As shown in this figure, the non-linear element 1 has a very high resistance value in a voltage range smaller than a predetermined voltage. However, as the applied voltage is increased, the resistance value gradually decreases and a large amount of current flows. become. Further, as shown in the equivalent circuit in FIG. 1, the nonlinear element 1 also has a capacitance component in the element itself. A specific configuration, structure, and manufacturing method of such a nonlinear element 1 will be described later.

  Next, the principle of D / A conversion by the circuit shown in FIG. 1 will be described. FIG. 3A is a timing chart showing respective waveforms of the input voltage Vin and the output voltage Vout of the D / A conversion circuit. In FIG. 3A, the waveform of the input voltage Vin is indicated by a dotted line 101, and the waveform of the output voltage Vout is indicated by a solid line 102. The minimum unit of operation of this circuit is composed of two phases of a charging period and a holding period. The range indicated by t1 in FIG. 3A is the charging period, and the range indicated by t2 is the holding period. In FIG. 3A, the charging period t1 and the holding period t2 have the same length. However, in the implementation of the present invention, this is not necessarily the same.

  First, when a pulse voltage having a potential of + V1 is input during the charging period, first, Vout changes according to the capacitance ratio of the capacitance component included in the nonlinear element 1 and the capacitor 2, and then passes through the nonlinear element 1. The capacitor 2 starts to be charged, and the output voltage Vout gradually rises accordingly. When a certain time elapses, the potential of + V2 is further added, the input voltage Vin becomes (V1 + V2), and the output voltage Vout rises following it. Here, the time during which (V1 + V2) is input, that is, the pulse width is td1. The amount of electric charge stored in the capacitor 2 and the magnitude of Vout reflecting it are determined by the magnitudes of the pulse voltages + V1, + V2 and the time during which they are applied, such as t1, td1.

  Further, since the resistance value of the non-linear element changes depending on the voltage applied to the non-linear element, that is, the difference between the input voltage Vin and the output voltage Vout, the resistance value is relatively low during the charging period t1 when a high write voltage is applied. It changes with the resistance and works so that the capacitor 2 is charged. During the holding period described below, the resistance becomes high and the charge stored in the capacitor 2 is held.

  Next, when the input voltage Vin falls to + V3 at the beginning of the holding period, the output voltage Vout also falls according to the capacitance ratio of the capacitance component included in the nonlinear element 1 and the capacitor 2, but thereafter the nonlinear element 1 Since the potential applied to the capacitor is small and the resistance of the nonlinear element is large, the charge accumulated in the capacitor 2 is not discharged and the magnitude of Vout does not change.

  In a display device having a resolution such as VGA to XGA, the charging period t1 and the holding period t2 are on the order of several tens to several hundreds of microseconds or less.

  As a result of the above operation, the output voltage Vout in this holding period has a positive correlation with the amount of charge accumulated in the capacitor 2, so that the voltage pulse width td1 of (V1 + V2) is obtained by pulse width modulation (PWM) of the digital signal. By controlling, an analog voltage output corresponding to the control can be obtained. As the potentials V1, V2, and V3 of the input pulse, appropriate values according to circuit constants such as a desired output voltage range, a resistance value, and a capacitance value are used.

  In the waveform shown in FIG. 3A, a positive voltage is input during the first charging period and a negative voltage is input during the next charging period. In this case, pixel driving is performed using a voltage whose polarity is inverted for each scanning line. This circuit is configured such that the input / output relationship has a positive / negative symmetrical characteristic that does not depend on the polarity of the voltage.

  One of the following two types can be used as the nonlinear element of this circuit. The first is an element having an MIM (metal-insulator-metal) structure in which an electrode such as chromium or aluminum is laminated on anodized tantalum or aluminum. In order to obtain the above-described polarity symmetric input / output characteristics, a back-to-back structure in which the MIM elements are connected in series in the reverse direction is adopted. Specifically, for example, an element having a laminated structure of chromium-tantalum oxide film-tantalum-tantalum oxide film-chromium is used.

  The second is a diode structure using p-type or n-type silicon. In order to obtain polarity symmetric input / output characteristics in this diode structure, a ring structure (DR) in which two diode elements are connected in parallel in opposite directions is used.

  Next, a first embodiment in which a liquid crystal display device (electro-optical device) is configured using the above-described D / A conversion circuit will be described. FIG. 4 is a circuit diagram showing a D / A conversion unit and a pixel unit of the liquid crystal display device according to the embodiment. In this figure, reference numeral 10 denotes a D / A conversion unit, and 20 denotes a pixel unit.

  In the pixel portion 20, the pixels 11 are arranged in a matrix, and the data lines 14 are arranged in the vertical direction and the scanning lines 15 are arranged in the horizontal direction. The pixel electrode switching element 12 in the pixel 11 is on / off controlled by the voltage of the scanning line 15, and the voltage of the data line 14 is applied to the pixel electrode only when it is on. The light transmittance of the liquid crystal 13 sandwiched between the pixel electrode and the common electrode changes according to the applied voltage.

  The D / A conversion unit 10 is provided with a D / A conversion circuit including the nonlinear element 1 and the capacitor 2 corresponding to each data line 14. The D / A conversion output switching element 3 provided at the output portion of the D / A conversion circuit and realized by a transistor is on / off controlled by the voltage of the D / A conversion timing switching signal line 4. .

  FIG. 5 is a block diagram showing the overall configuration of this apparatus including peripheral circuits. In this figure, reference numeral 31 is a liquid crystal panel substrate, and 32 is a scanning driver for driving the scanning lines 15. In addition, the data driver 33 receives voltages of ± V1, ± (V1 + V2), ± V3 from the voltage supply source 34, and sends a pulse waveform corresponding to the pulse width data output from the data modulation circuit 35 to the D / A converter 10. Output.

  Next, the circuit operation of this apparatus will be described. The input display data is first converted by the data modulation circuit 35 into pulse input timing data corresponding to the luminance for each pixel. This conversion is performed as follows. The data modulation circuit 35 is provided with pulse input timing storage means realized by a semiconductor ROM or the like, and this pulse input timing storage means raises a pulse having a potential of (V1 + V2) at any timing during the charging period. It is stored according to each brightness whether it should be increased.

  For example, as shown in FIG. 3A, in order to input a pulse having a width of td1, the potential is changed from V1 to (V1 + V2) at the time when (t1-td1) has elapsed after the start of the charging period. Just start up. Since the entire apparatus is synchronized by the reference clock pulse generated by the reference clock generation circuit 36, specifically, the timing is controlled using the number of reference clock pulses. Although the clock pulse width td1 and the transmittance of the pixel have a correlation, the relationship is non-linear due to the stray capacitance of the data line 14 and the electro-optical characteristics of the liquid crystal. Therefore, the above-mentioned pulse input timing storage means stores, for example, 64 reference clock pulse count values corresponding to each stage for displaying gradations in 64 stages from 0 to 63.

  The pulse timing data for each pixel generated in this way is transferred from the data modulation circuit 35 to the data driver 33, and each pixel is driven as follows using this data. The scanning driver 32 sequentially scans the scanning lines 15 from above based on the input vertical synchronization signal and horizontal synchronization signal. FIGS. 3C and 3D are timing charts showing potentials of two adjacent scanning lines. As shown in FIG. 3, the potential of the scanning line 15 at the timing of scanning is “H”. It becomes level and becomes “L” level at other timings.

  In synchronization with the scanning timing, the data driver 33 uses the basic potentials ± V1, ± (V1 + V2), ± V3 supplied from the voltage supply source 34 based on the timing data passed from the data modulation circuit 35. A voltage pulse having a waveform as shown in FIG. 3A is input to a D / A converter circuit corresponding to each pixel of the D / A converter 10.

  FIG. 6 is a circuit diagram showing a configuration of a pulse wave generation circuit built in the data driver 33. The data driver 33 inputs the signals S1 to S7 to the switches 41 to 47, thereby switching the six types of voltages and the common voltage COM received from the voltage supply source 34, generating a desired pulse waveform, and generating the D / A Output to the converter.

  A pulse signal as shown in FIG. 3B is supplied to the D / A conversion timing switching signal line 4. During the charging period, since this pulse potential is “L”, the D / A conversion output switching element 3 is turned off, and the output voltage of the D / A conversion circuit is not transmitted to the data line 14. The capacitor 2 is stored without leaking to the stray capacitance. Further, during the holding period, the D / A conversion timing switching signal line 4 becomes “H” level, the D / A conversion output switching element 3 is turned on, and the output voltage of the D / A conversion circuit is applied to the data line 14. Is done.

  As shown in FIG. 3, the scanning timing of the scanning line 15 described above and the timing of applying the output voltage of the D / A conversion circuit to the data line 14 are synchronized. When the scanning line 15 is at the “H” level, the pixel electrode switching element 12 connected to the scanning line 15 is turned on, and the potential of the data line 14 connected to the pixel electrode switching element 12 is applied to the pixel electrode, The liquid crystal 13 of the pixel changes to a state corresponding to the applied voltage. Further, the pixel electrode switching element 12 is turned off at the “L” level.

  As described above, the digital signal based on the input image data is converted into an analog voltage by the D / A conversion circuit, and this voltage is applied to the pixel electrode in synchronization with the scanning line timing, thereby displaying a gradation. I do.

  In this device, the range of the voltage applied to the pixel electrode is determined by the liquid crystal to be used, and the voltage range can be realized, and the resistance value and capacitance value of the nonlinear element 1 and the capacitor 2 are also considered. The basic voltages V1, (V1 + V2), and V3 are selected in advance so that they can be supplied from the voltage supply source 34.

  In addition, the pixel transmittance according to the pulse width is measured in advance by experiment, and the pulse width of each signal is determined based on the measurement result so that the gradation at equal intervals according to the display data can be reproduced. The pulse input timing data is stored in the pulse input timing storage means in the data modulation circuit 35.

  In this embodiment, the scanning driver 32, the data driver 33, and the D / A conversion unit 10 are formed on the liquid crystal panel substrate 31, but either one or both of the scanning driver 32 and the data driver 33 are outside the substrate. It may be incorporated in the IC. Furthermore, the D / A converter 10 may be incorporated in an IC outside the substrate.

  Next, a second embodiment of the electro-optical device of the invention will be described. FIG. 7 is a circuit diagram showing a configuration of a D / A conversion unit and a pixel unit of the liquid crystal display device according to the embodiment. The circuit shown in this figure is different from the circuit of the first embodiment shown in FIG. 4 in that the D / A conversion unit 10 does not have a capacitor dedicated to D / A conversion, and instead, the pixel unit 20 includes This is that the capacity 51 of the arranged data line 14 itself is used. With this configuration, the D / A conversion unit 10 does not require the D / A conversion output switching element 3 and the D / A conversion timing switching signal line 4, and the circuit configuration can be further simplified.

  The timing of D / A conversion and pixel driving of this apparatus will be described with reference to FIG. A voltage pulse having a waveform and timing as shown in FIG. 3A is input to the D / A conversion circuit.

  In the first charging period shown in FIG. 3A, the potential levels of all the scanning lines 15 are “L”, and therefore, all the pixel electrode switching elements 12 are turned off. A positive charge is accumulated in the wiring capacitor 51 by this pulse. In the next holding period, the input potential falls to V3, and an analog voltage corresponding to the input pulse width td1 is applied to the data line. At this time, the non-linear element constituting the D / A conversion unit has a high resistance because the applied voltage is low, and the analog potential of the data line is held. In synchronization with this, as shown in FIG. 3C, the potential level of the scanning line 15 currently undergoing scanning becomes “H”, and the pixel electrode switching element 12 connected to the scanning line 15 is turned on. Therefore, the potential of the data line 14 is applied to the pixel electrode. During the next charging period and holding period, a negative potential pulse is input to the D / A conversion circuit, and the same operation is performed for the next scanning line 15.

  About parts other than the D / A conversion part 10 and the pixel part 20, it is an apparatus structure as shown by FIG. 5 similarly to the case of 1st Embodiment.

  Since the D / A converter in this embodiment has a simple structure that does not have a dedicated capacitor, a D / A conversion output switching element, and a D / A conversion timing switching signal line, it is further formed on the liquid crystal panel substrate. There is a merit that it is easy to do.

  Next, a third embodiment of the electro-optical device according to the invention will be described. FIG. 8 is a circuit diagram showing a configuration of the D / A conversion unit and the pixel unit of the liquid crystal display device according to the embodiment. The feature of this configuration is that two sets of D / A conversion circuits and D / A conversion output switching elements connected thereto are present in parallel, and their outputs are combined and connected to one data line 14. That is.

  The nonlinear elements 1a and 1b receive separate input signals, and the D / A conversion output switching elements 3a and 3b are turned on / off by separate D / A conversion timing switching signal lines 4a and 4b, respectively. Be controlled.

  The operation timing of this apparatus will be described with reference to the drawings. FIG. 9 is a timing chart showing the operations of the D / A conversion unit 10 and the pixel unit 20 of the present apparatus. In this figure, the waveforms indicated by (a) and (b) are input voltage pulses applied to the non-linear elements 1a and 1b, respectively. For example, “Ha (m)” in the figure represents a horizontal scanning period in which the pixels connected to the mth scanning line 15 are scanned through the nonlinear element 1a. Similarly, “Hb (m)” is a horizontal scanning period in which scanning is performed via the nonlinear element 1b, and “Hb (m)” has a phase delayed by a half horizontal scanning period from “Ha (m)”. .

  FIGS. 9C and 9D are signal waveforms of the D / A conversion timing switching signal lines 4a and 4b, respectively. Both of them alternately transmit signals in which “H” and “L” are reversed, and therefore each D / A conversion output switching element 3a and 3b is turned on during the holding period of each D / A conversion circuit. It becomes.

  FIG. 9E shows the waveform of the pulse signal of the mth scanning line 15. In the first half of the period when the pulse rises and is at the “H” level, the voltage output via the D / A conversion output switching element 3a is applied to the data line 14, and the second half of the period is A voltage output via the D / A conversion output switching element 3 b is applied to the data line 14. In this way, the D / A conversion output is applied to the pixel electrode through one horizontal scanning period shown in FIG. FIG. 9F shows the pulse waveform of the (m + 1) th scanning line 15, and the same operation is performed by a negative input voltage during this horizontal scanning period.

  As in the above-described operation, this apparatus has a timing advantage that a driving period twice as long as one pixel can be taken as compared with the apparatuses described in the first and second embodiments. . That is, at the timing shown in FIG. 3, the first half of the scanning selection period assigned to the pixel is used for charging the D / A converter capacitor and the second holding period is used for writing to the pixel. The entire selection period can be used for writing to the pixels. This is particularly effective in a display body that sometimes has a large number of scanning lines and a short selection period per scanning line.

  In addition, since the signal of each pixel is determined by the combination of the drive signals composed of two parts such as “Ha (m)” and “Hb (m)”, there is an advantage that finer gradation control is possible. is there. That is, the output voltage for 64 gradations can be obtained by generating data for 32 gradations in each D / A converter and combining them.

  Further, as described above, the voltage is applied to the pixel electrode connected to one scanning line 15 in both the period in which the voltage is output via the switching element 3a and the period in which the voltage is output via the switching element 3b. Instead of applying, the scanning of the next scanning line 15 may be performed at the switching timing of the switching elements 3a to 3b. In this case, the waveform of the pulse signal of the scanning line 15 is as shown in FIG. 9 (g), (h), (i), and (j).

  By performing such an operation, as in the previous example, the entire scan selection period can be used for writing to the pixels. Further, in this case, in order to invert the polarity for each scanning line, the signal in FIG. 9B is required to have the polarity inverted, and the Ha ( m) and Hb (m) are applied signals to adjacent scanning lines.

  The first to third embodiments of the electro-optical device have been described above. Next, the capacity of the D / A conversion circuit incorporated in these devices will be described. First, the capacitance C2 of the capacitor 2 is preferably in the range of 2 to 8 times the capacitance C1 of the nonlinear element 1, and particularly preferably about 4 times. The same applies to the nonlinear element 1 and the wiring capacitance 51 of FIG.

  The reason for this is clear from experiments conducted by the inventors that the dynamic range of the analog output voltage can be maximized when the ratio is about 4 times, which is advantageous for gradation display. Because. When the input voltage is V, the voltage applied to the nonlinear element 1 at the timing when the input voltage is applied is V · C2 / (C1 + C2). However, when the ratio is twice or less, a voltage sufficient for the nonlinear element 1 is obtained. Is no longer applied, which is inconvenient. Further, the resistance value of the element has a positive correlation with the capacitance due to the structure of the nonlinear element 1 in which the insulating thin film is sandwiched between metals. Therefore, in a circuit configuration in which this ratio is 8 times or more, the resistance value as well as the capacitance of the nonlinear element 1 becomes relatively small, which is inconvenient from the viewpoint of reducing power consumption.

  Next, the capacitance C2 is preferably at least 3 times the liquid crystal capacity per pixel, and more preferably at least 10 times. When this ratio is low, particularly when the liquid crystal capacity is relatively large because it is three times or less, the capacitor potential of the D / A converter cannot be accurately transmitted to the pixel during the holding period, and the accuracy of gradation display is reduced. Can not be high.

  In the configuration of the device, the capacitance value is determined so as to satisfy the two conditions described here, and a capacitor suitable for this is incorporated in the circuit, or the data line 14 so that the wiring capacitance 51 corresponding to this is obtained. Determine the thickness of the.

  Further, as a characteristic of the nonlinear element 1, when the applied voltage changes in the range of 4V to 10V, the value of the flowing current is changed 100 times or more.

  Next, a manufacturing method for forming such a D / A conversion circuit on a liquid crystal panel substrate will be described.

  First, a first method for forming an MIM element having a back-to-back structure as a nonlinear element on a substrate will be described.

  In this method, first, in a first process, an electrode made of tantalum or aluminum is formed on a base film formed of a Ta or Si oxide film on a glass substrate. FIG. 10A is a plan view at a stage where this electrode is formed, and FIG. 10B is a cross-sectional view taken along line 591 in FIG. In FIG. 10, reference numeral 501 denotes a substrate, 502 denotes a base film on the substrate, and 511 and 521 denote electrodes of nonlinear elements formed by this process.

  Next, in the second process, the electrodes 511 and 521 are anodized at a voltage of 10 to 40 V using citric acid or the like as a chemical conversion solution. As a result, an oxide layer having a thickness in the range of 20 to 80 nanometers is formed on the electrode surface. FIG. 11A is a plan view at the stage where this oxide layer is formed, and FIG. 11B is a cross-sectional view taken along line 592 in FIG. In FIG. 11, reference numerals 512 and 522 denote oxide layers formed on the electrodes 511 and 521, respectively. The oxide layers 512 and 522 serve as insulating films in the nonlinear element formed by this process.

  Next, in the third process, annealing is performed at a temperature of 300 to 500 degrees Celsius for about 1 hour. By this annealing treatment, the oxide layers 512 and 522 become dense, so that the reliability of the formed element is improved.

  Finally, in the fourth process, an upper electrode pattern is formed of aluminum or chromium. FIG. 12A is a plan view at the stage where the upper electrode is formed, and FIG. 12B is a cross-sectional view taken along line 593 in FIG. In FIG. 12, reference numeral 531 denotes an upper electrode, and the upper electrode 531 is formed in a pattern that bridges the oxide layers 512 and 522.

  By the above-described process, two MIM elements denoted by reference numerals 510 and 520 in FIG. 12A are formed. For example, in the case where the electrode is formed using tantalum in the first process and the electrode is formed using aluminum in the fourth process, the tantalum − is formed between the electrodes 511 and 521 as described above. A non-linear element having a back-to-back structure of tantalum oxide-aluminum-tantalum oxide-tantalum is formed on the substrate.

  Next, a second method for forming a nonlinear element having a back-to-back structure on a substrate will be described. First, in the first step of this method, patterns of input electrodes and output electrodes are formed on a substrate by a polysilicon film. A plan view and a cross-sectional view of the substrate at the stage where these electrodes are formed are the same as FIGS. 10A and 10B, respectively.

Next, in the second step, 20N of silicon nitride (SiN _x : H) subjected to hydrogen treatment by a PECVD (Plasma Enhanced Chemical Vapor Deposition) apparatus is formed on the input electrode and the output electrode. A film is formed to a thickness of nanometer to 80 nanometer to form an insulating layer. A plan view and a cross-sectional view of the substrate at the stage where these insulating layers are formed are the same as FIGS. 11A and 11B, respectively.

  Finally, in the third step, an upper electrode is formed that bridge-connects the insulating layer formed on the input electrode and the insulating layer formed on the output electrode. A plan view and a cross-sectional view of the substrate at the stage where the upper electrode is formed are the same as FIGS. 12A and 12B, respectively.

  A diode using a junction of p-type and n-type semiconductors may be used as the nonlinear element. At this time, in order to obtain positive-negative symmetry in the electrical characteristics of the nonlinear element, it is preferable to have a ring structure in which two diodes arranged in opposite directions are connected in parallel.

  As described above, various manufacturing methods for forming a non-linear element on a substrate have been described. However, when a capacitor dedicated to a D / A conversion circuit is provided on the same substrate, it is formed by the same process and structure as the pixel holding capacitor of the pixel portion. can do. Further, when the D / A conversion output switching element is provided on the same substrate, it can be formed by the same process and structure as the pixel electrode switching TFT of the pixel portion.

  As described above, by providing the D / A conversion circuit on the same substrate as the pixel, it is possible to reduce the size of the device, and it is possible to reduce the cost by making the manufacturing process common.

  The D / A conversion method, the D / A conversion circuit, and the manufacturing method thereof according to the present invention described above can be applied to both a reflection type and a transmission type liquid crystal device. In a reflection type liquid crystal device that is not required, the advantage of lower power consumption of the D / A conversion circuit is even greater. The reason is that the power ratio of the D / A conversion circuit in the reflection type is relatively high in the power consumption of the entire apparatus.

  Next, application examples that make use of the effects of the present invention will be described. FIG. 13A is an external view of a portable telephone terminal incorporating the liquid crystal display device according to the present invention. The portable telephone terminal 1000 uses the liquid crystal display panel 1001 to display various information such as an operation menu and communication contents. It is supposed to be displayed.

  FIG. 13B is an external view of a wrist watch incorporating the liquid crystal display device according to the present invention. Information such as time and calendar is displayed on the liquid crystal display panel 1101.

  FIG. 13C is an external view of a portable information terminal incorporating the liquid crystal display device according to the present invention. The portable information terminal 1200 has functions of a personal computer or PDA (Personal Digital Assistant), and various types of information corresponding to these functions are displayed on the liquid crystal display panel 1206.

  Since all of the devices shown in FIGS. 13A to 13C use a reflective liquid crystal display device and adopt the D / A conversion circuit according to the present invention, they are compared with the prior art. As a result, power consumption is further reduced. Therefore, the frequency of charging and battery replacement can be reduced, and the effect of improving the convenience for the user can be obtained.

  In the above description, the liquid crystal device that controls the pixel brightness by the voltage applied to the liquid crystal has been described. The present invention can be applied to electro-optical devices that perform display or the like depending on characteristics. Examples of such an electro-optical device include a plasma display, EL (electroluminescence), and FED (field emission device) in addition to a liquid crystal device, but the application target of the present invention is not limited to these.

  As described above, according to the present invention, it is possible to realize a D / A conversion circuit that can operate at high speed with a simple configuration and consumes low power, and an electro-optical device that realizes gradation display using the D / A conversion circuit. Is possible. In addition, since the configuration is simple, a D / A conversion circuit can be formed over the same substrate as the pixel portion, and the degree of freedom in designing the device is improved. As a result, it is possible to obtain an effect that the electro-optical device capable of gradation display can be reduced in size, cost, resolution, and power consumption.

1 is a circuit diagram showing a configuration of a D / A conversion circuit according to an embodiment of the present invention. FIG. It is a graph which shows the current-voltage characteristic of the nonlinear element which comprises the D / A circuit by the same embodiment. 6 is a timing chart showing the operation timing of the D / A circuit according to the same embodiment. It is a circuit diagram which shows the principal part structure of the liquid crystal display device by one Embodiment of this invention. It is a block diagram which shows the structure of the liquid crystal display device by the same embodiment. FIG. 3 is a circuit diagram showing a configuration of a voltage pulse generation circuit built in the data driver of the liquid crystal display device according to the same embodiment. It is a circuit diagram which shows the principal part structure of the liquid crystal display device by one Embodiment of this invention. It is a circuit diagram which shows the principal part structure of the liquid crystal display device by one Embodiment of this invention. 4 is a timing chart showing the operation timing of the liquid crystal display device according to the embodiment. It is the board | substrate top view (a) and sectional drawing (b) of the step in which the input / output electrode was formed in the D / A converter circuit manufacturing method by one Embodiment of this invention. It is the board | substrate top view (a) and sectional drawing (b) of the step in which the insulating layer was formed in the D / A conversion circuit manufacturing method by the same embodiment. It is the board | substrate top view (a) and sectional drawing (b) of the stage in which the upper electrode was formed in the D / A conversion circuit manufacturing method by the same embodiment. 1 is an external view of various devices to which a liquid crystal display device according to an embodiment of the present invention is applied.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1, 1a, 1b ... Nonlinear element, 2, 2a, 2b ... Capacitor, 3, 3a, 3b ... D / A conversion output switching element, 4, 4a, 4b ... D / A conversion timing switching signal line, 10 ... D / A conversion unit, 11 ... pixel, 12 ... pixel electrode switching element, 13 ... liquid crystal, 14 ... data line, 15 ... scanning line, 20 ... pixel unit, 31 ... liquid crystal panel substrate, 32 ... scan driver, 33 ... data driver, 34 ... Voltage supply source, 35 ... Data modulation circuit, 36 ... Reference clock generation circuit, 41-47 ... Switch, 51 ... Wiring capacitance, 501 ... Substrate, 502 ... Base film, 511, 512 ... Electrode, 521, 522 ... Oxidation Layer (insulating layer), 531 ... upper electrode, 1001, 1101, 1206 ... liquid crystal display panel.

Claims (4)

A first step of forming a pattern of input electrode wiring and output electrode wiring with tantalum (Ta) or aluminum (Al) on a substrate;
A second step of forming an oxide layer having a thickness in the range of 20 nanometers or more and 80 nanometers or less by anodizing the input electrode wiring and the output electrode wiring;
A third step in which the oxide layer is annealed at a temperature in the range of 300 degrees Celsius or more and 500 degrees Celsius or less;
A fourth step of forming an electrode pattern for bridging the oxide layer formed on the input electrode wiring and the oxide layer formed on the output electrode wiring with aluminum (Al) or chromium (Cr);
A method for manufacturing a digital / analog conversion circuit, comprising: A first step of forming a pattern of an input electrode wiring and an output electrode wiring by a polysilicon film on a substrate;
An insulating layer is formed on the input electrode wiring and the output electrode wiring by depositing silicon nitride (SiN _x : H) treated with hydrogen by a chemical vapor deposition apparatus to a thickness in the range of 20 nanometers to 80 nanometers. A second process to form;
A third step of forming an electrode pattern that bridge-connects the insulating layer formed on the input electrode wiring and the insulating layer formed on the output electrode wiring;
A method for manufacturing a digital / analog conversion circuit, comprising:   3. The method of manufacturing a digital / analog conversion circuit according to claim 1, further comprising a capacitor forming process in which a capacitor element is formed on the substrate with the same structure and process as a pixel holding capacitor.   4. A switching means forming process for forming a switching element for turning on / off a digital / analog conversion output on the substrate with the same structure and process as a pixel switching thin film transistor. A method for manufacturing a digital / analog conversion circuit according to one item.

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