JP2007011109A - Display device and driving circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device having a driving circuit that has simple constitution using no shift register in CMOS type structure and can be constituted at a low cost. <P>SOLUTION: The display device 1 has driving circuits 11 and 20 which supply data pulses synchronized with scan pulses to display cells CL, ..., through column electrodes while applying the scan pulses to row electrodes. The driving circuits 11 and 20 each include a converting circuit 21 which generates a control code specifying a row electrode and converts it into a K-bit code and pulse generating circuits 221 to 22N and 23 which are connected to row electrodes where combinations of (r) bits selected from the K-bit code irrelevantly to the order are assigned respectively. The pulse generating circuits 221 to 22N, and 23 apply scan pulses to row electrodes according to decoding results of the combinations of (r) bits. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a driving circuit for driving a display unit in an active matrix display device and related technology.

An active matrix type display device using an active element such as a thin film transistor (TFT) is widely known as a flat display excellent in high-speed response. FIG. 1 is a block diagram schematically showing the configuration of an active matrix display device 100. The display device 100 includes a signal processing unit 101, a display unit 114 in which a plurality of display cells CL,... Are formed in a planar and matrix form on a substrate, and a data driver 110 and an address driver that drive the display unit 114. 102. In the display unit 114, a plurality of scanning electrodes S _1, ..., S _N (N is a positive integer of 2 or more), the scanning electrodes S _1, ..., data electrodes E ₁ that intersects at a distance from each other in S _N, ... , E _M (M is a positive integer greater than or equal to 2), and display cells CL,... Are formed in regions respectively corresponding to the intersections of the scan electrodes and the data electrodes. Scanning electrodes S _1, ..., S _N is connected to the address driver 102, the data electrodes E _1, ..., E _M is connected to the data driver 110. The address driver 102 includes a shift register 103 and an output circuit 104, and the data driver 110 includes a shift register 111, a latch circuit 112, and an output circuit 113.

The signal processing unit 101 processes the video signal VS in synchronization with the system clock CLK to generate a data signal DS, selection pulses φ1 and φ2, and shift clocks CLK1 and CLK2. The shift register 103 of the address driver 102 includes a plurality of stages of registers, and shifts the input selection pulse φ2 to the next stage register according to the rising edge or falling edge of the shift clock CLK2. The outputs of the plurality of stages of registers are supplied to the output circuit 104 in parallel. The output circuit 104 generates a scanning pulse in accordance with the output level from the shift register 103, the scanning pulse scan electrodes S _1, ..., are sequentially applied to S _N. FIG. 2 schematically shows an example of the configuration of the shift register 103. Referring to FIG. 2, the shift register 103 is composed of a plurality of stages of flip-flops DL ₁ ,..., DL _N connected in series, and the first stage flip-flop DL ₁ is the rising edge or falling edge of the shift clock CLK2. The input D ₁ is read in accordance with the edge, and the read input is held and output to the flip-flop DL ₂ at the next stage. The flip-flops DL _{2 to} DL _N after the second stage also read the inputs D _{2 to} D _N-1 from the previous stage according to the pulse edge of the shift clock CLK2, respectively, and these are read as flip-flops DL ₃ to the next stage. Output to DL _N. The inverted outputs of the flip-flops DL _{1 to} DL _N are inverted and then supplied to the output circuit 104 in parallel.

On the other hand, the shift register 111 of the data driver 110 has the same configuration as the shift register 103 and includes a plurality of stages of registers. The shift register 111 shifts the input selection pulse φ1 to the next-stage register in accordance with the rising edge or falling edge of the shift clock CLK1. The outputs of the plurality of stages of registers are supplied to the latch circuit 112 in parallel. The latch circuit 112 reads the data signal DS from the signal processing unit 101 according to the output from the shift register 111 and performs serial-parallel conversion. Data signals after their conversion are supplied in parallel to the output circuit 113, output circuit 113 converts the data signal to the data pulses these data pulses each data electrodes E _1, ..., it is applied to E _M.

  As the shift register 103 used in the address driver 102, a register having a CMOS structure in which a pair of a p-channel TFT and an n-channel TFT is formed on the same substrate is widely used. As the display device 100 has a larger screen, the number of scanning lines (scanning electrodes) increases and the number of stages of the shift register 103 increases. However, the higher the number of stages, the higher the response speed required for the TFT. The circuit configuration of the register 103 is complicated. Examples of TFTs used for the shift register 103 include low-temperature polysilicon TFTs, amorphous silicon TFTs, and organic TFTs (TFTs using organic semiconductors as active layers). Amorphous silicon TFTs include semiconductors such as carrier mobility. From the viewpoint of characteristics, p-channel TFTs are rarely used, and n-channel TFTs are mainly used. In addition, a p-channel TFT is mainly used as the organic TFT, and an n-channel TFT is rarely used. Therefore, when an amorphous silicon TFT or an organic TFT is used, there is a problem that it is difficult to realize a shift register having a CMOS structure that operates stably at high speed.

  Similarly, even in the shift register 111 used in the data driver 110, it is difficult to realize a CMOS type structure using an amorphous silicon TFT or an organic TFT.

  As a technique for solving the above problems, an address driver and a data driver that do not use the shift registers 103 and 111 as described above are disclosed in Patent Document 1 (Japanese Patent Laid-Open No. 2004-264361) or Patent Document 2 (US Patent Application Publication No. 2003). No. 0184535).

  The address driver disclosed in Patent Document 1 includes a counter that generates a selection code that designates a scanning line, and a circuit that generates an inverted code in which the logic level of each bit of the selection code is inverted. The address driver has a plurality of combinational logic circuits each connected to a scan electrode (address electrode). Each combinational logic circuit decodes a part of the selection code and the inverted code. A scan pulse is generated according to the result of decoding. Such a combinational logic circuit can be composed of a logic gate composed of only one of a p-channel TFT and an n-channel TFT.

However, according to Patent Document 1, for example, when a scan pulse is sequentially applied to 480 rows of scan electrodes, a 9-bit selection code and a 9-bit inversion code for specifying the scan electrodes are required, and 18 (= 9 × 2) as many signal lines are required. Each combinational logic circuit must decode the 9-bit code of the selected code and its inverted code. In this way, the number of signal lines is large, and the number of bits required for each combinational logic circuit to decode is large. Therefore, a large circuit scale and a complicated circuit configuration are inevitable, resulting in a decrease in yield and reliability. There is. In addition, since the number of manufacturing steps increases, there is a problem that the manufacturing cost increases.
JP 2004-264361 A US Patent Application Publication No. 2003/0184535 (Corresponding US Patent Application Publication of Patent Document 1)

  In view of the above, an object of the present invention is to provide a drive circuit that can be formed at a low cost with a simple configuration without using a shift register having a CMOS structure, and a display device having the drive circuit.

  The invention according to claim 1 is a plurality of row electrodes, a plurality of column electrodes intersecting with the row electrodes, display cells formed in respective regions respectively corresponding to intersections of the row electrodes and the column electrodes, A display device comprising: a drive circuit that sequentially selects row electrodes and applies scan pulses to the selected row electrodes, and supplies data pulses synchronized with the scan pulses to the display cells via the column electrodes. The drive circuit generates a control code for designating a row electrode to which the scan pulse is to be applied, and the control code is a K-bit code (K is a positive code) having a code length larger than the code length of the control code. An integer) and a combination of r bits selected from the K-bit code in any order (r is a positive integer smaller than the integer K) connected to each row electrode. A pulse generation circuit, wherein the pulse generation circuit decodes each of the r-bit combinations and, depending on the decoding result, the row electrode to which the decoded r-bit combination is assigned. It is characterized by applying a scanning pulse.

  According to a sixth aspect of the present invention, there are provided a plurality of row electrodes, a plurality of column electrodes intersecting with the row electrodes, display cells formed in respective regions respectively corresponding to intersections of the row electrodes and the column electrodes, A display device comprising: a drive circuit that sequentially selects row electrodes and applies scan pulses to the selected row electrodes, and supplies data pulses synchronized with the scan pulses to the display cells via the column electrodes. The drive circuit generates a control code for designating a data signal to be sampled from the input data signal, and the control code is an L bit code (L is a code length larger than the code length of the control code). A combination of a conversion circuit for conversion to a positive integer) and a k-bit combination (k is a positive integer smaller than the integer L) selected regardless of the order from the L-bit code, and responds to the decoding result. Wherein the sampling circuit for sampling the data signal, is characterized in that on the basis of the sampled data signals including an output circuit for generating the data pulse Te.

  The invention according to claim 13 includes a plurality of row electrodes, a plurality of column electrodes intersecting with the row electrodes, and display cells formed in respective regions respectively corresponding to intersections of the row electrodes and the column electrodes. In the display device, a drive circuit that sequentially selects the row electrodes and applies scan pulses to the selected row electrodes, while supplying data pulses synchronized with the scan pulses to the display cells via the column electrodes. Then, a control code designating a row electrode to which the scan pulse is to be applied is generated, and the control code is converted into a K-bit code (K is a positive integer) having a code length larger than the code length of the control code. A pulse connected to a row electrode to which a combination of r bits selected from the conversion circuit and the K bit code in any order (r is a positive integer smaller than the integer K) is assigned. Generating circuit, wherein the pulse generation circuit decodes each of the r bit combinations, and the scan pulse is applied to the row electrode to which the decoded r bit combination is assigned according to the decoding result. Is applied.

  The invention according to claim 14 includes a plurality of row electrodes, a plurality of column electrodes intersecting with the row electrodes, and display cells formed in respective regions respectively corresponding to intersections of the row electrodes and the column electrodes. In the display device, a drive circuit that sequentially selects the row electrodes and applies scan pulses to the selected row electrodes, while supplying data pulses synchronized with the scan pulses to the display cells via the column electrodes. Generating a control code that specifies a data signal to be sampled from the input data signal, and converting the control code into an L-bit code (L is a positive integer) having a code length larger than the code length of the control code And a k-bit combination selected from the L-bit code regardless of the order (k is a positive integer smaller than the integer L), and according to the decoding result, A sampling circuit for sampling the data signal, is characterized in that on the basis of the sampled data signals including an output circuit for generating the data pulse.

  Hereinafter, various embodiments according to the present invention will be described.

<First embodiment>
FIG. 3 is a block diagram schematically showing the configuration of the display device 1 according to the first embodiment of the present invention. The display device 1 includes a signal processing unit 10, a data driver 11, an address driver (gate driver) 20, and a display unit 30. The data driver 11 and the address driver (gate driver) 20 constitute a peripheral drive circuit. The display unit 30 may be formed on a glass substrate or a plastic substrate such as PC (polycarbonate), PMMA (polyethyl methacrylate), or PET (polyethylene terephthalate). The data driver 11 and the address driver 20 are preferably formed on the same substrate together with the display unit 30.

  In the display unit 30, a plurality of display cells CL,... Are formed on the substrate in a matrix and in a planar shape. FIG. 4 shows an example of a display cell CL including an OLED (Organic Light Emitting Diode) 34 such as an organic EL element (organic electroluminescent device). The display cell CL shown in FIG. 4 includes an OLED 34 and an element drive circuit including TFTs 31 and 33 and a capacitor 32 that drive the OLED 34. Each of such display cells CL,... May constitute one pixel, or a plurality of display cells CL,... May constitute one pixel for color display or area gradation. For example, three display cells CL, CL, CL constituting one pixel for color display may have R (red), G (green), and B (blue) emission colors, respectively. A 2-bit area gradation may be realized by a combination of lighting and non-lighting of the three display cells constituting the pixel. In addition, the element drive circuit which drives OLED34 is not limited to what is shown by FIG.

In the display unit 30, N scanning electrodes (row electrodes) S ₁ ,..., S _N extending in the horizontal direction (N is an integer of 2 or more) and M data electrodes ( _N extending in the vertical direction) Column electrodes) E ₁ ,..., E _M (M is an integer of 2 or more), and the scan electrodes S ₁ ,..., S _N are connected to the output circuit 23 of the address driver 20 and the data electrodes E ₁ ,..., E _M are connected to the output circuit 14 of the data driver 11. Scanning electrodes S _1, ..., scanning electrodes S ₁ and S _N, ..., each display cell CL in an area corresponding respectively to the intersections of the S _M are formed.

The signal processing unit 10 generates the data signal DS by processing the video signal VS in synchronization with the system clock CLK, and supplies this to the data driver 11. At the same time, the signal processing unit 10 generates the selection pulse φ1 and the shift clock (reference clock) CLK1 and supplies them to the data driver 11, while generating the reset signal RP and the shift clock (reference clock) CLK2 and supplies them to the address driver. 20 is supplied. The shift clock CLK1 is synchronized with the transfer cycle of the data signal DS, which is an RGB signal, and is used by the data driver 11 to sample the data signal DS. Shift clock CLK2, the scanning electrodes S _1, ..., and a period synchronized with the scanning pulse to be applied sequentially to S _N.

The configuration of the data driver 11 is substantially the same as the configuration shown in FIG. That is, the data driver 11 includes a shift register 12, a latch circuit 13, and an output circuit 14. The shift register 12 includes a plurality of stages of registers, and shifts the input selection pulse φ1 to the next stage register according to the pulse edge (rising edge or falling edge) of the shift clock CLK1. The outputs of the plurality of stages of registers are given to the latch circuit 13 in parallel. The latch circuit 13 reads the data signal DS from the signal processing unit 10 according to the output level from the shift register 12 and performs serial-parallel conversion. Data signals after their conversion are supplied in parallel to the output circuit 14, output circuit 14 converts the data signal to the data pulse, the data electrodes E ₁ These data pulses respectively, ..., is applied to E _M. As a result, data pulse synchronized with the scan pulse, the data electrodes E _1, ..., display cells CL through the E _M, and is supplied to ....

Referring to FIG. 4, the display cell CL includes an OLED 34 and an element driving circuit that drives the OLED 34. Element driving circuit includes two p-channel type TFT31,33 an active element, and a capacitor 32, one of the p-channel type TFT that is, the gate of the selection TFT31 is connected to the Q-th scan electrode S _Q, selected The source of the TFT 31 is connected to the Pth data electrode E _P. The other p-channel TFT, that is, the gate of the driving TFT 33 is connected to the drain of the selection TFT 31 and one end of the capacitor 32, and the source of the driving TFT 33 is the other end of the capacitor 32 and the power supply line W ₁ for supplying the power supply voltage V _DD. The drain of the driving TFT 33 is connected to the anode of the OLED 34. The cathode of the OLED 34 is connected to a common potential. When the scanning pulse to the scanning electrodes S _Q is applied by the address driver 20, selection TFT31 are turned on in response to the scan pulse, to conduct between the source and the drain. At this time, the data driver 11 applies a data pulse synchronized with the scanning pulse to the data electrode E _P , this data pulse is transmitted to the capacitor 32 via the source and drain of the selection TFT 31, and the data voltage is applied to the capacitor 32. Accumulated. Since this data voltage is applied between the gate and source of the drive TFT 33, a drain current corresponding to the gate-source voltage (gate voltage) of the drive TFT 33 flows and is supplied to the OLED 34. As a result, the OLED 34 emits light.

Next, the configuration of the address driver 20 will be described below. Referring to FIG. 3, the address driver 20 includes a conversion circuit 21, combinational logic circuits (LC) 22 ₁ ,..., 22 _N and an output circuit 23. Combinational logic circuits 22 _1, ..., pulse generating circuit of the present invention in the 22 _N and the output circuit 23 may be configured.

The conversion circuit 21 uses the reset signal RP and the shift clock CLK2 from the signal processing unit 10 to sequentially control the scan electrodes S ₁ ,..., S _N to which the scan pulse is to be applied. A positive integer) is generated, and this control code is converted into a K-bit code (K is a positive integer larger than the integer H). For example, 480 scanning electrodes S _1, ..., if the scan pulse is applied to the S _480, the scan electrodes S _1, ..., can take a value of "0" to "511" in order to sequentially specify the S ₄₈₀ A 9-bit control code may be generated.

Each of the combinational logic circuits 22 ₁ ,..., 22 _N decodes only r bits (r is a positive integer) in the K-bit conversion code supplied from the conversion circuit 21 and ignores the other bits. A timing pulse is generated according to the decoding result and supplied to the output circuit 23. The r bit combination is selected from the conversion codes regardless of the bit order. The output circuit 23 generates a scan pulse according to the logical value “1” of the timing pulse.

When selecting without r bits related to the order from the conversion code K bits, the number _K C _r of the combination of the r bit is given by the following equation (1).

  Here, for any positive integer n (n ≠ 0), n! = N × (n−1) ×... × 1 is established.

For example, a combination of 2 bits selected from a 4-bit conversion code “B ₃ B ₂ B ₁ B ₀ ” (where each of B ₀ , B ₁ , B ₂ , and B ₃ represents a bit) regardless of the order. Are “B ₁ B ₀ ”, “B ₂ B ₀ ”, “B ₃ B ₀ ”, “B ₂ B ₁ ”, “B ₃ B ₁ ”, “B ₃ B ₂ ”, and six combinations There are a number of.

The code length of the combination code having a code length and r-bit conversion code, the number _K C _r is the scanning electrode S ₁ of the combination, ..., it may be determined to be equal to or greater than the number of S _N. For example, when it is desired to sequentially specify ₄₈₀ scan electrodes S ₁ ,..., S ₄₈₀ , ₁₂ C ₄ = 495, so that the conversion circuit 21 generates a 12-bit conversion code and sets a 4-bit combination code. That's fine.

These r bit combinations are assigned one-to-one to the scan electrodes S ₁ ,..., S _N. Combinational logic circuits 22 ₁ through 22 _N decodes the combination of r bits, depending on the resulting code value, the timing to the combination of the r bits to apply a scan pulse to the scan electrodes S _Q assigned The pulse is supplied to the output circuit 23.

Table 1 below shows the row numbers of the _eight scan electrodes S ₁ ,..., S ₈ , and the 3-bit control code “Q ₂ Q ₁ Q ₀ ” (Q ₀ , Q ₁ , Q ₂ each represents a bit. And a 5-bit conversion code “B ₄ B ₃ B ₂ B ₁ B ₀ ” (B ₀ , B ₁ , B ₂ , B ₃ , and B ₄ each represent a bit). Indicates. In Table 1, “0” or “1” indicates the logical value of each bit.

In Table 1, a combination of 2 bits in the conversion code is assigned to each of the scan electrodes S ₁ ,..., S ₈ . That is, the scanning electrode S ₁ is "B ₁ B _0", the scanning electrode S ₂ is "B ₂ B _0", the scanning electrodes S ₃ "B ₂ B _1" is, the scanning electrode S ₄ is "B ₃ B _0" is, the scanning electrodes S ₅ "B ₃ B _1" is, to scan electrodes S ₆ is "B ₃ B _2", to the scanning electrodes S ₇ is "B ₄ B _0", “B ₄ B ₁ ” is assigned to each of the scan electrodes S ₈ .

An example of the configuration of the conversion circuit 21 is shown in FIG. The conversion circuit 21 counts the pulses of the shift clock CLK2 and generates a control code that is an H-bit binary code, and an edge that detects the pulse edge of the shift clock CLK2 and generates its detection signal DP A detection circuit 41 and a code converter 43 that converts the output of the counter circuit 42 to generate a K-bit conversion code are included. Combinational logic circuits 22 _1, ..., in each of transform coding of 22 _N, only the combination of r bits assigned thereto a decodes the pulse signal OT ₁ in response to the result of decoding, ..., output OT _N This is supplied to the circuit 23.

The operation of the conversion circuit 21 when a scan pulse is applied to the _eight scan electrodes S ₁ ,..., S ₈ will be described below with reference to the timing chart of FIG. Referring to FIG. 6, the counter circuit 42 resets the value of the control code to the initial value in accordance with the reset signal RP having a signal level corresponding to the logical value “1”. The counter circuit 42 is triggered by a rising edge of the shift clock CLK2, and generates a control code “Q ₂ Q ₁ Q ₀ ” that is a 3-bit binary code. The signal level of each of the bits Q ₀ , Q ₁ , and Q ₂ is high for the logical value “1” and low for the logical value “0”. On the other hand, the edge detection circuit 41 generates a detection signal DP composed of low level detection pulses P _L ,..., P _L in response to the rising edge of the shift clock CLK2.

The code converter 43 generates the conversion code “B ₄ B ₃ B ₂ B ₁ B ₀ ” according to Table 1 according to the binary code from the counter circuit 42. The signal level of each of the bits B ₀ , B ₁ , B ₂ , B ₃ , B ₄ is high for the logical value “1” and low for the logical value “0”. Further, as shown in FIG. 6, the code converter 43 provides a low level output according to the low level detection pulses P _L ,..., P _L. In other words, the output level of the code converter 43, the detection pulse P _L, ..., in a period for receiving a supply of P _L, bits _{B 0, B 1, B 2} , B 3, relating to the logic value of B ₄ It is fixed at a low level.

Each of the combinational logic circuits 22 ₁ ,..., 22 _N decodes only a predetermined 2-bit combination “Q _p Q _q ” (p, q is an integer of 0 to 4) in the conversion code, If the code value is a predetermined “11”, a high level pulse signal is output. If the code value is “01”, “10” or “00” other than “11”, a low level pulse signal is output. Output a signal. The output circuit 23 sequentially generates the scan pulses SP ₁ ,..., SP ₈ in response to the high level pulse signal.

As shown in FIG. 6, when the value of the conversion code “B ₄ B ₃ B ₂ B ₁ B ₀ ” is switched, the signal levels of the bits B ₀ , B ₁ , B ₂ , B ₃ , and B ₄ are all low. The invalid periods Tm,..., Tm are fixed. Thereby, the combinational logic circuits 22 ₁ ,..., 22 _N can reliably detect the sign value of the 2-bit combination “Q _p Q _q ”. For example, even if the distortion of the signal waveform occurs when the value of the combination code “Q _p Q _q ” is switched from “01” to “11” or “11” to “01”, the erroneous detection of the code value is ensured. Can be avoided.

In this embodiment, the code converter 43 gives a low level output in accordance with the low level detection pulses P _L ,..., P _L from the edge detection circuit 41, but the present invention is not limited to this. is not. For example, the code converter 43 may provide a low level output in response to a high level detection pulse from the edge detection circuit 41.

By the conversion circuit 21 as described above, the combinational logic circuits 22 ₁ ,..., 22 _N are composed of logic gates composed of only one of p-channel TFTs or n-channel TFTs, or logic gates composed of only diodes. It becomes possible to do. 7, FIG. 8, FIG. 9, and FIG. 10 schematically show examples of the combinational logic circuit 22 _q (q is an integer of 1 to N).

Referring to FIG. 7, the combinational logic circuit 22 _q includes a logic gate (AND gate) composed of r n-channel transistors N ₁ ,..., N _r connected in series, and the n-channel transistors N ₁ ,. , N _r control terminals (gates) are respectively applied with 1-bit signals constituting r-bit combination codes. _One controlled terminal of the transistor N ₁ is pulled up to the power supply potential Vcc, and one controlled terminal of the transistor N _r is grounded via the resistor 24 and is connected to one controlled terminal of the transistor N _r. A pulse signal OT _q is output. Only when a high level signal is applied to all the control terminals of the transistors N ₁ ,..., N _r , the high level output signal OT _q is given, and among the control terminals of the transistors N _{1 ,.} When a low level signal is applied to at least one, a low level output signal OT _q is provided.

Referring to FIG. 8, the combinational logic circuit 22 _q includes a logic gate (AND gate) composed of diodes DD ₁ ,..., DD _r whose anodes are commonly connected to the power supply potential Vcc via the resistor 28 and are grounded. It includes these diodes DD _1, ..., to the cathode of each DD _r, respectively, the signal of 1 bit constituting the combination code of r bits is applied. To one end of the resistor 28 is connected the power supply potential Vcc, the pulse signal OT _q is output from the other end. When a high level signal is applied to all the cathodes, a reverse bias is applied to all the diodes DD ₁ ,..., DD _r, and the voltage drop across the resistor 28 becomes substantially zero. OT _q is given. On the other hand, when a low level signal is applied to any one of the cathodes, a low level output signal OT _q is given.

The combinational logic circuit 22 _q shown in FIGS. 7 and 8 corresponds to the case where positive logic is applied in which a high level corresponds to the logical value “1” as a signal level and a low level corresponds to the logical value “0”. It is what is used. The timing chart of FIG. 6 and Table 1 above are in accordance with positive logic. Instead of this positive logic, a negative logic in which a high level is associated with a logical value “0” and a low level is associated with a logical value “1” may be applied. Examples of the combinational logic circuit 22 _q that can be used in such a case are shown in FIGS.

The combinational logic circuit 22 _q shown in FIG. 9 includes a logic gate composed of _r p-channel transistors P ₁ ,..., Pr that are connected in series, and controls the p-channel transistors P _{1 ,.} A 1-bit signal constituting an r-bit combination code is applied to each terminal (gate). Transistor one controlled terminal of the N _r is grounded, the transistor one of the control terminal of the P ₁ is connected to a power supply potential Vcc via a resistor 25, one of the pulse signals from the control terminal of the transistor P ₁ OT _q is output. Only when a low level signal is applied to all the control terminals of the transistors P ₁ ,..., _Pr , the low level output signal OT _q is provided, and among the control terminals of the transistors N _{1 ,.} When a high level signal is applied to at least one, a high level output signal OT _q is provided.

The combinational logic circuit 22 _q shown in FIG. 10 includes a logic gate (OR gate) composed of diodes DD ₁ ,..., DD _r whose cathodes are commonly grounded via a resistor 29, and these diodes DD _1. ,..., DD _r are respectively applied with 1-bit signals constituting r-bit combination codes. One end of the resistor 29 is grounded, and a pulse signal OT _q is output from the other end. Diode DD _1, ..., if a low level signal is applied to all the anodes of DD _r, they diodes DD _1, ..., a reverse bias is applied to all the DD _r, given the output signal OT _q low levels . On the other hand, when a high level signal is applied to at least one anode, a current flows through the resistor 29 and a high level output signal OT _q is provided.

Incidentally, the n-channel transistor N _1, ..., using the amorphous silicon TFT is the N _r, the p-channel transistor P _1, ..., the P _r can be used organic TFT.

As described above, according to the address driver 20 in the first embodiment, the code length of the transform coding of K bits supplied by the conversion circuit 21 is short, also the combinational logic circuits 22 _1, ..., 22 _N is transform coding since it is sufficient to decode only predetermined combination of r bits in the combinational logic circuit 22 _1, ..., be reduced as compared with the prior art the number of signal lines forming between 22 _N and the conversion circuit 21 Is possible. In addition, since the combinational logic circuits 22 ₁ ,..., 22 _N can be configured with a logic gate composed of only one of an n-channel TFT and a p-channel TFT, or a logic gate composed of only a diode. A relatively small circuit configuration is possible.

  Therefore, by using such an address driver 20, it is possible to provide a peripheral drive circuit with high yield and high reliability without using a shift register having a CMOS structure.

<Second embodiment>
FIG. 11 is a block diagram schematically showing the configuration of a display device 1A according to the second embodiment of the present invention. The blocks denoted by the same reference numerals in FIG. 11 and FIG. 3 are assumed to have substantially the same configuration and function, and detailed description thereof is omitted. A display device 1A shown in FIG. 11 is different from the display device 1 shown in FIG.

The data driver 50 of the second embodiment, the conversion circuit 51, a plurality of combinational logic circuits 52 _1, ..., and 52 _M, the first sample-and-hold circuit group 53 _1, ..., and 53 _M, the second sample-and-hold A circuit group 54 ₁ ,..., 54 _M and an output circuit 55 are provided. These combinational logic circuits 52 _1, ..., and 52 _M, the sample and hold circuit 53 ₁ of the first group and the second group, ..., 53 _M, 54 _1, ..., a sampling circuit of the present invention may be composed of a 54 _M .

Conversion circuit 51 uses a reset signal RPx and shift clock (reference clock) CLK1 from the signal processing unit 10, a control code of H ₂ bits to specify the timing for sampling the transferred data signal DS from the signal processing unit 10 (H ₂ is a positive integer) is generated, and this control code is converted into an L-bit code (L is a positive integer larger than the integer H ₂ ). The configuration of the conversion circuit 51 is substantially the same as the configuration of the conversion circuit 21 of the address driver 20 of the first embodiment.

Each of the combinational logic circuits 52 ₁ ,..., 52 _M decodes only k bits (k is a positive integer) in the L-bit conversion code supplied from the conversion circuit 51 and ignores the other bits. Combinational logic circuits 52 _1, ..., 52 _M generates a timing pulse in accordance with the decoded result, the sample hold circuit 53 ₁ These timing pulses respectively, ..., giving a 53 _M. The configurations of the combinational logic circuits 52 ₁ ,..., 52 _M are substantially the same as the configurations of the combinational logic circuits 22 ₁ ,..., 22 _N of the address driver 20 of the first embodiment. Therefore, the combinational logic circuits 52 ₁ ,..., 52 _M need only decode the code value of the k-bit combination selected from the L-bit conversion code regardless of the bit order. Such combinational logic circuits 52 ₁ ,..., 52 _M can be composed of a logic gate composed of only one of a p-channel TFT and an n-channel TFT, or a logic gate composed of only a diode. is there.

For example, the signal processing unit 10 transfers a series of 8-bit RGB signals to the data driver 50 as the data signal DS. Sample and hold circuit 53 ₁ of the first group, ..., 53 _M, respectively, the combinational logic circuits 52 _1, ..., in accordance with the pulse edge of a given timing pulse from 52 _M (rising edge or falling edge), the data signal DS is sampled dot-sequentially and the sampled signal voltage is held until the next timing pulse is applied. Sample and hold circuit 53 ₁ of the first group, ..., 53 _M, respectively, the sample and hold circuit 54 ₁ of the second group, ..., and supplies the sampled signal voltage to 54 _M. The second group of sample and hold circuits 54 ₁ ,..., 54 _M sample the signals from the sample and hold circuits 53 ₁ ,..., 53 _M in response to the pulse edge of the shift clock CLK2, and until the next pulse is given. The sampled signal voltage is supplied to the output circuit 55 while being held. The output circuit 55 includes a sample and hold circuit 54 ₁ of the second group, ..., the data pulse corresponding to the signal voltage from 54 _M, respectively, the data electrodes E _1, ..., it is applied to E _M.

According to the data driver 50 of the second embodiment such as the above, the code length of transform coding of L bits supplied by the conversion circuit 51 is small, also, the combinational logic circuits 52 _1, ..., 52 _M is the transform coding Since it is sufficient to decode only a predetermined combination of k bits, it is possible to reduce the number of signal lines formed between the combinational logic circuits 52 ₁ ,..., 52 _N and the conversion circuit 51 as compared with the prior art. Is possible. In addition, the combinational logic circuits 52 ₁ ,..., 52 _N can be configured with a logic gate consisting of only one of an n-channel TFT or a p-channel TFT, or a logic gate consisting of only a diode. A relatively small circuit configuration is possible.

  Therefore, by using such a data driver 50, it is possible to provide a peripheral drive circuit with high yield and high reliability without using a shift register having a CMOS structure.

  Next, a modification of the data driver 50 of the second embodiment is shown in FIG. In this modification, the signal processing unit 10 transfers the R signal (red signal), G signal (green signal), and B signal (blue signal) to the data driver 50A in units of pixels. That is, the R signal, the G signal, and the B signal are supplied to the data driver 50A in parallel at substantially the same timing.

The data driver 50A includes a converter circuit 51, the combinational logic circuits 52 _1, ..., and 52 _M. Further, as the sample-and-hold circuits in the first group, the sample and hold circuits 53R ₁ for sampling the R signal, ..., and 53R _M, the sample and hold circuit 53G ₁ for sampling a G signal, ..., sampling and 53G _M, B signals sample and hold circuits 53B ₁ to, ..., is provided with a 53B _M, as the sample-and-hold circuits of the second group, the sample and hold circuits 53R ₁ for R signal, ..., and 53R _M, the sample-hold for G signal circuit 53G _1, ..., and 53G _M, the sample and hold circuit 53B ₁ for B signals, ..., are provided and 53B _M.

The output circuit 55 outputs data pulses corresponding to the signal voltages from the second group of sample hold circuits 54R ₁ , 54G ₁ , 54B ₁ ,..., 54R _M , 54G _M , 54B _M to the data electrodes E ₁ ,. , E _3M .

It is a block diagram which shows schematically the structure of the conventional active matrix type display apparatus. It is a figure which shows roughly an example of a structure of the conventional shift register. 1 is a block diagram schematically showing a configuration of a display device that is a first embodiment according to the present invention; FIG. It is the schematic which shows an example of the display cell CL. It is a figure which shows roughly an example of a structure of a conversion circuit. 6 is a timing chart for explaining the operation of the conversion circuit. It is a figure which shows roughly the example of the combinational logic circuit which has a logic gate which consists only of n channel type TFT. It is a figure which shows roughly the example of the equivalent circuit of the combinational logic circuit which has a logic gate which consists only of a diode. It is a figure which shows roughly the example of the equivalent circuit of the combinational logic circuit which has a logic gate which consists only of p channel type TFTs. It is a figure which shows roughly the other example of the equivalent circuit of the combinational logic circuit which has a logic gate which consists only of a diode. It is a block diagram which shows roughly the structure of the display apparatus which is 2nd Example which concerns on this invention. It is a figure which shows roughly the structure of the data driver of the modification of 2nd Example.

Explanation of symbols

1, 1A Display device 10 Signal processing unit 11, 50 Data driver 12 Shift register 13 Latch circuit 14 Output circuit 20 Address driver (gate driver)
21, 51 conversion circuit 22 _{1 to} 22 _N combinational logic circuit (LC)
52 _{1 to} 52 _M combinational logic (LC)
41 Edge detection circuit 42 Counter circuit 43 Code converter

Claims (14)

A plurality of row electrodes, a plurality of column electrodes intersecting the row electrodes, display cells formed in respective regions respectively corresponding to the intersections of the row electrodes and the column electrodes, and the row electrodes are sequentially selected and selected. A driving circuit that applies a scan pulse to the row electrode, and supplies a data pulse synchronized with the scan pulse to the display cell via the column electrode,
The drive circuit is
A conversion circuit that generates a control code designating a row electrode to which the scanning pulse is to be applied, and converts the control code into a K-bit code (K is a positive integer) having a code length larger than the code length of the control code When,
A pulse generation circuit connected to each row electrode to which a combination of r bits selected from the K bit code in any order (r is a positive integer smaller than the integer K) is assigned,
The pulse generation circuit decodes each of the r bit combinations, and applies the scan pulse to the row electrode to which the decoded r bit combination is assigned according to the decoding result. Display device.   2. The display device according to claim 1, wherein the pulse generation circuit includes a combinational logic circuit that provides a code value of the combination of r bits as the decoding result.   3. The display device according to claim 2, wherein the combinational logic circuit includes a logic gate including only one of a p-channel thin film transistor and an n-channel thin film transistor.   3. The display device according to claim 2, wherein the combinational logic circuit includes a logic gate including only a diode. The display device according to any one of claims 1 to 4,
The conversion circuit includes:
A counter for generating the control code by counting pulses of a reference clock having a period synchronized with the scan pulse;
An edge detection circuit that detects each pulse edge of the reference clock and generates a detection signal;
A code converter that converts the control code into the K-bit code using the detection signal;
A display device comprising: The display device according to claim 5,
The edge detection circuit generates a low-level or high-level detection pulse corresponding to each pulse edge of the reference clock as a pulse of the detection signal,
The code converter provides a low level or high level output according to the detection pulse. A plurality of row electrodes, a plurality of column electrodes intersecting the row electrodes, display cells formed in respective regions respectively corresponding to the intersections of the row electrodes and the column electrodes, and the row electrodes are sequentially selected and selected. A driving circuit that applies a scan pulse to the row electrode, and supplies a data pulse synchronized with the scan pulse to the display cell via the column electrode,
The drive circuit is
Conversion that generates a control code that specifies a data signal to be sampled from an input data signal, and converts the control code into an L-bit code (L is a positive integer) having a code length larger than the code length of the control code Circuit,
A sampling circuit that decodes a combination of k bits selected from the L-bit code regardless of the order (k is a positive integer smaller than the integer L), and samples the data signal according to the decoding result;
An output circuit for generating the data pulse based on the sampled data signal;
A display device comprising:   8. The display device according to claim 7, wherein the sampling circuit includes a combinational logic circuit that provides a code value of the k-bit combination as the decoding result.   9. The display device according to claim 8, wherein the combinational logic circuit includes a logic gate including only one of a p-channel thin film transistor and an n-channel thin film transistor.   The display device according to claim 8, wherein the combinational logic circuit includes a logic gate including only a diode. A display device according to any one of claims 7 to 10,
The conversion circuit includes:
A counter for generating the control code by counting pulses of a reference clock synchronized with a transfer cycle of the data signal;
An edge detection circuit that detects each pulse edge of the reference clock and generates a detection signal;
A code converter for converting the control code into the L-bit code using the detection signal;
A display device comprising: The display device according to claim 11,
The edge detection circuit generates a low-level or high-level detection pulse corresponding to each pulse edge of the reference clock as a pulse of the detection signal,
The code converter provides a low level or high level output according to the detection pulse. In a display device having a plurality of row electrodes, a plurality of column electrodes intersecting with the row electrodes, and display cells formed in respective regions respectively corresponding to the intersections of the row electrodes and the column electrodes, the row electrodes are A driving circuit for sequentially applying a scan pulse to the selected row electrode and supplying a data pulse synchronized with the scan pulse to the display cell via the column electrode;
A conversion circuit that generates a control code designating a row electrode to which the scanning pulse is to be applied, and converts the control code into a K-bit code (K is a positive integer) having a code length larger than the code length of the control code When,
A pulse generation circuit connected to each row electrode to which a combination of r bits selected from the K bit code in any order (r is a positive integer smaller than the integer K) is assigned,
The pulse generation circuit decodes each of the r bit combinations, and applies the scan pulse to the row electrode to which the decoded r bit combination is assigned according to the decoding result. Drive circuit. In a display device including a plurality of row electrodes, a plurality of column electrodes intersecting with the row electrodes, and display cells formed in respective regions respectively corresponding to the intersections of the row electrodes and the column electrodes, the row electrodes are A driving circuit for sequentially applying a scan pulse to the selected row electrode and supplying a data pulse synchronized with the scan pulse to the display cell via the column electrode;
Conversion that generates a control code that specifies a data signal to be sampled from an input data signal, and converts the control code into an L-bit code (L is a positive integer) having a code length larger than the code length of the control code Circuit,
A sampling circuit that decodes a combination of k bits selected from the L-bit code regardless of the order (k is a positive integer smaller than the integer L), and samples the data signal according to the decoding result;
An output circuit for generating the data pulse based on the sampled data signal;
A drive circuit comprising:

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