JP2007006136A - Interface circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an interface circuit capable of reducing an influence of the variance in supply voltage upon an output signal. <P>SOLUTION: An interface circuit 100 includes a transmission circuit 1 for outputting a signal by performing push-pull control of a constant current on the basis of a prescribed signal, a transmission line 2 for transmitting a signal, and a reception circuit 3. The reception circuit 3 includes a first constant current circuit 9, a first transistor 10 which has an impedance matched with the transmission line 2 and has a gate voltage kept constant, a first resistance 11 connected between the first transistor 10 and the ground potential, a second constant current circuit 12 which is connected to a power source and outputs a current being a 1/m of the current of the first constant current 9, a second resistance 14 which is connected between the second constant current circuit 12 and a ground potential and has m-fold resistance value of the first resistance 11, and a comparator 15 which compares a potential of the first resistance 11 and a potential 14 of the second resistance to output a signal. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an interface circuit of a transmission / reception system that transmits data and the like from a transmission circuit to a reception circuit via a transmission line.

  Conventionally, as a foldable mobile phone that folds the operation unit and display unit, an interface that transmits image data signals, clock signals, etc. to the display unit side via a flexible wiring (transmission line) from an LSI mounted on the operation unit side Some have a circuit. For example, the interface circuit senses an input signal ΔV and transmits a current proportional to the transmission signal to the transmission line, a gate-grounded transistor impedance-matched to the transmission line, and the input via the transmission line. And a receiving circuit having a resistor for converting a change in current of the signal into a voltage (see, for example, Non-Patent Document 1).

  In the above prior art, as described above, the drain current is changed according to the voltage (input signal) applied to the transistor of the transmission circuit, but the current change at the rise and fall of the voltage (input signal) is large. There was a problem that noise occurred in the ground.

Furthermore, in the above prior art, the voltage output generated at the resistance end of the receiving circuit varies depending on the amplitude of the signal input from the transmission line. When the comparator compares the voltage output with a reference voltage based on the power supply voltage and outputs a signal to a display device or the like, if the reference voltage fluctuates due to power supply noise, the comparator output signal varies. That is, there has been a problem that a signal to be output to a display device or the like is easily affected by power supply voltage fluctuations.
Behzad Razavi, “Design of Analog CMOS Integrated Circuits”, McGraw-Hill Education, October 2003, p. 77-78

  The present invention solves the above-described problems, and an object thereof is to provide an interface circuit capable of reducing the influence of power supply voltage fluctuations on an output signal.

An interface circuit according to an embodiment of one aspect of the present invention includes:
A transmission circuit that outputs a current signal by push-pull control of a constant current based on a predetermined signal input;
A transmission line for transmitting the signal output from the transmission circuit;
A first constant current circuit connected to a power source; a first transistor connected to the first constant current circuit and the transmission line; impedance matched with the transmission line; and a gate voltage kept constant; , A first resistor connected between the first transistor and a ground potential, and a second resistor connected to the power source and outputting a current of 1 / m magnitude of the first constant current circuit. A constant current circuit; a second resistor connected between the second constant current circuit and the ground potential; the second resistor having a resistance value m times the first resistor; and the potential of the first resistor; A receiving circuit having a comparator that compares the potential of the second resistor and outputs a predetermined signal.

In another aspect, a transmission circuit that outputs a current signal by push-pull controlling a constant current based on a predetermined signal input;
A transmission line for transmitting the signal output from the transmission circuit;
A first constant current circuit connected to a power source; and a first resistor connected between the first constant current circuit and a ground potential and connected to the transmission line and impedance-matched to the transmission line And a second constant current circuit that is connected to a power source and outputs a current of 1 / m magnitude of the first constant current circuit, and between the second constant current circuit and the ground potential A receiving circuit having a second resistor connected and having a resistance value that is m times the first resistor, and a comparator that compares the potentials of the two resistors and outputs a predetermined signal; It is characterized by that.

  According to the interface circuit of the present invention, it is possible to reduce the influence of power supply voltage fluctuations on the output signal.

  In the interface circuit according to the embodiment of the present invention, for example, as a foldable mobile phone that folds the operation unit and the display unit, an image data signal is transmitted from an LSI mounted on the operation unit side via a flexible wiring (transmission line). A description will be given of an interface circuit applied to a device that transmits a clock signal or the like to the display unit.

  Note that the interface circuit according to one embodiment of the present invention can be applied to an electronic device such as a personal computer having a configuration in which a signal is transmitted through a transmission line and a signal is output based on a predetermined signal input. Of course.

  Embodiments according to the present invention will be described below with reference to the drawings.

  FIG. 1 is a diagram illustrating a configuration of a main part of an interface circuit according to a first embodiment which is an aspect of the present invention.

  As shown in FIG. 1, the interface circuit 100 includes a constant current (based on a predetermined signal input such as an image data signal or a clock signal from an LSI or the like mounted on the operation unit side of a foldable mobile phone, for example. A transmission circuit 1 that outputs a signal by push-pull control of a reference current), a transmission line 2 for transmitting a signal output from the transmission circuit 1, and a signal that is impedance-matched to the transmission line 2 and transmitted And a receiving circuit 3 that compares the value (potential) obtained by voltage conversion with a reference voltage value (reference potential) set so as to be positioned at the center of the amplitude of the signal and outputs a signal.

  The transmission circuit 1 includes a constant current circuit 5a, a push-pull circuit 6, and a constant current circuit 5b connected in series between the voltage source VDD and the ground potential. The constant current generated by the constant current circuits 5a and 5b is push-pull controlled by the push-pull circuit 6 based on a signal input from the input terminal 4 to generate a current signal. That is, the transmission circuit 1 outputs a signal from the output terminal 7 to the transmission line 2 based on a predetermined signal input such as an image data signal or a clock signal.

  The transmission line 2 is connected between the output terminal 7 of the transmission circuit 1 and the input terminal 4 of the reception circuit 3. The transmission line 2 is used for, for example, a flexible wiring (for example, impedance Rs = 50Ω) that is folded in two in a mobile phone, and transmits an image data signal, a clock signal, and the like.

  The receiving circuit 3 includes a first constant current circuit 9 connected to the power supply VDD, and a first transistor 10 whose source is connected to the connection point of the first constant current circuit 9 and the transmission line 2 and whose gate is grounded, A first resistor 11 connected between the drain of the first transistor 10 and the ground potential, a second constant current circuit 12 connected to the power supply VDD, and a source connected to the second constant current circuit 12 Is connected to the gate of the second transistor 13, the second resistor 14 is connected between the drain of the second transistor 13 and the ground potential, the resistance terminal of the first resistor 11 and the second resistor A comparator 15 having an input connected to the resistance end of the resistor 14, and inverter circuits 16, 17 connected to the comparator 15 and the output for shaping the output and outputting a signal from the output terminal 18. You .

  The first constant current circuit 9 forms a mirror circuit by sharing the power supply VDD with the second constant current circuit 12, and the second constant current circuit 12 is the first constant current circuit 9 of the first constant current circuit 9. A current Iz / m having a magnitude proportional to 1 / m (m ≧ 1) of the output current Iz of the constant current circuit 9 is output. Further, the current Iz is adjusted to a current value that becomes an operating point of the first transistor 10 to be matched with the input impedance viewed from the transmission line 2 side of the first transistor 10.

  The first transistor 10 (here, PMOS type) is configured so that the gate voltage is kept constant and a predetermined current flows as a result of grounding the gate. In addition, the first transistor 10 is impedance matched with the transmission line 2 (impedance Rs = 50Ω) as described above, and suppresses the generation of a reflected wave on the transmission line 2.

  Here, the input impedance Zin of the receiving circuit 3 viewed from the transmission line 2 side is obtained as Zin = (R + ro) / (1+ (gm + gmb) * ro) (R: resistance value of the first resistor 11; ro: output resistance of the first transistor 10, gm: mutual conductance of the first transistor 10, and gmb: mutual conductance due to the substrate bias effect of the first transistor 10.

  In this embodiment, assuming that the relationship of ro >> R, (gm + gmb) * ro >> 1, and gm >> gmb is established, the input impedance Zin can be approximated as Zin≈1 / gm. Here, in order for the first transistor 10 to perform impedance matching, the relationship of input impedance Zin = impedance Rs (= 50Ω) of the transmission line 2 needs to be established. Therefore, in this embodiment, the mutual conductance gm is adjusted to be 1 / gm = 50Ω.

  The first resistor 11 has a resistance value R (here, R = 300Ω, for example), and converts the current applied through the first transistor 10 into a voltage across the first transistor 11. The resistance end of the first resistor 11 and the input of the converter 15 are connected, and the voltage generated at the resistance end is input to the comparator 15.

  The second transistor 13 (PMOS type here) has a channel length that is 1 / m of that of the first transistor 10, and the other configuration is the same. Further, since the gate electrode of the second transistor 13 is commonly connected to the first transistor and grounded, the gate voltage is kept constant. Thus, the second transistor 13 has a resistance value that is m times that of the first transistor 10. The second constant current circuit 12 allows a constant current Iz / m to flow through the second resistor 14. Therefore, even if the second transistor 13 is not provided, a desired reference voltage Vref (= IzR) is generated at least at the resistance end of the second resistor 14.

  The second resistor 14 has a resistance value mR that is m times that of the first resistor 11, and the constant current Iz / m generated by the second constant current circuit 12 that is applied via the second transistor 13. Is converted into a voltage (reference voltage Vref = IzR). By adjusting (increasing) the value of m, power consumption in the second resistor 14 can be reduced.

  As will be described later, the comparator 15 compares the potential 11 of the first resistor with the potential of the second resistor 14 and outputs a predetermined signal.

  Next, the operation of the interface circuit 100 having the above configuration will be described.

  First, based on a predetermined signal input such as an image data signal or a clock signal, a constant current Ic (signal current) is push-pull controlled from the transmission circuit 1 and output as a transmission signal to the transmission line 2. Hereinafter, the case where the predetermined signal input to the input terminal 4 is “1” and the case where it is “0” will be described separately.

  When the predetermined signal input is “1”, that is, when the input is High, the constant current Ic generated by the constant current circuit 5a is transmitted through the transmission line 2 and applied to the receiving circuit 3 from the input terminal 8, and the transmitting circuit 1 is pushed. It becomes a state. At this time, the constant current Ic generated by the constant current circuit 5b flows through the other path in the transmission circuit 1 to the ground.

Thereby, in the receiving circuit 3, the input constant current Ic and the constant current Iz generated by the first constant current circuit 9 are voltage V _push (= Iz × R + Ic × R) by the first resistor 11. Is converted to

The comparator 15 compares the voltage V _push converted by the first resistor 11 with the voltage Vref (reference voltage) converted by the second resistor 14, and the voltage V _push is higher than the voltage Vref. , Outputs a high-level signal. This signal is shaped by the inverter circuits 16 and 17 and output as an output signal of the interface circuit 100 via the output terminal 18.

  On the other hand, when the predetermined signal input is “0”, that is, when the input is Low, the constant current circuit 5 b becomes conductive with the transmission line 2, whereby the current on the receiving circuit 3 side is pulled and the receiving circuit 3 The constant current Ic is transmitted through the transmission line 2 and flows into the output terminal 7 of the transmission circuit 1, so that the transmission circuit 1 is pulled. At this time, the constant current Ic generated by the constant current circuit 5a flows to the ground via another path in the transmission circuit 1.

As a result, in the receiving circuit 3, the difference current between the constant current Ic flowing out from the input terminal 8 and the constant current Iz generated by the first constant current circuit 9 is converted to a voltage V _pull (= Iz) by the first resistor 11. × R−Ic × R).

The comparator 15 compares the voltage V _pull with the voltage Vref (reference voltage), and outputs a low-level signal because the voltage V _pull is lower than the voltage Vref. This signal is shaped by the inverter circuits 16 and 17 and output as an output signal of the interface circuit 100 via the output terminal 18.

  The waveform of the input voltage of the comparator 15 generated as described above is shown in FIG.

As shown in FIG. 2, the amplitude of the voltages (V _push , V _pull ) input to the converter 15 changes based on the values of the constant currents Ic, Iz (V _push = Iz × R + Ic × R, V _pull = Iz × R−Ic × R) is such that the reference voltage Vref (= IzR) is located at the center of this amplitude. Therefore, since the comparator 15 can compare these voltage values clearly, it can output a signal more accurately.

Thereby, for example, even when the power supply voltage fluctuates and the constant current Ic fluctuates, the relationship in which the reference voltage Vref is located at the center of the amplitude of the voltages (V _push , V _pull ) is maintained, so the comparator 15 It is possible to reduce the influence of power supply voltage fluctuations on the output signal.

Further, for example, even when the resistance value R of the first resistor 11 and the resistance value mR of the second resistor 14 of the receiving circuit 3 fluctuate due to manufacturing variations, temperature changes, and the like, The center voltage of the voltage generated at the end and the reference voltage (Vref) fluctuate similarly, and the relationship in which the reference voltage Vref is located at the center of the amplitude of the voltage (V _push , V _pull ) is maintained. Therefore, it is possible to reduce the influence of manufacturing variations and temperature changes on the output signal of the comparator 15.

  Further, the current value of the reference current (constant current Ic) of the transmission circuit 1 is reduced to, for example, 500 μA or less by adjusting the resistance value R of the first resistor 11 within a range in which the comparator 15 appropriately performs the comparison operation. It is possible to set. As a result, the voltage amplitude of the transmission signal and the current consumption of the transmission circuit can be suppressed. In addition, the interface circuit 1 can be reduced in EMI (Electro Magnetic Interference) and power consumption.

  As described above, according to the interface circuit according to the present embodiment, based on a predetermined signal input, a transmission circuit that outputs a signal by performing push-pull control of a constant current, and a signal output from the transmission circuit Compare the transmission line for transmission with the impedance of this transmission line and compare the voltage value of the transmitted signal with the reference voltage value set to the center of the amplitude of this signal and output the signal Since the receiving circuit is provided, it is possible to reduce the influence of the power supply voltage fluctuation on the output signal.

  Furthermore, by adjusting the m value of the receiving circuit and the resistance value R of the first resistor, the constant current of the receiving circuit and the reference current of the transmitting circuit can be reduced, so that low EMI and low power consumption are achieved. Can be achieved.

  In the first embodiment, the configuration in which the transmission circuit has the push-pull circuit that push-pull-controls the constant current of the constant current circuit has been described. In this embodiment, in particular, the push-pull circuit for reducing power supply noise and ground noise. The detailed configuration will be described.

  FIG. 3 is a diagram showing a main configuration of an interface circuit 100a according to the second embodiment which is an aspect of the present invention. The configurations of the transmission line 2 and the receiving circuit 3 are the same as those in the first embodiment.

  As shown in FIG. 3, the transmission circuit 1a includes a third constant current circuit 5a connected to the voltage source and a fourth constant current circuit 5b connected to the ground potential.

  Further, the transmission circuit 1a is a push-pull circuit that includes a transistor 19 that is a first switch circuit whose source is connected to the third constant current circuit 5a, and a second transistor whose source is connected to the fourth constant current circuit 5b. A transistor 20 as a switch circuit, a transistor 21 as a third switch circuit whose source is connected to the third constant current circuit 5a, and a fourth constant current circuit 5b whose drain is connected to the drain of the transistor 21. Are connected between the voltage source VDD and the drain of the transistor 20, the transistor 22 being the fourth switch circuit, the third resistor 23 connected between the drain of the transistor 19 and the ground potential, And a fourth resistor 24, and an inverter 25 connected between the input terminal 4 and the gate terminals of the transistors 21 and 22. .

  The transistor 19 is of a PMOS type, and its inverting input gate terminal is connected to the input terminal 4 so as to be switched on / off based on a predetermined signal input.

  The transistor 20 is an NMOS type, and has a gate terminal connected to the input terminal 4 and is turned on and off in reverse to the transistor 19 based on a predetermined signal input.

  The transistor 21 is a PMOS type, and an inverting input gate terminal is connected to the input terminal 4 via the inverter 25, and the transistor 20 and the transistor 20 are similarly switched on and off based on a predetermined signal input.

  The transistor 22 is of the NMOS type, the gate terminal is connected to the input terminal 4 via the inverter 25, and the transistor 19 is switched on and off similarly based on a predetermined signal input.

  Further, the transmission line 2 is connected between the transistor 21 and the transistor 22 via the output terminal 7. Thereby, a signal current is output from between the transistor 21 and the transistor 22 to the transmission line 2.

  As described above, the transistors 19 to 22 operate in a complementary manner. Although the input signal is delayed by the inverter 25, a delay circuit (not shown) equal to the delay time of the inverter is provided between the input terminal 4 and the gate terminals of the transistors 19 and 20. The transistors 22 are ideally switched at the same time.

  Next, the operation of the interface circuit 100a having the above configuration will be described. Hereinafter, the case where the predetermined signal input to the input terminal 4 is “1” and the case where it is “0” will be described separately. Since the operation of the receiving circuit 3 is the same as that of the first embodiment, the description thereof is omitted.

  When the predetermined signal input is “1”, that is, when the input is High, the transistor 19 is turned off, the transistor 20 is turned on, and the transistor 21 in which the signal obtained by inverting the input signal by the inverter 25 is input to the gate terminal is turned on. Then, the transistor 22 is turned off.

  Thereby, the constant current Ic of the constant current circuit 5 a is applied as a signal current to the transmission line 2 via the transistor 21. That is, the constant current Ic generated by the constant current circuit 5a is transmitted through the transmission line 2 and applied from the input terminal 8 to the receiving circuit 3, and the transmitting circuit 1 is in a push state. The constant current Ic of the constant current circuit 5 b flows from the voltage source VDD to the ground via the fourth resistor 24 and the transistor 20. That is, the constant current Ic generated by the constant current circuit 5b is maintained in a closed state in the transmission circuit 1 via the above-described path.

  On the other hand, when the predetermined signal input is “0”, that is, the input is Low, the transistor 19 is turned on, the transistor 20 is turned off, and a signal obtained by inverting the input signal by the inverter 25 is input to the gate terminal. Is turned off, and the transistor 22 is turned on.

  As a result, the constant current Ic of the constant current circuit 5 b is applied as a negative signal current to the transmission line 2 via the transistor 22. That is, when the constant current circuit 5b is in conduction with the transmission line 2, the current on the receiving circuit 3 side is pulled, and the constant current Ic is transmitted from the receiving circuit 3 through the transmission line 2, and the output terminal 7 of the transmitting circuit 1a. And the transmission circuit 1 enters the pull state. The constant current Ic of the constant current circuit 5 a flows from the transistor 19 and the voltage source VDD to the ground via the third resistor 23. That is, the constant current Ic generated by the constant current circuit 5a is maintained in a closed state in the transmission circuit 1 via the above-described path.

  Thus, by securing a path through which a constant current flows to the constant current circuits 5a and 5b, dynamic current changes can be suppressed, and generation of power supply noise and ground noise can be reduced. It has become.

  Through the above-described operation, the constant current Ic (signal current) is push-pull controlled from the transmission circuit 1 based on a predetermined signal input such as an image data signal or a clock signal, and is output to the transmission line 2 as a transmission signal.

  As described above, according to the interface circuit of the present embodiment, a path through which a constant current flows to the constant current circuit of the transmission circuit is secured, and a dynamic current change is suppressed to reduce power supply noise and ground noise. Since the generation is reduced, it is possible to reduce the influence of the power supply voltage fluctuation on the output signal.

  In the present embodiment, the case where each of the switch circuits uses a PMOS-type or NMOS-type transistor has been described. However, if the same operation is performed, the switch circuit may be replaced with another element, a circuit configuration, or the like. Of course, there are similar actions and effects.

  In the second embodiment, the detailed configuration of the push-pull circuit for reducing power supply noise and ground noise has been described. However, in this embodiment, the push-pull control that realizes push-pull control with a simpler circuit configuration than the second embodiment is described. The pull circuit will be described.

  FIG. 4 is a diagram illustrating a main configuration of an interface circuit 100b according to the third embodiment which is an aspect of the present invention. The configurations of the transmission line 2 and the receiving circuit 3 are the same as those in the first embodiment.

  As shown in FIG. 4, the transmission circuit 1b includes a third constant current circuit 5a connected to the voltage source VDD and a fourth constant current circuit 5b connected to the ground potential.

  Further, the transmission circuit 1b is a push-pull circuit, which is a transistor 26, which is a first switch circuit having a source connected to the third constant current circuit 5a, and a drain connected to the drain of the transistor 26. A transistor 27 which is a second switch circuit having a source connected to the circuit 5b, and an inverter 28 which is connected between the gate terminals of the transistors 26 and 27 and the input terminal 4 and inverts the input signal. .

  The transistor 26 is a PMOS type, and is turned on / off based on a predetermined signal input. The transistor 27 is an NMOS type, and is turned on / off in reverse to the transistor 26 based on a predetermined signal input. Thus, the transistors 26 and 27 operate in a complementary manner.

  Further, the transmission line 2 is connected between the transistor 26 and the transistor 27 via the output terminal 7. As a result, a signal current is output from between the transistor 26 and the transistor 27 to the transmission line 2.

  Next, the operation of the interface circuit 100b having the above configuration will be described. Hereinafter, as in the above-described embodiment, the case where the predetermined signal input to the input terminal 4 is “1” and the case where it is “0” will be described separately. Since the operation of the receiving circuit 3 is the same as that of the first embodiment, the description thereof is omitted.

  When the predetermined signal input is “1”, that is, when the input is High, the transistor 26 is turned on and the transistor 27 is turned off.

  As a result, the constant current Ic of the constant current circuit 5 a is applied as a signal current to the transmission line 2 via the transistor 26. That is, the constant current Ic generated by the constant current circuit 5a is transmitted through the transmission line 2 and applied to the receiving circuit 3 from the input terminal 8, and the transmitting circuit 1b is in a push state. Here, the path of the constant current Ic of the constant current circuit 5b is forcibly cut off because the transistor 27 is off.

  On the other hand, when the predetermined signal input is “0”, that is, when the input is low, the transistor 26 is turned off and the transistor 27 is turned on.

  As a result, the constant current Ic of the constant current circuit 5 b is applied as a negative signal current to the transmission line 2 via the transistor 27. That is, when the constant current circuit 5b is brought into conduction with the transmission line 2, the current on the receiving circuit 3 side is pulled, and the constant current Ic is transmitted from the receiving circuit 3 through the transmission line 2, and the output terminal 7 of the transmitting circuit 1b. And the transmission circuit 1b enters the pull state. Here, the path of the constant current Ic of the constant current circuit 5a is forcibly cut off because the transistor 26 is off.

  As described above, since no current path is secured for the constant current circuits 5a and 5b, a dynamic current change can occur, but at least the current consumption of the transmission circuit can be reduced. .

  Through the above-described operation, the constant current Ic (signal current) is push-pull controlled from the transmission circuit 1b based on a predetermined signal input such as an image data signal or a clock signal, and is output to the transmission line 2 as a transmission signal.

  In the present embodiment, the case where each of the switch circuits uses a PMOS-type or NMOS-type transistor has been described. However, if the same operation is performed, the switch circuit may be replaced with another element, a circuit configuration, or the like. Of course, there are similar actions and effects.

  In each of the above-described embodiments, the configuration in which the impedance matching transistor is provided in the receiving circuit to suppress the reflected wave to the transmission line has been described. In this embodiment, the receiving circuit for converting the received signal current into a voltage. A configuration that suppresses the reflected wave with respect to the transmission line by impedance matching of the resistors will be described.

  FIG. 5 is a diagram illustrating a main configuration of an interface circuit 100c according to a fourth embodiment which is an aspect of the present invention. In addition, the structure of the transmission circuit 1a and the transmission line 2 is the same as that of Example 2 in the figure.

  The receiving circuit 3a includes a first constant current circuit 9 connected to the power supply VDD, a first resistor 11a connected between the first constant current circuit 9 and the transmission line 2 and the ground potential, a power supply The second constant current circuit 12 connected to VDD, the second resistor 14a connected between the second constant current circuit 12 and the ground potential, the resistance end of the first resistor 11a and the second resistor A comparator 15 having an input connected to the resistance end of the resistor 14a, and inverter circuits 16 and 17 connected to the comparator 15 and the output for shaping the output and outputting a signal from the output terminal 18. .

  The first constant current circuit 9 forms a current mirror circuit by sharing the power source VDD with the second constant current circuit 12, and the second constant current circuit 12 is the first constant current circuit 9 of the first constant current circuit 9. The current Iz / m having a magnitude proportional to 1 / m (m ≧ 1) of the output current Iz of the constant current circuit 9 is output.

  As described above, the resistance value R of the first resistor 11a is adjusted so as to be impedance matched with the transmission line 2 (impedance Rs = 50Ω) (here, R = Rs = 50Ω), and the reflected wave to the transmission line 2 is reflected. It is designed to suppress the occurrence of.

  The second resistor 14a has a resistance value mR that is m times that of the first resistor 11a, and converts the constant current Iz / m generated by the second constant current circuit 12 into a voltage (reference voltage Vref = IzR). It is supposed to be. The resistance terminal of the second resistor 14 a is connected to the input of the converter 15, and a reference voltage generated at the resistance terminal is input to the comparator 15. By adjusting (increasing) the value of m, the power consumption in the second resistor 14a can be reduced.

  The comparator 15 compares the potential 11a of the first resistor with the potential of the second resistor 14a and outputs a predetermined signal.

  Next, the operation of the interface circuit 100c having the above configuration, particularly the operation of the receiving circuit 3a will be described in detail.

  First, based on a predetermined signal input such as an image data signal or a clock signal, a constant current Ic (signal current) is push-pull controlled from the transmission circuit 1a and output to the transmission line 2 as a transmission signal. Hereinafter, as in the above-described embodiment, the case where the predetermined signal input to the input terminal 4 is “1” and the case where it is “0” will be described separately.

  When the predetermined signal input is “1”, that is, when the input is High, the constant current Ic generated by the constant current circuit 5a is transmitted through the transmission line 2 and applied to the reception circuit 3a from the input terminal 8, and the transmission circuit 1 is pushed. It becomes a state.

Thereby, in the receiving circuit 3a, the input constant current Ic and the constant current Iz generated by the first constant current circuit 9 are voltage V _push (= Iz × R + Ic × R) by the first resistor 11a. Is converted to

The voltage V _push and the voltage Vref (reference voltage) are compared by the comparator 15, and since the voltage V _push is higher than the voltage Vref, a signal in a high state is output.

  On the other hand, when the predetermined signal input is “0”, that is, when the input is Low, the constant current circuit 5b is brought into conduction with the transmission line 2, so that the current on the receiving circuit 3a side is pulled and the receiving circuit 3a The constant current Ic is transmitted through the transmission line 2 and flows into the output terminal 7 of the transmission circuit 1a, and the transmission circuit 1a is pulled.

As a result, in the receiving circuit 3a, the difference current between the constant current Ic flowing out from the input terminal 8 and the constant current Iz generated by the first constant current circuit 9 is converted to the voltage V _pull (= Iz) by the first resistor 11a. × R−Ic × R).

Then, the comparator 15 compares the voltage V _pull with the voltage Vref (reference voltage), and outputs a low-level signal because the voltage V _pull is lower than the voltage Vref.

  Here, the waveform of the input voltage of the comparator 15 generated as described above is the same as in FIG. Therefore, similarly to the first embodiment, it is possible to reduce the influence of power supply voltage fluctuation, manufacturing variation, and temperature change on the output signal of the comparator 15.

  As described above, according to the interface circuit of the present embodiment, as in the first embodiment, impedance matching with the transmission line is performed, and the value obtained by converting the voltage of the transmitted signal and the amplitude of this signal are located at the center. Since the receiving circuit that compares the reference voltage value set in this way and outputs a signal is provided, it is possible to reduce the influence of power supply voltage fluctuation, manufacturing variation, and temperature change on the output signal. Further, compared with the first embodiment, it is not necessary to adjust the value of the current Iz of the first constant current circuit 9 for impedance matching, and the circuit design can be facilitated.

  In the fourth embodiment, the transmission circuit described in the second embodiment is selected as the transmission circuit. However, it is needless to say that the transmission circuit described in the first or third embodiment can be applied. .

  Further, in each of the embodiments described above, the value of m is described as being 1 or more in order to reduce the power consumption on the receiving circuit side. However, even if the value of m is less than 1, the power supply for at least the output signal is used. Of course, the influence of voltage fluctuation can be reduced.

  In each of the above embodiments, the voltage source VDD on the transmission circuit side and the voltage source VDD on the reception circuit side may be common or may be provided separately.

It is a figure which shows the principal part structure of the interface circuit which concerns on Example 1 which is 1 aspect of this invention. FIG. 6 is a diagram illustrating a waveform of an input voltage of a comparator of one embodiment of the present invention. It is a figure which shows the principal part structure of the interface circuit which concerns on Example 2 which is 1 aspect of this invention. It is a figure which shows the principal part structure of the interface circuit which concerns on Example 3 which is 1 aspect of this invention. It is a figure which shows the principal part structure of the interface circuit which concerns on Example 4 which is 1 aspect of this invention.

Explanation of symbols

1, 1a, 1b Transmission circuit 2 Transmission line 3, 3a Reception circuit
4 Input terminals 5a, 5b Constant current circuit 6 Push-pull circuit 7 Output terminal 8 Input terminal 9 First constant current circuit 10 First transistor 11, 11a First resistor 12 Second constant current circuit 13 Second transistor 14, 14a Second resistor 15 Comparator 16 Inverter 17 Inverter 18 Output terminal 19 Transistor 20 Transistor 21 Transistor 22 Transistor 23 First resistor 24 Second resistor 25 Inverter 26 Transistor 27 Transistor 28 Inverters 100, 100a, 100b, 100c Inter Face circuit

Claims (5)

A transmission circuit that outputs a current signal by push-pull control of a constant current based on a predetermined signal input;
A transmission line for transmitting the signal output from the transmission circuit;
A first constant current circuit connected to a power source; a first transistor connected to the first constant current circuit and the transmission line; impedance matched with the transmission line; and a gate voltage kept constant; , A first resistor connected between the first transistor and a ground potential, and a second resistor connected to the power source and outputting a current of 1 / m magnitude of the first constant current circuit. A constant current circuit; a second resistor connected between the second constant current circuit and the ground potential; the second resistor having a resistance value m times the first resistor; and the potential of the first resistor; An interface circuit comprising: a receiving circuit having a comparator that compares the potential of the second resistor and outputs a predetermined signal.   The receiving circuit is connected between the second constant current circuit and the second resistor, has a channel length of 1 / m of the first transistor, and a gate voltage is kept constant. The interface circuit according to claim 1, further comprising a second transistor. A transmission circuit that outputs a current signal by push-pull control of a constant current based on a predetermined signal input;
A transmission line for transmitting the signal output from the transmission circuit;
A first constant current circuit connected to a power source; and a first resistor connected between the first constant current circuit and a ground potential and connected to the transmission line and impedance-matched to the transmission line And a second constant current circuit that is connected to a power source and outputs a current of 1 / m magnitude of the first constant current circuit, and between the second constant current circuit and the ground potential A receiving circuit having a second resistor connected and having a resistance value that is m times the first resistor, and a comparator that compares the potentials of the two resistors and outputs a predetermined signal; An interface circuit characterized by that. The transmission circuit includes:
A third constant current circuit connected to the voltage source;
A fourth constant current circuit connected to the ground potential;
A first switch circuit which is connected between the third constant current circuit and the ground potential and switches based on the predetermined signal input;
A second switch circuit connected between the voltage source and the fourth constant current circuit, wherein the first switch circuit and the second switch circuit are switched on and off in reverse based on the predetermined signal input;
A third switch circuit that is connected to the third constant current circuit and is switched on and off in the same manner as the second switch circuit based on the predetermined signal input;
A fourth switch circuit connected between the third switch circuit and the fourth constant current circuit, wherein the first switch circuit and the fourth switch circuit are similarly switched on and off based on the predetermined signal input; Have
4. The interface circuit according to claim 1, wherein the transmission line is connected between the third switch circuit and the fourth switch circuit. 5. The transmission circuit includes:
A third constant current circuit connected to the voltage source;
A fourth constant current circuit connected to the ground potential;
A first switch circuit that switches based on the predetermined signal;
A first switch circuit based on the predetermined signal and a second switch circuit that is switched on and off in reverse,
4. The interface circuit according to claim 1, wherein the transmission line is connected between the first switch circuit and the second switch circuit. 5.

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