JP2007005775A5

JP2007005775A5 -

Info

Publication number: JP2007005775A5
Application number: JP2006139863A
Authority: JP
Filing date: 2006-05-19
Publication date: 2009-04-30
Anticipated expiration: 2026-05-19

Claims

A semiconductor layer having a first channel formation region, a second channel formation region, and an intermediate impurity region provided between the first channel formation region and the second channel formation region;
A gate insulating layer provided on the semiconductor layer;
A first conductive layer provided on the gate insulating layer;
And second and third conductive layers provided on the first conductive layer,
The first conductive layer is provided at a position overlapping the first channel formation region, the second channel formation region, and the intermediate impurity region,
The second conductive layer is provided at a position overlapping the first channel formation region,
The semiconductor device, wherein the third conductive layer is provided at a position overlapping with the second channel formation region.

First and second high-concentration impurity regions; first and second low-concentration impurity regions provided between the first high-concentration impurity region and the second high-concentration impurity region; and the first First and second channel formation regions provided between the low concentration impurity region and the second low concentration impurity region, and between the first channel formation region and the second channel formation region. A semiconductor layer having a third low-concentration impurity region provided;
A gate insulating layer provided on the semiconductor layer;
A first conductive layer provided on the gate insulating layer;
And second and third conductive layers provided on the first conductive layer,
The first conductive layer is provided at a position overlapping the first and second channel formation regions and the first to third low-concentration impurity regions,
The second conductive layer is provided at a position overlapping the first channel formation region,
The semiconductor device, wherein the third conductive layer is provided at a position overlapping with the second channel formation region.

A semiconductor layer having a plurality of channel formation regions and a plurality of intermediate impurity regions respectively provided between adjacent channel formation regions;
A gate insulating layer provided on the semiconductor layer;
A first conductive layer provided on the gate insulating layer;
A plurality of second conductive layers provided on the first conductive layer,
The first conductive layer is provided at a position overlapping the plurality of channel formation regions and the plurality of intermediate impurity regions,
Each of the plurality of second conductive layers is provided at a position overlapping with the plurality of channel formation regions.

First and second high-concentration impurity regions; first and second low-concentration impurity regions provided between the first high-concentration impurity region and the second high-concentration impurity region; and the first A plurality of channel formation regions provided between the low concentration impurity region and the second low concentration impurity region, and a plurality of third low concentration impurity regions provided between the adjacent channel formation regions, A semiconductor layer having
A gate insulating layer provided on the semiconductor layer;
A first conductive layer provided on the gate insulating layer;
A plurality of second conductive layers provided on the first conductive layer,
The first conductive layer is provided at a position overlapping the plurality of channel formation regions, the first and second low concentration impurity regions, and the plurality of third low concentration impurity region regions,
Each of the plurality of second conductive layers is provided at a position overlapping with the plurality of channel formation regions.

In any one of Claims 1 thru | or 4,
The semiconductor device, wherein the semiconductor layer is provided over a substrate having an insulating surface.

In any one of Claims 1 thru | or 4,
A semiconductor device, wherein a semiconductor substrate is used as the semiconductor layer.

A semiconductor layer, a gate insulating layer provided on the semiconductor layer, a first conductive film provided on the gate insulating layer, and a second conductive film provided on the first conductive film; Forming,
On the second conductive film, the first and second regions, and a third region provided between the first region and the second region, the third region Forming a first resist pattern in which the film thickness of the first and second regions is greater than the film thickness of the region;
Etching the second conductive film to form a second conductive layer using the first resist pattern, etching the first conductive film to form a first conductive layer; and Removing the third region of the first resist pattern to form a second resist pattern in which the first region and the second region remain;
Etching the second conductive layer using the second resist pattern to form a third conductive layer and a fourth conductive layer,
Removing the second resist pattern;
By adding an impurity to the semiconductor layer, a first channel formation region is formed at a position overlapping with the third conductive layer, and a second channel formation region is formed at a position overlapping with the fourth conductive layer; A method for manufacturing a semiconductor device, wherein an intermediate impurity region is formed at a position that does not overlap the third conductive layer and the fourth conductive layer but overlaps the first conductive layer.

A first semiconductor layer; a gate insulating layer provided on the first semiconductor layer; a first conductive film provided on the gate insulating layer; and provided on the first conductive film. Forming a second conductive film;
On the second conductive film, fourth and fifth regions, first and second regions provided between the fourth region and the fifth region, and the first region And a third region provided between the first region and the second region, and the first and second regions are thicker than the third to fifth regions. 1 resist pattern is formed,
Etching the second conductive film to form a second conductive layer using the first resist pattern, etching the first conductive film to form a first conductive layer; and Removing the third to fifth regions of the first resist pattern to form a second resist pattern in which the first region and the second region remain;
Etching the second conductive layer using the second resist pattern to form a third conductive layer and a fourth conductive layer,
Removing the second resist pattern;
By adding an impurity to the semiconductor layer, a first channel formation region is formed at a position overlapping with the third conductive layer, and a second channel formation region is formed at a position overlapping with the fourth conductive layer; A low concentration impurity region is formed at a position not overlapping with the third conductive layer and the fourth conductive layer and overlapping with the first conductive layer, and a high concentration impurity is positioned not overlapping with the first conductive layer. A method for manufacturing a semiconductor device, wherein a region is formed.

A semiconductor layer, a gate insulating layer provided on the semiconductor layer, a first conductive film provided on the gate insulating layer, and a second conductive film provided on the first conductive film; Forming,
The second conductive film has a plurality of first regions and a plurality of second regions provided between the adjacent first regions, respectively, and the film thickness of the second region Forming a first resist pattern having a thickness greater than that of the first region,
Etching the second conductive film to form a second conductive layer using the first resist pattern, etching the first conductive film to form a first conductive layer; and Removing the plurality of second regions of the first resist pattern to form a second resist pattern in which the plurality of first regions remain;
Using the second resist pattern, the second conductive layer is etched to form a plurality of third conductive layers,
Removing the second resist pattern;
By adding an impurity to the semiconductor layer, a plurality of channel formation regions are formed at positions overlapping with the plurality of third conductive layers, respectively, and do not overlap with the plurality of third conductive layers and the first A method for manufacturing a semiconductor device, wherein an intermediate impurity region is formed in a position overlapping with a conductive layer.

A semiconductor layer, a gate insulating layer provided on the semiconductor layer, a first conductive film provided on the gate insulating layer, and a second conductive film provided on the first conductive film; Forming,
A first region adjacent to the third and fourth regions, a plurality of first regions provided between the third region and the fourth region, on the second conductive film. A plurality of second regions provided between each of the first regions, and forming a first resist pattern in which the thickness of the first region is larger than the thickness of the second to fourth regions,
Etching the second conductive film to form a second conductive layer using the first resist pattern, etching the first conductive film to form a first conductive layer; and Removing the third and fourth regions of the first resist pattern and the plurality of second regions to form a second resist pattern in which the plurality of first regions remain;
Using the second resist pattern, the second conductive layer is etched to form a plurality of third conductive layers,
Removing the second resist pattern;
By adding an impurity to the semiconductor layer, a plurality of channel formation regions are formed at positions overlapping with the plurality of third conductive layers, respectively, and do not overlap with the plurality of third conductive layers and the first A method for manufacturing a semiconductor device, wherein a low concentration impurity region is formed at a position overlapping with a conductive layer, and a high concentration impurity region is formed at a position not overlapping with the first conductive layer.

In any one of Claims 7 to 10,
The method for manufacturing a semiconductor device, wherein the semiconductor layer is provided over a substrate having an insulating surface.

In any one of Claims 7 to 10,
A method for manufacturing a semiconductor device, wherein a semiconductor substrate is used as the semiconductor layer.