JP2006522460A - Lateral rubista structure and formation method - Google Patents

Abstract

An ESD resistant rubyster structure based on FINFET technology is provided.
The structure uses vertical fins (50) (thin vertical members including the source, drain and body of the device), and in alternative embodiments may or may not include a gate (60). Sometimes. The gate (60) can be connected to the external electrode (51) to be protected to form a self-actuating device, or it can be connected to a reference voltage (92). This device may be used in digital or analog circuits.

Description

  The present invention relates generally to the field of integrated circuit manufacturing, and more particularly to the field of manufacturing devices for ESD (electrostatic discharge) protection in integrated circuit technology using FINFETs.

  FINFET is a promising integrated circuit technology that uses thin vertical members (10 nm to 100 nm) as the source, drain, and body of the FET (field effect transistor), next to the two vertical sides and the top of the channel. Having a gate. When the body is made thin in this way, the coupling (coupling) of the gate becomes extremely strong, so that a complete depletion operation is easily realized. In these structures, stress events related to EOS (electrical overstress) such as ESD (electrostatic breakdown) and other voltages or currents present in semiconductor manufacturing, shipping, and testing processes. ) Overvoltage protection is required. EOS events include overcurrent stress, latch-up, and high current that occurs during and when stressed. HBM (human body model), MM (machine model), CDM (charged device model), TLU (transient latch-up), cable discharge model, CN (cassette ESD events and other events such as those occurring during the model) can cause electrical failure of the FINFET structure.

  Thus, it is clear that these structures need to be protected from EOS and ESD in order to provide proper ESD protection to the FINFET structures.

US Pat. No. 6,015,993 shows a technique for constructing a lateral ESD device having a gated diode with a channel formed in bulk silicon or in the device layer of an SOI wafer. This structure is not compatible with the FINFET structure and the FINFET process.
US Pat. No. 6,015,993

  The present invention relates to a structure that provides EOS and ESD protection for FINFET technology.

  In accordance with aspects of the present invention, an ESD LUBISTOR structure based on FINFET technology uses vertical fins (50) (thin vertical members including the source, drain, and body of the device), and in an alternative embodiment, a gate (60) may or may not be provided. The gate (60) can be connected to an external electrode (51) to be protected to form a self-activating device, or it can be connected to a reference voltage (92). This device may be used in digital or analog circuits.

  Therefore, a structure including an elongated vertical member (50) is provided in the integrated circuit based on the substrate (10). An elongated vertical member (50) protrudes from the substrate (10) and includes a semiconductor having a top (57) and two opposing elongated sides (48, 49). A first electrode (52) is formed at the first end of the vertical member, and a second electrode (54) of opposite polarity is formed at the second end on the opposite side of the vertical member. The first and second electrodes (52, 54) are doped with an electrode concentration higher than the dopant concentration in the central portion (53) of this vertical member between the first electrode and the second electrode.

  The ESD LUBISTOR structure based on FINFET technology uses vertical fins (50) (thin vertical members including the source, drain and body of the device) and may or may not have a gate (60) in the alternative. There is also. The gate (60) can be connected to the external electrode (51) to be protected to form a self-actuating device, or it can be connected to a reference voltage (92). This device may be used in digital or analog circuits.

Some of the advantages that may be obtained from one or more preferred embodiments of the present invention are listed below.
-Providing ESD-robust structures that are compatible with FINFET semiconductor processes and structures.
-Use of an ESD resistant FINFET structure and support structure.
-Providing fins with diode terminals separated by body. This fin is controlled by the gate or not gated, such as p ⁺ / p ⁻ / n ⁺ , p ⁺ / n ⁻ / n ⁺ , or p ⁺ / p ⁻ / n ⁻ / n ⁺ Having a doped structure of
-Provision of gated lateral diodes. The diode is formed on an insulator layer and has a p ⁺ / p ⁻ / n ⁺ , or p ⁺ / n ⁻ / n ⁺ , or p ⁺ / p with a body contact to a lightly doped body. ^- / ⁿ - having a / ^{n +} structure.
-Providing a FINFET structure with a body contact that enables a dynamic threshold FINFET device for use as an ESD protection element.
-Providing FINFET resistor elements that are electrically and thermally stable (gated or not gated) for ESD protection.

  Reference is now made to the drawings. More specifically, referring to FIG. 1, the process sequence according to the present invention includes a preparatory step for forming fins (for fin-diode structures) or vertical members. These steps are conventional in FINFET technology. Typically, for example, by forming nitride sidewalls on a dummy oxide mesa formed on a silicon layer (single crystal or epitaxial film), a suitable width (less than 10 nm) Form a hard mask. This silicon film may be single crystal silicon (including the epitaxial layer). Polysilicon, selective silicon, strained silicon on silicon germanium films and other films can also be used. The silicon is etched with a directional dry etch, leaving a thin vertical member, for example, 10 nm thick, 1 μm wide, and 0.1 μm long, thereby obtaining the electrodes and body of the device.

With reference to FIGS. 1 and 2, a top view of FIG. 2 shows a gate 60 overlying a fin 50. This gate extends between the front side and the back side of the paper surface in the cross-sectional view of FIG. In FIG. 1, fins 50 are disposed on the substrate 10, and the fins 50 are separated from the gate 60 by a gate dielectric 55, for example, a 1 nm oxide. In this embodiment, the fins 50 rest directly on the silicon substrate, but in some versions of the invention, insulation embedded in an SOI (silicon on insulator) wafer between the substrate and the fins. May have a dielectric layer such as a body. In this example, the substrate is an SOI substrate, and the buried oxide 20 is shown as the lower device layer 10. In some versions, the fin can be formed from the device layer and placed on the buried oxide. For example, the fins 50, like the layer 10, the first p ^- is doped. Gate 60 is polysilicon (poly) and is later doped by implantation.

FIG. 3 illustrates this gate implantation step with a temporary layer 65. Layer 65 is, for example, an anti-reflective coating (ARC) and is deposited as a step to form other devices in this circuit and is planarized to the level of gate 60, for example by chemical mechanical polishing. The gate 60 is implanted with high dose ions of p or n. Preferably, the gate 60 receives an N ⁺⁺ dose of about 10 ²¹ / cm ² , for example two orders of magnitude greater than an N ⁺ dose of 5 × 10 ¹⁹ / cm ² . With this degree of difference, further doping received by the gate will not significantly affect the work function of the gate.

4 and 5, a non-critical opening is opened to expose the cathode 52 and N ⁺ implantation (with a dose at least an order of magnitude less than the gate implant). Optionally, the ARC can be opened, or any other convenient mask, such as a photoresist layer 67, can be placed and patterned. FIG. 5 shows the same process for implanting the anode 54. Again, the dose (P ⁺ ) is 1/10 of the gate dose.

  The injection into the fin is performed at an earlier stage. If the fin is polysilicon and a single polarity is required, the injection into the fin can be done when the fin is placed. Optionally, this fin can be formed prior to well implantation and an opening can be opened in the photoresist for well implantation so that the fin can implant P or N or both simultaneously with these wells. receive.

  Referring now to FIG. 6, the fin-diode device is shown after the last interlayer dielectric has been deposited, the openings for contacts 72, 74, and 76 have been formed and the contact material has been deposited. Since these contacts are at a low level, it is appropriate to use tungsten (W) when used for other contacts at this level. If poly is used at this level, poly contacts are sufficient. For the electrical interconnects, standard interconnect (Al or Cu) and ILD (inter-level dielectric) processes can be used. Aluminum interconnect structures are adhesive refractory metals (eg, TiN), refractory metals (eg, Ti, TiNi, Co), so as to provide adhesion, diffusion barriers, and good electrical conductivity. And may consist of an aluminum structure. The copper interconnect structure may consist of an adhesive film (eg, TaN), a refractory metal (eg, Ta), and a copper interconnect. In general, for Cu interconnect structures, these structures are formed using a single damascene process or a dual damascene process. For ESD and resistance ballasting in these structures, refractory metals can be used. This is because these metals have a high melting point.

  The advantage of the gate in this fin-diode structure shown in FIG. 6 is that the current in the gated p + / n− / n + structure can be adjusted by electrical control of the gate structure. Therefore, leakage, bias, and electrical stress can be reduced by connecting this gate structure to an anode or cathode node, ground plane or power supply, voltage or current reference circuit, or electrical network. Can be adjusted. The disadvantage of this gate is that the gate insulator can be damaged. The circuit designer will make a selection based on a tradeoff between advantages and disadvantages.

  A set of several fin-diode structures are placed in parallel to lower the total series resistance of the ESD structure, increase the total propagation current capacity, and increase the power-to-failure. Can be higher. For example, all anode and cathode connections can be such that these parallel FINFET diode structures can be electrically connected. These parallel structures may or may not use the same gate electrode. The number of parallel elements can also be individualized and customized based on ESD requirements or performance goals. Furthermore, resistance stabilization can be performed, different gate biases can be established to improve current uniformity and provide a means to turn these elements on and off. Compared to prior art devices, the advantages of these parallel elements are 1) three-dimensional capability, 2) improved current stabilization control, and 3) improved current uniformity control. In a two-dimensional singlefinger Lubistor structure, the current uniformity is not inherent in the design and therefore weakens the ESD resistance per micron cross-sectional area. In these structures, each fin-diode structure is separated from adjacent regions by heating. Therefore, due to thermal coupling between adjacent regions, the temperature profile and ESD resistance in each fin-diode parallel element are not uniform.

Furthermore, these fin-diode structures can be designed as p + / p− / n + elements or p + / n− / n + elements. Differences in the position of metallurgical junctions make one embodiment superior to others for different purposes. This has been shown experimentally by the inventor and is a function of doping concentration and application. This choice will be affected by the capacitance-resistance trade-off, as well as the possibility of using fin-diode injections initially targeted for some other application. A low resistance value is more suitable for the current purpose, and when the available implant dose is relatively low, the p ⁺ / n ⁻ / n ⁺ structure is preferred because of the higher electron mobility. Conversely, the p ⁺ / p ⁻ / n ⁺ structure may be preferred when the available implant dose is relatively high.

  A halo implant can be established in these devices, thereby improving lateral conduction, better junction capacitance, and improved breakdown characteristics. In this case, it is preferable to provide a halo for only one doping polarity to prevent the formation of a parasitic diode due to incorrect halo implantation with the wrong polarity.

FIG. 7 shows an alternative version of a fin-diode structure in which the channel is doped P ⁻ and there is no separate gate. The advantage of this structure is that the gate is not exposed to ESD voltage stress. Electrical overstress in the gate dielectric can be removed by not having the gate structure present.

  The CDM failure mechanism can occur due to the electrical connection of the gate structure for the FINFET ESD protection network. In previous embodiments that included gates, electrical control was possible, but in that embodiment, more electrical connections and / or design areas for electrical circuits were required. In this embodiment, fewer electrical connections are required, thereby allowing a denser circuit.

  In the embodiment of FIG. 7, a plurality of parallel fin-diode structures can be densely arranged, thereby increasing the resistance of ESD per unit area. Furthermore, resistance stabilization and current uniformity control can be addressed by changing the effective resistance value in the individual fin-diode structure. By physically separating adjacent fin-diode structures, thermal coupling between adjacent elements can be reduced. Appropriate spacing conditions and non-uniform adjacent spacing conditions can ensure that adjacent element spacing is optimized, thereby obtaining optimal temperature results. In this way, a thermal method is obtained that can optimize these elements. This thermal method cannot be used with a two-dimensional Lubistor element, but is a natural method for the construction of a parallel fin-diode structure.

Similarly, FIG. 8 shows a version in which the body is divided into two doped areas, a first P ^- body region and a second N ^- body region. In this fin-diode structure, the metal junction can be optimized and placed regardless of the gate structure. The implant can be a p-type well or an n-type well, or both, a halo type (eg, angled, twisted, or straight) implant, or other well known It can also be provided by implantation or diffusion process steps. The gradual profile introduced by the p + / p− and n + / n− transitions results in a junction that is less rapidly changing and can improve ESD resistance.

Versions of devices with gates can be divided into several categories:
1) N ⁺ / P type fin-gated diode with body in contact with substrate 10. In this case, there is a path to the substrate.
2) N ⁺ / P type fin-gated diode with body floating on SOI.
3) N ⁺ / P-type fin-gated diode on SOI with the gate in contact with the (P ⁺ )-type body. Thereby, the anode potential can be dynamically controlled.
4) N ⁺ / P type fin-gated diode on SOI with the gate in contact with the N ⁺ type cathode.
To provide ESD protection to a FINFET device, it is also advantageous to form a resistor element that is integrated into the FINFET device or a resistor element that is not integrated into the FINFET device, or both.

  Referring to FIG. 10, a FINFET device can be formed by a technique similar to that used in the previous embodiment, having the same polarity source and drain implants separated by opposite polarity bodies. This body is covered by a gate insulator 55 and a gate 155. This structure can be formed by symmetric or asymmetric implantation, which provides an advantage over ESD. In addition, resistors can be incorporated into the same structure to obtain an ESD-resistant FINFET structure. For example, the second gate 155 'can be placed in series with the drain structure. At this location, this second gate structure provides a block of heavily doped source / drain implants, so that the lightly doped fins form a resistance. This gate structure performs the following two functions. First, a resistive region is formed in the source or drain region, and second, a salicide film disposed on the source or drain region provides a means of not shorting the resistor. This forms a “ballasting resistor” that is essentially integrated into the FINFET. This structure is referred to as a FIN-R-FET structure.

  Furthermore, the second gate 155 'can be removed from the FIN-R-FET, as was done with the fin-diode structure. Removing this second gate structure after salicidation eliminates electrical overstress or ESD problems associated with the resistor element.

  This element 150 for use in a FIN-R-FET device can also be constructed as a single resistor element. This is accomplished by placing an n-channel FINFET in the n-type well or n-type body region. This resistor or FIN-R device can be used to provide ESD immunity to the FINFET, fin-diode, or for circuit applications. As discussed previously, this gate can be removed to eliminate electrical overstress in the physical element.

  In addition, salicide can be removed from the source, drain, and gate regions to improve the ESD tolerance of the FINFET device. Since the gate length of this device is relatively short compared to a planar device, salicide can be removed in the gate region.

  Referring now to FIG. 9, a schematic diagram of an exemplary arrangement for protecting a circuit from ESD at terminal 51 is shown. Dashed lines, indicated by numerals 72 and 74, indicate options discussed below. Two FIN-LUBISTORs according to the invention are connected between the protected node 53 and the voltage terminals at 54 and 52 '. In this case, gate 60 is connected to terminal 54, so that the ESD event dynamically reduces the resistance of one of these diodes. Alternatively, terminal 60 could be connected to a power source. To eliminate electrical overstress on these gate structures, an electrical circuit comprising a FINFET device is used to electrically isolate these gate structures from electrical overstress. An electrical circuit with a FINFET-based inverter or a FINFET-based reference control network for electrical isolation from the power supply eliminates overstress and establishes a potential to prevent leakage.

  For use as an ESD network for HBM (Human Body Model), MM (Mechanical Model) and other ESD events, multiple lateral fin-diode structures are used in parallel to minimize series resistance and It should be possible to discharge large currents through this structure without causing failures in the diode element or circuit. Therefore, a plurality of parallel fin-diode elements are connected and arranged between the input pin and the power source.

  For voltage tolerance, FIG. 9 shows an ESD network constructed from fin-diode elements in a series configuration that includes a fin-diode 75 within dashed line 72 here. A fin-diode structure may be constructed where the anode of the first fin-diode element is connected to the first pad and the cathode is connected to the anode of the second fin-diode. This can be extended in a string (series) or series configuration. For each stage aligned in series, a plurality of parallel fin-diode elements may be placed in each “stage” of the fin-diode string. These string configurations can be between input pads and power supplies, between two common power supply pads (eg, VDD1 and VDD1), between any two different power supply pads (eg, VCC and VDD), and any It can be placed between ground rails (eg, VSS1 and VSS2) and between any different ground rails (eg, VSS and VEE). These fin-diode series elements can be configured as a single series continuous string configuration or a back-to-back configuration, whereby current can flow in both directions between these two pads. In the case of input pads to a power supply, there is generally only a single fin-diode string configuration, so that current flows in a single direction.

  For HBM and CDM (Charging Device Model) events, ESD circuits can be improved using ESD circuits consisting of fin-diode elements, fin-resistor (FIN-R) elements, and FINFETs. . FIG. 11 is an example of a circuit that implements ESD protection using fin-diode element 75, fin-resistor 94, and FINFET 96 with its gate grounded. For example, the gate voltage of the fin-diode is provided by the reference network, not the ESD voltage itself. Thereby, the current capacity of the diode 75 can be controlled better.

  In addition, resistive ballast FIN-R-FET elements can be used to achieve ESD protection. This circuit can be implemented in two ways: The first uses a FIN-R resistor in series with the FINFET. To achieve ESD protection, multiple parallel FIN-R resistors are placed in series with multiple FINFET devices. In another embodiment, multiple parallel FIN-R-FET structures may be used to achieve ESD protection. These above-described structures are arranged in a cascade configuration, which results in a larger snapback voltage or voltage tolerance. For ESD protection, as with fin-diode elements, a series of FINFET stages with FIN-R resistor elements can be connected where each stage includes a set of elements in parallel.

  Devices constructed in accordance with the present invention are not limited to ESD applications, but can also be used in the traditional role of circuitry, such as circuitry for digital, analog, and RF (radio frequency). The present invention is not limited to silicon wafers, and other wafers such as SiGe alloys or GaAs can be used. These structures can be placed on strained silicon films using films with SiGe deposited or grown. These structures are suitable for SOI (Silicon On Insulator), RF SOI, and UTSOI (Ultra Thin SOI).

  While the invention has been described in terms of one preferred embodiment, those skilled in the art will recognize that the invention can be practiced in various versions within the spirit and scope of the appended claims.

  The present invention may be utilized in integrated circuit electronic devices and their manufacture.

1 is a sectional view of a device according to the invention at an early stage. 1 is a plan view of a device according to the invention at an early stage. FIG. FIG. 6 is a cross-sectional view of the same device at another stage. FIG. 6 is a cross-sectional view of the same device at another stage. FIG. 6 is a cross-sectional view of the same device at another stage. FIG. 6 is a cross-sectional view of the same device at another stage. FIG. 6 illustrates an example of an alternative embodiment. FIG. 6 illustrates an example of an alternative embodiment. It is the schematic of the device in an ESD use example. FIG. 6 is a diagram of a fin-resistor integrated with a FINFET. It is a figure which shows another example of ESD use.

Claims (14)

A structure in an integrated circuit based on a substrate (10),
An elongated vertical member (50) comprising a semiconductor protruding from the substrate (10) and having a top (57) and two opposing elongated sides (48, 49);
The first electrode (52) is formed at the first end of the vertical member,
A second electrode (54) having a polarity opposite to that of the first electrode is formed at a second end of the vertical member on the opposite side of the first end;
The first electrode and the second electrode (52, 54) are doped with an electrode concentration higher than the dopant concentration in the central portion (53) between the first electrode and the second electrode. The structure of claim 1, wherein one of the electrodes (52, 54) is doped p ⁺ and the other of the electrodes (52, 54) is doped n ⁺ . The one is the electrode (52, 54) is doped ^{p +,} said central portion (53) is p ^- doped, the other of said electrodes (52, 54) are doped ^{n +,} in claim 1 Description structure.   The first sub-portion (53A) of the central portion adjacent to the first electrode (52) has the same polarity as the first electrode (52) and is doped at a lower concentration, and the second electrode (54) A structure according to claim 2, wherein the second sub-portion (53B) of the central portion adjacent to is doped with the same polarity as the second electrode (54) and at a lower concentration. The structure according to claim 2, wherein the dopants are arranged in the order of p ⁺ / p ⁻ / n ⁻ / n ⁺ .   A gate (60) is further disposed on the upper central portion (53) and proximate to the central portion of the two side surfaces, the gate (60) being formed by a dielectric gate layer (55). 6. A structure according to any preceding claim, wherein the structure is separate from the vertical member (50).   7. An ESD (electrostatic breakdown) protection circuit attached to an external terminal (51) of an integrated circuit and comprising a structure according to any of claims 1-6.   The ESD protection circuit according to claim 7, further comprising two devices (75), wherein the external terminal is connected to the anode (52) of the first device and the cathode (54) of the other device.   The substrate (10) is an SOI substrate having a buried insulator layer (20), and the vertical member (50) is disposed directly on the buried insulator layer (20). The ESD protection circuit according to 1.   The ESD protection circuit according to claim 7, wherein the substrate (10) is a bulk substrate and the vertical member (50) is disposed directly on the bulk substrate.   The ESD protection circuit according to claim 7, comprising a plurality of fin-diode structures (75) connected in parallel between the external terminal (51) and the voltage terminal (91, 91 ').   The ESD protection circuit according to claim 7, comprising at least one fin-diode structure (75) in series configuration between two external terminals (51).   The ESD protection circuit according to claim 7, comprising at least one fin-diode structure (75) and at least one FIN-R resistor element (94).   The ESD protection circuit of claim 7, comprising at least one fin-diode structure (75), at least one FIN-R resistor element (94), and at least one FINFET element (96).

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