CN107492569B - Gated diode and method of forming the same - Google Patents

Gated diode and method of forming the same Download PDF

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CN107492569B
CN107492569B CN201610407349.6A CN201610407349A CN107492569B CN 107492569 B CN107492569 B CN 107492569B CN 201610407349 A CN201610407349 A CN 201610407349A CN 107492569 B CN107492569 B CN 107492569B
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forming
gate structure
fin
doped region
gate
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CN107492569A (en
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7391—Gated diode structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4885—Wire-like parts or pins
    • H01L21/4889—Connection or disconnection of other leads to or from wire-like parts, e.g. wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66356—Gated diodes, e.g. field controlled diodes [FCD], static induction thyristors [SITh], field controlled thyristors [FCTh]

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Abstract

A gated diode and method of forming the same, the gated diode comprising: a substrate having a fin portion thereon; the first grid structure is positioned on the surface of the fin part; the first doped region and the second doped region are positioned in the fin parts at two sides of the first grid structure; the first connecting plug is positioned on the surface of the first doping region, and the first connecting plug covers the surface of the first doping region exposed by the first grid structure; and the second connecting plug is positioned on the surface of the second doping area. The invention also provides a method for forming the grid-controlled diode. According to the invention, the first connecting plug covering the surface of the first doping region is formed, so that the contact area between the first connecting plug and the first doping region is increased, the width of a current channel at the interface of the first connecting plug and the first doping region is effectively increased, the problem of current congestion at the interface of the first connecting plug and the first doping region is improved, and the performance of the formed gate-controlled diode is improved.

Description

Gated diode and method of forming the same
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a grid-controlled diode and a forming method thereof.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density and higher integration. As the transistor is currently widely used as the most basic semiconductor device, as the element density and the integration degree of the semiconductor device are improved, the gate size of the planar transistor is shorter and shorter, and the conventional planar transistor has weak control capability on channel current, generates a short channel effect, generates leakage current, and finally affects the electrical performance of the semiconductor device.
In order to overcome the short channel effect of the transistor and suppress the leakage current, a Fin field effect transistor (Fin FET) is proposed in the prior art, and the Fin FET is a common multi-gate device. The structure of the fin field effect transistor comprises: the semiconductor device comprises a fin part and a dielectric layer, wherein the fin part and the dielectric layer are positioned on the surface of a semiconductor substrate, the dielectric layer covers a part of the side wall of the fin part, and the surface of the dielectric layer is lower than the top of the fin part; the grid electrode structure is positioned on the surface of the dielectric layer, the top of the fin part and the surface of the side wall; and the source region and the drain region are positioned in the fin parts at two sides of the grid structure.
As the size of semiconductor devices is reduced, the factors that semiconductor chips are damaged by static electricity are increasing. Electrostatic Discharge (ESD) protection circuits are often used in existing chip designs to reduce Electrostatic damage to the chip. Prior art esd protection circuits typically include gated diodes with finfet structures.
However, as the size of semiconductor devices is continuously reduced, the gated diode having the finfet structure often has insufficient performance.
Disclosure of Invention
The invention provides a grid-controlled diode and a forming method thereof, which are used for improving the performance of the grid-controlled diode.
To solve the above problems, the present invention provides a gate controlled diode, including:
a substrate having a fin portion thereon; the first grid electrode structure is positioned on the surface of the fin part and spans the fin part to cover the top of the fin part and partial surface of the side wall; the first doped region and the second doped region are positioned in the fin parts at two sides of the first grid structure, first type doped ions are arranged in the first doped region, and second type doped ions are arranged in the second doped region; the first connecting plug is positioned on the surface of the first doping region, the first connecting plug is a current input end of the grid control diode, and the first connecting plug covers the surface of the first doping region exposed by the first grid structure; and the second connecting plug is positioned on the surface of the second doping region and is a current output end of the grid-controlled diode.
Optionally, the first connection plug is further in contact with a top surface of the first gate structure.
Optionally, the gate-controlled diode further includes a well region located in the substrate and the fin portion, and the well region has second-type doped ions therein; the first gate structure includes a first work function layer, which is a first type of work function layer.
Optionally, the ratio of the projected area of the first connection plug at the top surface of the first gate structure to the top surface area of the first gate structure is in the range of 1/3 to 2/3.
Optionally, the first gate structure includes a first gate stack and a first sidewall on a sidewall of the first gate stack; the first connecting plug also covers the surface of the first side wall.
Optionally, the gated diode further includes: the second grid electrode structure is positioned on the surface of the fin portion, stretches across the fin portion, covers the top of the fin portion and partial surface of the side wall of the fin portion, and has a preset interval with the first grid electrode structure; the first doping area is positioned in the fin part between the first grid structure and the second grid structure; the first connecting plug is filled in a gap between the first gate structure and the second gate structure and is in contact with the top surfaces of the first gate structure and the second gate structure.
Optionally, the gate-controlled diode further includes a well region located in the substrate and the fin portion, and the well region has second-type doped ions therein; the second gate structure includes a second work function layer of a first type.
Optionally, the ratio of the projected area of the first connecting plug at the top surface of the first gate structure to the top surface area of the first gate structure is in the range of 1/3 to 2/3, or the ratio of the projected area of the first connecting plug at the top surface of the second gate structure to the top surface area of the second gate structure is in the range of 1/3 to 2/3; or the ratio of the projected area of the first connecting plug at the top surface of the first gate structure to the top surface area of the first gate structure is in the range of 1/3 to 2/3, and the ratio of the projected area of the first connecting plug at the top surface of the second gate structure to the top surface area of the second gate structure is in the range of 1/3 to 2/3.
Optionally, the second gate structure includes a second gate stack and a second sidewall on a sidewall of the second gate stack; the first connecting plug also covers the surface of the second side wall.
Optionally, the gated diode further includes a third doped region located in the fin portion of the second gate structure on a side away from the first doped region, where the third doped region has second-type doped ions; and the third connecting plug is positioned on the surface of the third doped region and is a current output end of the grid-controlled diode.
Optionally, the first type of doped ions are P-type ions, the second type of doped ions are N-type ions, and the first type of work function layer is a P-type work function layer.
Optionally, the gate-controlled diode is configured to form an electrostatic discharge protection structure, the first connection plug is configured to input an electrostatic discharge current, and the second connection plug is configured to output the electrostatic discharge current.
Optionally, the material of the first connection plug includes tungsten.
Correspondingly, the invention also provides a forming method of the grid-controlled diode, which comprises the following steps:
providing a substrate, wherein the substrate is provided with a fin part; forming a first grid electrode structure on the surface of the fin part, wherein the first grid electrode structure stretches across the fin part and covers the top of the fin part and part of the surface of the side wall of the fin part; forming a first doping area and a second doping area in fin parts on two sides of the first grid structure, wherein the first doping area is internally provided with first type doping ions, and the second doping area is internally provided with second type doping ions; forming a first connecting plug positioned on the surface of the first doping region, wherein the first connecting plug is a current input end of a grid control diode, and the first connecting plug covers the surface of the first doping region exposed by the first grid structure; and forming a second connecting plug on the second doping region, wherein the second connecting plug is a current output end of the grid-controlled diode.
Optionally, in the step of forming the first connection plug, the first connection plug is further in contact with a top surface of the first gate structure.
Optionally, after providing the substrate and before forming the first gate structure, the forming method further includes: forming a well region in the substrate and the fin portion, wherein the well region is internally provided with second-type doped ions; the step of forming the first gate structure comprises: and forming a first grid laminated layer on the surface of the fin part, wherein the first grid laminated layer comprises a first work function layer and a first grid electrode which are sequentially arranged on the surface of the fin part, and the first work function layer is a first type work function layer.
Optionally, the step of forming the first gate structure includes: forming a first grid laminated layer on the surface of the fin part; forming a first side wall on the side wall of the first grid laminated layer; in the step of forming the first connecting plug, the first connecting plug also covers the surface of the first sidewall.
Optionally, after providing the substrate and before forming the first doped region and the second doped region, the forming method further includes: forming a second grid electrode structure on the surface of the fin portion, wherein the second grid electrode structure stretches across the fin portion and covers the top of the fin portion and part of the surface of the side wall of the fin portion, and a preset interval is formed between the second grid electrode structure and the first grid electrode structure; in the step of forming the first doped region and the second doped region, forming the first doped region in a fin portion between the second gate structure and the first gate structure, and forming a second doped region in a fin portion on one side of the first gate structure away from the first doped region; in the step of forming the first connection plug, the first connection plug is filled in a gap between the first gate structure and the second gate structure and is in contact with top surfaces of the first gate structure and the second gate structure.
Optionally, after providing the substrate and before forming the second gate structure, the forming method further includes: forming a well region in the substrate and the fin portion, wherein the well region is internally provided with second-type doped ions; the step of forming the second gate structure comprises: and forming a second gate stack layer on the surface of the fin portion, wherein the second gate stack layer comprises a second work function layer and a second gate electrode which are sequentially arranged on the surface of the fin portion, and the type of the second work function layer is a first type work function layer.
Optionally, the step of forming the second gate structure includes: forming a second grid laminated layer on the surface of the fin part; forming a second side wall on the side wall of the second grid laminated layer; in the step of forming the second connecting plug, the second connecting plug also covers the surface of the second sidewall.
Compared with the prior art, the technical scheme of the invention has the following advantages:
according to the invention, the first connecting plug is formed and covers the surface of the first doping region exposed out of the first gate structure, so that the contact area between the first connecting plug and the first doping region is increased, the width of a current channel at the interface between the first connecting plug and the first doping region is effectively increased, the problem of current congestion at the interface between the first connecting plug and the first doping region is improved, and the performance of the formed gate-controlled diode is improved.
In an alternative scheme of the invention, the first connection plug also covers the top surface of the first gate structure, so that heat generated by the fin part can be led out to the first connection plug through the first gate structure, the heat dissipation capability of the gate-controlled diode is effectively improved, the self-heating problem of the gate-controlled diode is relieved, and the stability of the gate-controlled diode is improved.
Drawings
FIG. 1 is a schematic cross-sectional view of a gated diode;
fig. 2 to 7 are schematic cross-sectional views of intermediate structures of respective steps of a gate-controlled diode forming method according to an embodiment of the present invention.
Detailed Description
As can be seen from the background art, the prior art gated diode has a problem of insufficient performance. The reason for the insufficient performance problem is analyzed by combining a structure of a grid-controlled diode:
referring to fig. 1, a schematic cross-sectional structure of a gated diode is shown.
The gated diode includes: the substrate 10, the surface of the substrate 10 has a fin 11, and the substrate 10 and the fin 11 have an N-type well region nw therein; a first gate electrode 21 and a second gate electrode 22 on the surface of the fin portion 11; a P-type doped region 30P located in the fin 11 between the first gate 21 and the second gate 22; the N-type doped region 30N is positioned in the fin portion 11 on the side, far away from the P-type doped region 30P, of the first grid 21 and the second grid 22; and a connection plug 40 positioned on the P-type doped region 30P and the N-type doped region 30N.
As the size of the semiconductor device is reduced, the sizes of the P-type doped region 30P, the N-type doped region 30N and the connecting plug 40 are reduced, so that the contact area between the connecting plug 40 and the P-type doped region 30P and the N-type doped region 30N is smaller and smaller, and the width of the current channel from the connecting plug 40 to the gate controlled diode is correspondingly reduced. When the gate controlled diode is turned on, a current congestion phenomenon easily occurs at a connection between the connection plug 40 and the P-type doped region 30P or the N-type doped region 30N.
Particularly, when the gate diode is used in an electrostatic discharge protection structure, an electrostatic current discharging static electricity flows into the gate diode from the connection plug 40 on the surface of the P-type doped region 30P when the gate diode is broken down. The electrostatic current is easy to generate current congestion at the interface between the connecting plug 40 and the P-type doped region 30P, so that the discharge performance of the formed electrostatic discharge protection structure is limited.
In order to solve the technical problem, the invention provides a method for forming a gate-controlled diode, which comprises the following steps:
providing a substrate, wherein the substrate is provided with a fin part; forming a first grid electrode structure on the surface of the fin part, wherein the first grid electrode structure stretches across the fin part and covers the top of the fin part and part of the surface of the side wall of the fin part; forming a first doping area and a second doping area in fin parts on two sides of the first grid structure, wherein the first doping area is internally provided with first type doping ions, and the second doping area is internally provided with second type doping ions; forming a first connecting plug positioned on the surface of the first doping region, wherein the first connecting plug is a current input end of a grid control diode, and the first connecting plug covers the surface of the first doping region exposed by the first grid structure; and forming a second connecting plug on the second doping region, wherein the second connecting plug is a current output end of the grid-controlled diode.
According to the invention, the first connecting plug is formed and covers the surface of the first doping region exposed out of the first gate structure, so that the contact area between the first connecting plug and the first doping region is increased, the width of a current channel at the interface between the first connecting plug and the first doping region is effectively increased, the problem of current congestion at the interface between the first connecting plug and the first doping region is improved, and the performance of the formed gate-controlled diode is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Referring to fig. 2 to 7, cross-sectional views of intermediate structures of respective steps of an embodiment of a method for forming a gated diode according to the present invention are shown.
In the present embodiment, the gate diode for forming the esd protection structure is taken as an example for description, and the invention should not be limited thereto. The technical scheme of the invention can also be used for forming grid-controlled diodes for other purposes.
Referring to fig. 2 and 3, wherein fig. 3 is a cross-sectional view along line AA of fig. 2, a substrate 100 is first provided, the substrate 100 having a fin 110 thereon.
The substrate 100 is an operation platform for a subsequent semiconductor process; the fin 110 is subsequently used to form a gated diode. The number of the fins 110 on the surface of the substrate 100 is one or more. Specifically, a plurality of fin portions 110 are formed on the surface of the substrate 100, and the fin portions 110 are arranged in parallel. In addition, in this embodiment, an isolation structure 102 is further disposed between the fins 110 on the surface of the substrate 100 to achieve electrical isolation.
The forming step of the substrate 100 includes: providing a semiconductor substrate; etching the semiconductor substrate to form a substrate 100 and a fin portion 110 on the surface of the substrate 100; isolation structures 102 are formed between adjacent fins 110.
The semiconductor substrate is used for providing an operating platform for a semiconductor process and is also used for etching and forming the fin portion 110. The material of the semiconductor substrate is selected from monocrystalline silicon, polycrystalline silicon or amorphous silicon; the semiconductor substrate may also be selected from silicon, germanium, gallium arsenide, or silicon germanium compounds; the semiconductor substrate may also be other semiconductor materials. The invention is not limited in this regard. In this embodiment, the semiconductor substrate is a single crystal silicon substrate, and thus the substrate 100 and the fin 110 are made of single crystal silicon.
In other embodiments of the present invention, the semiconductor substrate may also be selected to have an epitaxial layer or a silicon-on-epitaxial layer structure. Specifically, the semiconductor substrate may include a substrate and a semiconductor layer on a surface of the substrate. The semiconductor layer may be formed on the substrate surface using a selective epitaxial deposition process. The substrate can be a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a silicon-on-insulator substrate, a germanium-on-insulator substrate, a glass substrate, or a III-V compound substrate, such as a gallium nitride substrate or a gallium arsenide substrate; the material of the semiconductor layer is silicon, germanium, silicon carbide, silicon germanium or the like. The selection of the substrate and the semiconductor layer is not limited, and the substrate suitable for the process requirement or easy integration and the material suitable for forming the fin part can be selected. And the thickness of the semiconductor layer can be controlled through an epitaxial process, so that the height of the formed fin part can be accurately controlled.
The step of forming the fin 110 includes: forming a first patterning layer on the surface of the semiconductor substrate, wherein the first patterning layer is used for defining the position and the size of the fin portion 110; and etching the semiconductor substrate by taking the first patterning layer as a mask to form the substrate 100 and the fin part 110 positioned on the surface of the substrate 100.
The first patterned layer may be a patterned photoresist layer formed using a photoresist coating process and a photolithography process. In addition, in order to reduce the size of the fins 110 and the distance between adjacent fins 110, the first patterning layer may also be formed by a multiple patterning mask process. The multiple patterning mask process comprises the following steps: a Self-aligned Double patterning (SaDP) process, a Self-aligned triple patterning (Self-aligned triple patterning) process, or a Self-aligned quadruple patterning (SaDDP) process.
The isolation structures 102 are used to achieve electrical isolation between the fins 110 and between the gated diode and other semiconductor devices in the substrate 100. The top surface of the isolation structure 102 is lower than the top surface of the fin 110 to expose the sidewalls of the fin 110, so that the sidewalls of the fin 110 can be covered by the subsequently formed first and second gates.
It should be noted that, in this embodiment, the gated diode further includes a well region 101 located in the substrate 100 and the fin portion 110, and is used for defining an active region of the gated diode. The well 101 has second type doped ions therein. In this embodiment, the second type doped ions are N-type ions, that is, the well region 101 is an N-type well region. The second type of dopant ions includes phosphorous ions, arsenic ions, or antimony ions.
In this embodiment, the well region 101 is formed after the fin portion 110 and the isolation structure 102 are formed. The step of forming the well region 101 includes: an ion implantation process is used to form the well region 101 in the substrate 100 and the fin portion 110.
The formation of well region 101 after fin 110 and isolation structure 102 is merely exemplary. In another embodiment of the present invention, the well region may also be formed after the fin portion is formed and before the isolation structure is formed, that is, after the well region is formed in the substrate and the fin portion by using an ion implantation process, the isolation structure is formed.
In addition, in other embodiments of the present invention, the well region may also be formed before the fin portion is formed. The step of forming the well region comprises: directly forming a well region in the semiconductor substrate by adopting an ion implantation process; and after ion implantation, etching the semiconductor substrate to form the base and the fin part, wherein the bottom of the well region is lower than the surface of the base.
Referring to fig. 4, a first gate structure 210 is formed on the surface of the fin 110, and the first gate structure 210 spans the fin and covers a portion of the surface of the top and the sidewalls of the fin 110.
In this embodiment, the gated diode is used for forming an esd protection structure, and therefore, after providing the substrate 100, the forming method further includes: forming a second gate structure 220 on the surface of the fin 110, wherein the second gate structure 220 crosses over the fin 110 and covers a portion of the surface of the top and the sidewall of the fin 110, and a predetermined gap is formed between the second gate structure 220 and the first gate structure.
The first gate structure 210 and the second gate structure 220 are used for shielding part of the fin portion 110 in the subsequent process of forming a doped region, so as to prevent the formed doped region from being in direct contact with each other, thereby forming a gated diode.
The first gate structure 210 includes a first gate stack, and the first gate stack includes a first gate dielectric layer 211, a first work function layer 212, and a first gate electrode 213, which are sequentially located on the surface of the fin 110.
The second gate structure 220 includes a second gate stack, which includes a second gate dielectric layer 221, a second work function layer 222, and a second gate electrode 223 sequentially disposed on the surface of the fin 110.
The first gate structure 210 and the second gate structure 220 are dummy gate structures, and in order to avoid forming a current channel in the well region 101 under the first gate structure 210 and the second gate structure 220, the types of the first work function layer 212 and the second work function layer 222 are different from the type of doped ions in the well region 101. In this embodiment, the well region has a second type of doped ions therein, so that the first work function layer is of the first type, and the second work function layer is of the first type.
Specifically, in this embodiment, the second type dopant ions are N-type ions, so the first work function layer 212 and the second work function layer 222 are P-type work function layers, and the P-type work function layers include a titanium nitride layer.
The first gate stack and the second gate stack may be formed simultaneously. Specifically, the step of forming the first gate stack and the second gate stack includes: firstly, forming a gate material lamination on the surface of the fin portion 110, wherein the gate material lamination comprises a dielectric material layer, a work function material layer and an electrode material layer; forming a second patterned layer on the surface of the gate stack, wherein the second patterned layer is used for defining the size and the position of the first gate stack and the second gate stack; and etching the gate material lamination by taking the second patterning layer as a mask to form the first gate lamination and the second gate lamination which are positioned on the surface of the fin portion.
The first gate structure 210 further includes a first sidewall 214 on the sidewall of the first gate stack, and the second gate structure 220 further includes a second sidewall 224 on the sidewall of the second gate stack. The first and second sidewalls 214 and 224 are used to prevent the first and second doped regions and the first and third doped regions from being too close to each other to cause punch-through.
The first sidewall 214 and the second sidewall 224 may be formed simultaneously. Specifically, the step of forming the first sidewall 214 and the second sidewall 224 includes: forming a side wall material layer covering the first grid laminated layer and the second grid laminated layer; etching the side wall material layer by an anisotropic etching method, removing the side wall material layer on the top surface of the first gate stack and the second gate stack, and forming the first side wall 214 and the second side wall 224
In this embodiment, a plurality of fins 110 are formed on the surface of the substrate 100, and the plurality of fins 110 are parallel to each other, so that the first gate structure 210 and the second gate structure 220 cross the plurality of fins 110 and are disposed perpendicular to the fins 110.
Referring to fig. 5, a first doped region 310 and a second doped region 320 are formed in the fin 110 at two sides of the first gate structure 210, wherein the first doped region 310 has a first type of doped ions therein, and the second doped region 320 has a second type of doped ions therein.
In this embodiment, the gated diode is used for forming an electrostatic discharge protection structure, and therefore, in order to improve the protection capability of the formed electrostatic discharge protection structure, the gated diode further has a second gate structure 220, so after the first gate structure 210 and the second gate structure 220 are formed, the forming method further includes: a third doped region 330 is formed in the fin 110 on a side of the second gate structure 220 away from the first doped region 310, wherein the third doped region 330 has a second type of dopant ions.
The first doped region 310, the second doped region 320 and the third doped region 330 are used to form a P region and an N region of the gated diode, so that the first type of doped ions and the second type of doped ions have opposite conductivity types.
Specifically, in this embodiment, the first doped region 310 is a P-type doped region, that is, the first type of doped ions are P-type ions, and include boron ions or indium ions; the second doped region 320 and the third doped region 330 are N-type doped regions, that is, the second type doped ions are N-type ions, including phosphorus ions or arsenic ions.
The forming step of the first doped region 310 includes: the first doped region 310 is formed in a fin between the first gate structure 210 and the second gate structure 220. Specifically, the first doping region 310 may be formed by ion implantation.
The second doped region 320 and the third doped region 330 may be formed simultaneously. Specifically, the steps of forming the second doped region 320 and the third doped region 330 include: the second doped region 320 and the third doped region 330 are formed in the fin portion 110 of the first gate structure 210 far away from the first doped region 310 and in the fin portion 110 of the second gate structure 220 far away from the first doped region 310 by ion implantation.
It should be noted that, in this embodiment, the first doped region 310, the second doped region 320 and the third doped region 330 are formed by ion implantation, which is only an example. In other embodiments of the present invention, the first doped region, the second doped region and the third doped region may also be doped regions with stress materials.
Specifically, the step of forming the first doped region with the stress material includes: firstly, forming a first stress layer in a fin part between the first grid structure and the second grid structure; and carrying out ion implantation on the first stress layer to form a first doped region.
The step of forming the second doped region and the third doped region with the stressed material comprises: forming a second stress layer and a third stress layer in the fin portion 110 of the first gate structure far away from the first doped region 310 and the fin portion 110 of the second gate structure 220 far away from the first doped region 310 respectively; and carrying out ion implantation on the second stress layer and the third stress layer to form a second doped region and a third doped region.
It should be noted that the method of forming the first doped region, the second doped region and the third doped region with the stress material by ion implantation is only an example, and in some embodiments of the present invention, the first doped region, the second doped region and the third doped region may also be formed by in-situ ion doping.
Referring to fig. 6 and 7, fig. 6 is a top view of the gated diode structure, and fig. 7 is a cross-sectional view taken along line BB in fig. 6. Forming a first connection plug 410 on the surface of the first doped region 310, wherein the first connection plug 410 is a current input end of a gate controlled diode, and the first connection plug 410 covers the exposed surface of the first doped region 310 of the first gate structure 210; a second connection plug 420 is formed on the second doped region 320, and the second connection plug 420 is a current output terminal of the gated diode.
In this embodiment, the gated diode further includes a third doped region 330, and therefore, the forming method further includes: forming a third connection plug 430 on the third doped region 330, wherein the third connection plug 430 is a current output terminal of the gated diode.
The first connection plug 410, the second connection plug 420 and the third connection plug 430 are respectively used for realizing the connection of the first doped region 310, the second doped region 320 and the third doped region 330 with an external circuit.
Specifically, the gate controlled diode is used to form an electrostatic discharge protection structure, the first connection plug 410 is used to input an electrostatic discharge current, and the second connection plug 420 and the third connection plug 430 are used to output an electrostatic discharge current.
The first connection plug 410 covers the surface of the first doped region 310 exposed by the first gate structure 210. By the method, the contact area between the first connection plug 410 and the first doped region 310 is increased, a current channel between the first connection plug 410 and the first doped region 310 can be effectively increased, the problem of current congestion at the interface between the first connection plug 410 and the first doped region 310 can be effectively solved, and the performance of the formed gated diode is improved.
In this embodiment, the gate controlled diode is used to form an esd protection structure, and the first connecting plug 410 is used to input an esd current. The larger current path between the first connection plug 410 and the first doped region 310 can effectively increase the discharge capability of the electrostatic discharge protection structure, and improve the protection performance of the electrostatic discharge protection structure.
The first gate structure 210 includes a first gate stack and a first sidewall 214 on a sidewall of the first gate stack, and the second gate structure 220 includes a second gate stack and a second sidewall 224 on a sidewall of the second gate stack. The first doping region 310 is located in the fin 110 between the first gate structure 210 and the second gate structure 220, so that the first connection plug 410 located on the surface of the first doping region 310 is located between the first gate structure 210 and the second gate structure 220.
In this embodiment, the first connecting plug 410 further covers the surfaces of the first sidewall 214 and the second sidewall 224. The first connection plug 410 fills a gap between the first gate structure 210 and the second gate structure 220. Therefore, in the step of forming the first coupling plug 410, the first coupling plug 410 may be formed by filling a gap between the first gate structure 210 and the second gate structure 220, which is beneficial to reducing process difficulty and improving yield.
The first connection plug 410 is also in contact with the top surfaces of the first gate structure 210 and the second gate structure 220. Therefore, the first connection plug 410 can conduct heat generated by the fin 110 through the first gate structure 210 and the second gate structure 220, thereby improving the self-heating problem of the gated diode and improving the stability of the device.
Specifically, in this embodiment, the first gate structure 210 further includes a first gate electrode 213, and the second gate structure 220 further includes a second gate electrode 223. The material of the first gate electrode 213 and the second gate electrode 223 includes metal tungsten. The material of the first connection plug 410 includes metal tungsten. The first connection plug 410 is in direct contact with the first gate electrode 213 and the second gate electrode 223, so that the heat dissipation capability of the gate-controlled diode can be effectively improved, and the stability of the device can be improved.
If the coverage area of the first connection plug 410 on the top surface of the first gate structure 210 and the top surface of the second connection plug 220 is too small, it is difficult to improve the heat dissipation capability; if the coverage area of the first connection plug 410 on the top surface of the first gate structure 210 and the top surface of the second connection plug 220 is too large, material waste and process difficulty are easily caused. Specifically, the ratio of the projected area of the first connection plug 410 on the top surface of the first gate structure 210 to the top surface area of the first gate structure 210 is in the range of 1/3 to 2/3; the ratio of the projected area of the second connecting plug on the top surface of the second gate structure 220 to the top surface area of the second gate structure 220 is 1/3-2/3
The material of the second connection plug 420 and the material of the third connection plug 430 may be the same as the material of the first connection plug 410. The first connection plug 410, the second connection plug 420, and the third connection plug 430 may be simultaneously formed.
Specifically, the step of forming the first, second, and third connection plugs 410, 420, and 430 includes: forming a connection metal layer covering the fin 110, the first gate structure 210 and the second gate structure 220; forming a third patterned layer on the surface of the connection metal layer, wherein the third patterned layer is used for defining the size and the position of the first connection plug 410, the second connection plug 420 and the third connection plug 430; and etching the connection metal layer by using the third patterned layer as a mask to form the first connection plug 410, the second connection plug 420 and the third connection plug 430.
It should be noted that the method of forming the first connection plug 410, the second connection plug 420, and the third connection plug 430 directly by mask etching is only an example, and in other embodiments of the present invention, the first connection plug, the second connection plug, and the third connection plug may also be formed by filling a trench.
Specifically, in other embodiments of the present invention, after the first doped region, the second doped region, and the third doped region are formed, a dielectric layer covering the fin portion, the first gate structure, and the second gate structure is formed; forming a first groove, a second groove and a third groove in the dielectric layer in a mask etching mode, wherein the size and the position of the first groove correspond to those of the first connecting plug, and the size and the position of the second groove and the size and the position of the third groove correspond to those of the second connecting plug and the third connecting plug respectively; and filling conductive materials into the first groove, the second groove and the third groove to form a first connecting plug, a second connecting plug and a third connecting plug.
Correspondingly, the invention also provides a gate-controlled diode, comprising:
a substrate having a fin portion thereon; the first grid electrode structure is positioned on the surface of the fin part and spans the fin part to cover the top of the fin part and partial surface of the side wall; the first doped region and the second doped region are positioned in the fin parts at two sides of the first grid structure, first type doped ions are arranged in the first doped region, and second type doped ions are arranged in the second doped region; the first connecting plug is positioned on the surface of the first doping region, the first connecting plug is a current input end of the grid control diode, and the first connecting plug covers the surface of the first doping region exposed by the first grid structure; and the second connecting plug is positioned on the surface of the second doping region and is a current output end of the grid-controlled diode.
Referring to fig. 6 and 7, a schematic structural diagram of an embodiment of the gated diode of the present invention is shown, wherein fig. 7 is a cross-sectional view taken along line BB in fig. 6.
As shown in fig. 6 and 7, the gated diode includes:
a substrate 100, the substrate 100 having a fin 110 thereon.
The substrate 100 is an operation platform for a subsequent semiconductor process; the fin 110 is subsequently used to form a gated diode. The number of the fins 110 on the surface of the substrate 100 is one or more. Specifically, a plurality of fin portions 110 are formed on the surface of the substrate 100, and the fin portions 110 are arranged in parallel. In addition, in this embodiment, an isolation structure 102 is further disposed between the fins 110 on the surface of the substrate 100 to achieve electrical isolation.
The material of the substrate 100 and the fin 110 is selected from monocrystalline silicon, polycrystalline silicon or amorphous silicon; the semiconductor substrate may also be selected from silicon, germanium, gallium arsenide, or silicon germanium compounds; the semiconductor substrate may also be other semiconductor materials. The invention is not limited in this regard. In this embodiment, the semiconductor substrate is a single crystal silicon substrate, and thus the substrate 100 and the fin 110 are made of single crystal silicon.
In other embodiments of the present invention, the substrate may also be a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a silicon-on-insulator substrate, a germanium-on-insulator substrate, a glass substrate, or a III-V compound substrate, such as a gallium nitride substrate or a gallium arsenide substrate; the fin may be made of silicon, germanium, silicon carbide, silicon germanium, or the like.
The isolation structures 102 are used to achieve electrical isolation between the fins 110 and between the gated diode and other semiconductor devices in the substrate 100. The top surface of the isolation structure 102 is lower than the top surface of the fin 110 to expose the sidewalls of the fin 110, so that the sidewalls of the fin 110 can be covered by the subsequently formed first and second gates.
It should be noted that, in this embodiment, the gated diode further includes a well region 101 located in the substrate 100 and the fin portion 110, and is used for defining an active region of the gated diode. The well region 101 has second type dopant ions. In this embodiment, the second type doped ions are N-type ions, that is, the well region 101 is an N-type well region. The second type of dopant ions includes phosphorous ions, arsenic ions, or antimony ions.
The first gate structure 210 is located on the surface of the fin 110, and the first gate structure 210 crosses the fin 110 to cover a portion of the surface of the top and the sidewall of the fin 110.
In this embodiment, the gate diode is used to form an esd protection structure, and therefore, in order to improve the protection capability of the formed esd protection structure, the gate diode further includes: and the second gate structure 220 is located on the surface of the fin portion 110, the second gate structure 220 crosses the fin portion 110 to cover a part of the surface of the top and the sidewall of the fin portion 110, and a preset interval is formed between the second gate structure 220 and the first gate structure 210.
The first gate structure 210 and the second gate structure 220 are used for shielding part of the fin portion 110 in the subsequent process of forming a doped region, so as to prevent the formed doped region from being in direct contact with each other, thereby forming a gated diode.
The first gate structure 210 includes a first gate stack, and the first gate stack includes a first gate dielectric layer 211, a first work function layer 212, and a first gate electrode 213, which are sequentially located on the surface of the fin 110.
The second gate structure 220 includes a second gate stack, which includes a second gate dielectric layer 221, a second work function layer 222, and a second gate electrode 223 sequentially disposed on the surface of the fin 110.
The first gate structure 210 and the second gate structure 220 are dummy gate structures, and in order to avoid forming a current channel in the well region 101 under the first gate structure 210 and the second gate structure 220, the types of the first work function layer 212 and the second work function layer 222 are different from the type of doped ions in the well region 101.
Specifically, in this embodiment, the well region has a second type of doped ions therein, and the second type of doped ions are N-type ions, that is, the doped ions in the well region 101 are N-type ions, so the first work function layer 212 and the second work function layer 222 are P-type work function layers, and the P-type work function layers include a titanium nitride layer.
The first gate structure 210 further includes a first sidewall 214 on the sidewall of the first gate stack, and the second gate structure 220 further includes a second sidewall 224 on the sidewall of the second gate stack. The first sidewall 214 and the second sidewall 224 are used for the first doped region and the second doped region and the first doped region and the third doped region are too close to cause punch-through.
In this embodiment, a plurality of fins 110 are formed on the surface of the substrate 100, and the plurality of fins 110 are parallel to each other, so that the first gate structure 210 and the second gate structure 220 cross the plurality of fins 110 and are disposed perpendicular to the fins 110.
The first doped region 310 and the second doped region 320 are located in the fin portion 110 on two sides of the first gate structure 210, the first doped region 310 has a first type of doped ions therein, and the second doped region 320 has a second type of doped ions therein.
In this embodiment, the gated diode is used for forming an electrostatic discharge protection structure, and therefore, in order to improve the protection capability of the formed electrostatic discharge protection structure, the gated diode further has a second gate structure 220, so that the first doped region 310 is located in the fin portion between the first gate structure 210 and the second gate structure 220, and the second doped region 320 is located in the fin portion 110 on the side of the first gate structure 210 far away from the second gate structure 220.
In addition, the gated diode further includes: a third doped region 330 in the fin 110 on a side of the second gate structure 220 away from the first doped region 310, the third doped region 330 having a second type of ions therein.
The first doped region 310, the second doped region 320 and the third doped region 330 are used to form a P region and an N region of the gated diode, so that the first type of doped ions and the second type of doped ions have opposite conductivity types.
Specifically, in this embodiment, the first doped region 310 is a P-type doped region, that is, the first type of doped ions are P-type ions, and include boron ions or indium ions; the second doped region 320 and the third doped region 330 are N-type doped regions, that is, the second type doped ions are N-type ions, including phosphorus ions or arsenic ions.
It should be noted that the first doped region 310, the second doped region 320, and the third doped region 330 may also be doped regions with stress layers to improve the performance of the gated diode.
With continued reference to fig. 6 and 7, the gated diode further comprises: a first connection plug 410 located on the surface of the first doped region 310, wherein the first connection plug 410 is a current input end of a gate controlled diode, and the first connection plug 410 covers the exposed surface of the first doped region 310 of the first gate structure 210; and a second connection plug 420 located on the surface of the second doped region 320, wherein the second connection plug 420 is a current output terminal of the gated diode.
The gated diode further comprises the third doped region 330, and thus the gated diode further comprises a third connection plug 430 on the surface of the third doped region 330, wherein the third connection plug 430 is a current output terminal of the gated diode.
The first connection plug 410, the second connection plug 420, and the third connection plug 430 are used to connect the first doped region 310, the second doped region 320, and the third doped region 330 to an external circuit.
Specifically, the gate controlled diode is used to form an electrostatic discharge protection structure, the first connection plug 410 is used to input an electrostatic discharge current, and the second connection plug 420 and the third connection plug 430 are used to output an electrostatic discharge current.
The first connection plug 410 covers the surface of the first doped region 310 exposed by the first gate structure 210. By the method, the contact area between the first connection plug 410 and the first doped region 310 can be increased, a current channel between the first connection plug 410 and the first doped region 310 can be effectively increased, the problem of current congestion at the interface between the first connection plug 410 and the first doped region 310 can be effectively solved, and the performance of the formed gated diode can be improved.
In this embodiment, the gate controlled diode is used to form an esd protection structure, and the first connecting plug 410 is used to input an esd current. The larger current path between the first connection plug 410 and the first doped region 310 can effectively increase the discharge capability of the electrostatic discharge protection structure, and improve the protection performance of the electrostatic discharge protection structure.
The first gate structure 210 includes a first gate stack and a first sidewall 214 on a sidewall of the first gate stack, and the second gate structure 220 includes a second gate stack and a second sidewall 224 on a sidewall of the second gate stack. The first doping region 310 is located in the fin 110 between the first gate structure 210 and the second gate structure 220, so that the first connection plug 410 located on the surface of the first doping region 310 is located between the first gate structure 210 and the second gate structure 220. In this embodiment, the first connecting plug 410 further covers the surfaces of the first sidewall 214 and the second sidewall 224. The first connection plug 410 fills a gap between the first gate structure 210 and the second gate structure 220.
The first connection plug 410 is also in contact with the top surfaces of the first gate structure 210 and the second gate structure 220. Therefore, the first connection plug 410 can conduct heat generated by the fin 110 through the first gate structure 210 and the second gate structure 220, thereby improving the self-heating problem of the gated diode and improving the stability of the device.
Specifically, in this embodiment, the first gate structure 210 further includes a first gate electrode 213, and the second gate structure 220 further includes a second gate electrode 223. The material of the first gate electrode 213 and the second gate electrode 223 includes metal tungsten. The material of the first connection plug 410 includes metal tungsten. The first connection plug 410 is in direct contact with the first gate electrode 213 and the second gate electrode 223, so that the heat dissipation capability of the gate-controlled diode can be effectively improved, and the stability of the device can be improved.
If the coverage area of the first connection plug 410 on the top surface of the first gate structure 210 and the top surface of the second connection plug 220 is too small, it is difficult to improve the heat dissipation capability; if the coverage area of the first connection plug 410 on the top surface of the first gate structure 210 and the top surface of the second connection plug 220 is too large, material waste and process difficulty are easily caused. Specifically, the ratio of the projected area of the first connection plug 410 on the top surface of the first gate structure 210 to the top surface area of the first gate structure 210 is in the range of 1/3 to 2/3; the ratio of the projected area of the second connection plug on the top surface of the second gate structure 220 to the top surface area of the second gate structure 220 is in the range of 1/3 to 2/3.
The material of the second connection plug 420 and the material of the third connection plug 430 may be the same as the material of the first connection plug 410.
In summary, in the invention, by forming the first connection plug, the first connection plug covers the surface of the first doped region exposed by the first gate structure, so that the contact area between the first connection plug and the first doped region is increased, the width of a current channel at the interface between the first connection plug and the first doped region is effectively increased, the problem of current congestion at the interface between the first connection plug and the first doped region is improved, and the performance of the formed gate controlled diode is improved. In addition, in an alternative scheme of the invention, the first connection plug also covers the top surface of the first gate structure, so that heat generated by the fin part can be led out to the first connection plug through the first gate structure, the heat dissipation capability of the gate-controlled diode is effectively improved, the self-heating problem of the gate-controlled diode is relieved, and the stability of the gate-controlled diode is improved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (20)

1. A gated diode, comprising:
a substrate having a fin portion thereon;
the first grid electrode structure is positioned on the surface of the fin part and spans the fin part to cover the top of the fin part and partial surface of the side wall;
the first doped region and the second doped region are positioned in the fin parts at two sides of the first grid structure, first type doped ions are arranged in the first doped region, and second type doped ions are arranged in the second doped region;
the first connecting plug is positioned on the surface of the first doping region, the first connecting plug is a current input end of the grid control diode, and the first connecting plug covers the surface of the first doping region exposed by the first grid structure;
and the second connecting plug is positioned on the surface of the second doping region and is a current output end of the grid-controlled diode.
2. The gated diode of claim 1 wherein the first connection plug is further in contact with a top surface of the first gate structure.
3. The gated diode of claim 2 further comprising a well region within the substrate and fin portion, the well region having second type dopant ions therein;
the first gate structure includes a first work function layer, which is a first type of work function layer.
4. The gated diode of claim 2, wherein a ratio of a projected area of the first connection plug at the top surface of the first gate structure to a top surface area of the first gate structure is in a range of 1/3 to 2/3.
5. The gated diode of claim 1 wherein the first gate structure comprises a first gate stack and first sidewalls on sidewalls of the first gate stack;
the first connecting plug also covers the surface of the first side wall.
6. The gated diode of claim 1, wherein the gated diode further comprises: the second grid electrode structure is positioned on the surface of the fin portion, stretches across the fin portion, covers the top of the fin portion and partial surface of the side wall of the fin portion, and has a preset interval with the first grid electrode structure;
the first doping area is positioned in the fin part between the first grid structure and the second grid structure;
the first connecting plug is filled in a gap between the first gate structure and the second gate structure and is in contact with the top surfaces of the first gate structure and the second gate structure.
7. The gated diode of claim 6 further comprising a well region within the substrate and fin portion, the well region having second type dopant ions therein;
the second gate structure includes a second work function layer of a first type.
8. The gated diode of claim 6, wherein a ratio of a projected area of the first connection plug at the top surface of the first gate structure to a top surface area of the first gate structure is in a range of 1/3 to 2/3, or a ratio of a projected area of the first connection plug at the top surface of the second gate structure to a top surface area of the second gate structure is in a range of 1/3 to 2/3;
or the ratio of the projected area of the first connecting plug at the top surface of the first gate structure to the top surface area of the first gate structure is in the range of 1/3 to 2/3, and the ratio of the projected area of the first connecting plug at the top surface of the second gate structure to the top surface area of the second gate structure is in the range of 1/3 to 2/3.
9. The gated diode of claim 6, wherein the second gate structure comprises a second gate stack and second sidewalls on sidewalls of the second gate stack;
the first connecting plug also covers the surface of the second side wall.
10. The gated diode of claim 6 further comprising a third doped region in the fin on a side of the second gate structure away from the first doped region, the third doped region having a second type of dopant ions;
and the third connecting plug is positioned on the surface of the third doped region and is a current output end of the grid-controlled diode.
11. The gated diode of claim 3 or 7, wherein the first type of dopant ions are P-type ions, the second type of dopant ions are N-type ions, and the first type of work function layer is a P-type work function layer.
12. The gated diode of claim 1 wherein the gated diode is configured to form an esd protection structure, the first connector plug is configured to input esd current, and the second connector plug is configured to output esd current.
13. The gated diode of claim 1, wherein a material of the first connection plug comprises tungsten.
14. A method for forming a gated diode, comprising:
providing a substrate, wherein the substrate is provided with a fin part;
forming a first grid electrode structure on the surface of the fin part, wherein the first grid electrode structure stretches across the fin part and covers the top of the fin part and part of the surface of the side wall of the fin part;
forming a first doping area and a second doping area in fin parts on two sides of the first grid structure, wherein the first doping area is internally provided with first type doping ions, and the second doping area is internally provided with second type doping ions;
forming a first connecting plug positioned on the surface of the first doping region, wherein the first connecting plug is a current input end of a grid control diode, and the first connecting plug covers the surface of the first doping region exposed by the first grid structure;
and forming a second connecting plug on the second doping region, wherein the second connecting plug is a current output end of the grid-controlled diode.
15. The method of forming in claim 14, wherein in the step of forming the first connection plug, the first connection plug is further in contact with a top surface of the first gate structure.
16. The method of forming of claim 15, wherein after providing the substrate and before forming the first gate structure, the method further comprises: forming a well region in the substrate and the fin portion, wherein the well region is internally provided with second-type doped ions;
the step of forming the first gate structure comprises: and forming a first grid laminated layer on the surface of the fin part, wherein the first grid laminated layer comprises a first work function layer and a first grid electrode which are sequentially arranged on the surface of the fin part, and the first work function layer is a first type work function layer.
17. The method of forming of claim 14, wherein forming the first gate structure comprises: forming a first grid laminated layer on the surface of the fin part; forming a first side wall on the side wall of the first grid laminated layer;
in the step of forming the first connecting plug, the first connecting plug also covers the surface of the first sidewall.
18. The method of forming of claim 14, wherein after providing the substrate and before forming the first doped region and the second doped region, the method further comprises: forming a second grid electrode structure on the surface of the fin portion, wherein the second grid electrode structure stretches across the fin portion and covers the top of the fin portion and part of the surface of the side wall of the fin portion, and a preset interval is formed between the second grid electrode structure and the first grid electrode structure;
in the step of forming the first doped region and the second doped region, forming the first doped region in a fin portion between the second gate structure and the first gate structure, and forming a second doped region in a fin portion on one side of the first gate structure away from the first doped region;
in the step of forming the first connection plug, the first connection plug is filled in a gap between the first gate structure and the second gate structure and is in contact with top surfaces of the first gate structure and the second gate structure.
19. The method of forming of claim 18, wherein after providing the substrate and before forming the second gate structure, the method further comprises: forming a well region in the substrate and the fin portion, wherein the well region is internally provided with second-type doped ions;
the step of forming the second gate structure comprises: and forming a second gate stack layer on the surface of the fin portion, wherein the second gate stack layer comprises a second work function layer and a second gate electrode which are sequentially arranged on the surface of the fin portion, and the type of the second work function layer is a first type work function layer.
20. The method of forming of claim 18, wherein forming the second gate structure comprises: forming a second grid laminated layer on the surface of the fin part; forming a second side wall on the side wall of the second grid laminated layer;
in the step of forming the second connecting plug, the second connecting plug also covers the surface of the second sidewall.
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