KR100735000B1 - Lateral lubistor structure and method - Google Patents

Abstract

An ESD LUBISTOR structure based on the FINFET technology uses a vertical fin 50 (thin vertical member including the source, drain and body of the device) with and without the gate 60. Gate 60 may be connected to an external electrode 51 that is protected to make a self-activating device, and may be connected to reference voltage 92. The device can be used in digital or analog circuits.

FINFET, ESD, LUBISTOR, Lateral, Rubister

Description

Lateral LUBISTOR STRUCTURE AND METHOD}

FIELD OF THE INVENTION The present invention relates generally to the field of integrated circuit fabrication, and more particularly to manufacturing devices for electrostatic discharge protection (ESD) in integrated circuit technology using FINFETs.

FINFETs use thin (10 nm to 100 nm) vertical vertical members as the source, drain and body of field effect transistors (FETs), with two vertical sides (two vertical sides) and a promising integrated circuit technology with a gate facing the top of the channel. With this thin body, there is a very strong gate coupling so that fully depleted operation is easily achieved. These structures, like other voltage or current related stress events present in semiconductor fabrication, shipping and testing processes, provide for overvoltage protection from electrical overstress (EOS), such as electrostatic discharge (ESD). Will be needed. EOS events include overcurrent stress, latchup, and high currents that occur during testing and stressing. Like other events, human body model (HBM), machine model (MM), charged device model (CDM), transient latchup (TLU), cable discharge model, cassette model ESD events, such as those that occur during a cassette model (CM), can lead to electrical failure of the FINFET structure.

Thus, it is clear that EOS and ESD protection of the FINFET structure is essential to provide adequate ESD protection for the FINFET structure.

U.S. Patent No. 6,015,993 shows construction techniques for a lateral ESD device with a gate diode, where the channel is in bulk silicon or in the device layer of an SOI wafer. It is formed within. This structure is not compatible with FINFET structures and FINFET processing.

The present invention is directed to structures that provide EOS and ESD protection for FINFET technology.

According to one aspect of the invention, an ESD LUBISTOR structure based on FINFET technology includes a vertical fin 50 (in source, drain and body of the device in alternative embodiments with and without gate 60). Thin vertical member). Gate 60 may be connected to external electrode 51 being protected to make a self-activating device, or may be connected to reference voltage 92. The device can be used in digital or analog circuits.

Thus, a structure is provided in an integrated circuit based on the substrate 10, which includes a semiconductor, protrudes from the substrate 10, and has a top 51 and two opposite elongated sides 48 and 49. And an elongated vertical member 50 having an elongated vertical member 50. The first electrode 52 is formed at the first end of the vertical member, and the second electrode 54 of opposite polarity is formed at the opposite, second end of the vertical member. The first and second electrodes 52 and 54 are doped between the first and second electrodes at an electrode concentration that is greater than the dopant concentration in the central portion 53 of the vertical member.

1 (a and b) show a plan and a cross section of a device according to the invention at an early stage;

2-4 show cross sections of the same device in subsequent steps.

5 and 6 illustrate alternative embodiments.

7 illustrates a schematic representation of a device in an ESD application.

8 shows a view of a fin-resister integrated into a FINFET.

9 illustrates another ESD application.

ESD LUBISTOR structures based on the FINFET technology use vertical fins 50 (thin vertical members comprising the source, drain and body of the device) in alternatives with and without gate 60. Gate 60 may be connected to external electrode 51 being protected to make a self-activating device, or may be connected to reference voltage 92. The device can be used in digital or analog circuits.

Advantages that may arise from one or more preferred embodiments of the present invention are as follows.

-Provision of an ESD-robust structure compatible with FINFET semiconductor processing and structures;

Use of ESD-rugged FINFET structures and supporting structures;

^{- p + / p - / n} +, p + / n - / n + or ^{p + / p - / n -} / n + and which is controlled by the unloading gates (ungated) or the gate, having a doping structure as, Providing a pin having diode terminals separated by a body;

- is formed on the insulator layer, p ⁺ / p having a body contact (body contact) in the slightly doped body ^{- / n +, p + /} n - / n + or ^{p + / p - / n -} / n + Providing a lateral gate diode having a structure;

The provision of a FINFET structure with body contacts enabling a dynamic threshold FINFET device for use as an ESD protection element; And

Providing (gateed or ungateed) FINFET resistor elements to provide electrical and thermal stability of the FINFET device for ESD protection.

Referring now to the drawings, and in particular to FIG. 1, the process sequence according to the present invention involves the preliminary step of forming vertical members or fins (for FIN-Diode structures) traditional in FINFET technology. Typically, for example, by forming a nitride sidewall on a dummy oxide mesa formed on a (single crystal or epitaxial film) silicon layer, an appropriate width (rather than 10 nm) is achieved. Small hard mask is formed. The silicon film may be single crystal silicon (including epitaxial layers). Polysilicon, selective silicon, strained silicon on silicon germanium film or other films may be used. The silicon is etched in a directional dry etch leaving a thin vertical member (eg, 10 nm thick, 1 μm wide, 0.1 μm long) to provide the body of the device and the electrode.

Referring to Figures 1 (a and b), the top view of Figure 1 (b) shows the gate 60 over the fin 50, the gate being the front of the cross section of Figure 1 (a) And the rear is expanding. In FIG. 1A, the substrate 10 includes fins 50 disposed on the substrate, separated from the gate 60 by a gate dielectric 55 (eg, 1 nm oxide). In this example, the fin 50 is located directly on the silicon substrate, but some versions of the present invention may have a dielectric layer between the substrate and the fin (eg, an insulator embedded in a silicon on insulator (SOI) wafer). Can have In this example, the substrate is an SOI substrate and buried oxide 20 is shown as layer 10 below the device. In some versions, fins may be formed on the buried oxide formed from the device layer. By way of example, the fin 50 is initially doped with p ⁻ , as is the layer 10. Gate 60 is polysilicon (poly) that is later doped by an implant.

The gate implant step is illustratively deposited as the step of forming other devices in the circuit, and is planarized anti-reflective coating (e.g., by chemical-mechanical polishing to the gate 60 level). It is shown in FIG. 2 as having a temporary layer 65 which is a reflection coating. A large dose of ions of p or n is implanted in the gate 60. Preferably, the gate 60 is, for example, 5 × 10 ¹⁹ / the order than the N ⁺ dose of 2 ㎠ by greater, given an N ⁺⁺ dose of approximately 10 ²¹ / ㎠. With this difference, any further doping received by the gate will not significantly affect its working function.

In FIGS. 3A and 3B, the non-critical aperture is open to expose N ⁺ to the implanted cathode 52 (with a dose at least one order smaller than the gate implant). Optionally, the gap may be open in the ARC or any other convenient mask, such as photoresist layer 67, may be topped and patterned. 3B shows the same process with the implanted anode 54. Again, the dose P ⁺ is one tenth of the dose of the gate.

At an early stage, the pin was implanted. If the pin is polysilicon and a single polarity is required, it can be implanted when the pin is loaded. Optionally, the pins may be formed before well implants, and the gap may be opened in the photoresist for the well implants to allow the pins to receive P and / or N implants simultaneously with the wells.

Referring now to FIG. 4, a FIN-Diode device is shown after deposition of a final interlayer dielectric, formation of gaps 72, 74, and 76 for contact and deposition of contact material. Since these contacts are at a low level, it is appropriate to use tungsten (W) if they are being used for other contacts at this level. If poly is used at this level, poly contacts are suitable. For electrical interconnection, standard interconnect (Al or Cu) and inter-level dielectrics (ILD) processes can be used. Aluminum interconnect structures may be formed from adhesive refractory metals (eg TiN), refractory metals (eg Ti, TiNi, Co) and to provide adhesion, diffusion barriers and good conductivity. It may be composed of an aluminum structure. The copper interconnect structure may consist of an adhesive film (eg, TaN), a fusion metal (eg, Ta), and a copper interconnect. Typically for Cu interconnect structures, the structures are formed using a single damascene or dual damascene process. High melting point refractory metals can be used for ESD and resistance ballasting in these structures.

An advantage of the gate in this FIN-Diode structure shown in FIG. 4 is that the current in the gated p + / n− / n + structure can be modulated by electrical control of the gate structure. Thus, leakage, bias and electrical stress can be modulated by the connection of the gate structure to the anode or cathode node, ground plane or power supply, voltage or current reference circuit, or electrical network. The disadvantage of the gate is that the gate insulator can be damaged. The circuit designer will make a choice based on a trade-off between benefits and weaknesses.

Several sets of FIN-Diode structures may be arranged in parallel to provide a low total series resistance, high total current carrying capacity, and a power-to-failure to high failure of the ESD structure. For example, both the anode and cathode connections may be such that they enable electrical connection of parallel FINFET diode structures. These parallel structures may or may not use the same gate electrode. In addition, personalization and customization of the number of parallel elements can be made based on ESD requirements or performance goals. Additionally, there may be resistor ballasting, and different gate biases may be set to provide a means for turning on or off the devices, or to enable improved current uniformity. Advantages of parallel elements compared to prior art devices are 1) three-dimensional capacitance, 2) improved current stability control and 3) improved current uniformity control. In a two-dimensional single finger lubricator structure, current uniformity is not inherent in the design and causes a weakening of the ESD robustness per micron unit of the cross-sectional area. In these structures, the heating of each FIN-Diode structure is isolated from the adjacent region. This prevents thermal coupling between adjacent regions to provide uniform thermal profile and ESD robustness uniformity within each FIN-Diode parallel device.

In addition, these FIN-Diode structures can be designed as p + / p− / n + devices or p + / n− / n + devices. Differences in metal joining positions make one embodiment superior to others for different purposes. This has been shown experimentally by the inventor and is a function of doping concentration and application. The choice will be influenced by the capacity-resistance trade-off and the implant availability for the FIN-Diode originally intended for some other application. When lower resistance is more suitable for near future purposes, and the available implants have a relatively low dose, p + / n− / n + structures are preferred because of their high electron mobility. Conversely, when the dose of the soluble implant is relatively high, the p + / p− / n + structure would be preferred.

Halo implants can be made in these devices to enable improved lateral conduction, better bond capacity and improved fracture properties. In this case, halo is preferably provided for only one doping polarity in order to prevent the formation of parasitic diodes by the wrong halo implant in the wrong polarity.

5 shows an alternative version of the FIN-Diode structures where the channel is doped with P ⁻ and without a separate gate. The advantage of this is that the gate is not exposed to ESD voltage stress. Electrical overstress in the gate dielectric can be eliminated by making the gate structure absent.

CDM failure mechanisms can occur because of the electrical connection of the gate structure for the FINFET ESD protection network. While the previous embodiment, including the gate, enables electrical control, the embodiment also required more design area and / or electrical connections for the electrical circuit. For this embodiment, fewer electrical connections are needed, allowing for higher density circuits.

In the embodiment of FIG. 5, a plurality of parallel FIN-Diode structures may be closely arranged to enable high ESD robustness per unit area. In addition, resistance stability and current uniformity control can be solved by changing the effective resistance in the individual FIN-Diode structures. With physical isolation of adjacent FIN-Diode structures, thermal coupling between adjacent devices can be reduced. Space optimization between adjacent devices can be ensured by appropriate spatial and nonuniform adjacent space conditions to provide optimal thermal results. This provides a thermal methodology that allows for optimization of the devices. This thermal methodology cannot be used in two-dimensional Lubistor devices, but is a natural methodology in the construction of parallel FIN-Diode structures.

Similarly, FIG. 6 shows a version in which the body is divided into two doped regions, namely a first P ⁻ and a second N ⁻ body region. This FIN-Diode structure enables the optimization and placement of metal junctions independent of the gate structure. This implant may be a p-well and / or n-well implant, or may be provided by a halo type implantation (eg, angled, twisted or straight) Or other known implant or diffusion process steps. The gradual profile introduced by the p + / p- and n + / n- conversions reduces abrupt junctions and can lead to improved ESD robustness.

Versions of devices with gates can be divided into several categories.

1) N ⁺ / P FIN-Gated diode with body in contact with substrate 10. In this case, a path exists to the substrate.

2) N ⁺ / P FIN-Gated diode with floating body on SOI.

3) N ⁺ / P FIN-Gated diodes on SOI with gates in contact with the (P ⁺ ) body allow dynamic control of the anode potential.

4) N ⁺ cathode SOI N ⁺ / P FIN-Gated on the diode with the gate in contact with.

In order to provide ESD protection to the FINFET device, it is also beneficial to provide resistive elements integrated with and / or not integrated into the FINFET devices.

Referring to FIG. 8, a FINFET device may be formed by similar techniques used in previous embodiments, and has a source and drain implant of the same polarity separated by a body of opposite polarity. The body is covered by a gate insulator 55 gate 155. This structure can be formed by symmetrical or asymmetrical implants to provide ESD advantages. Additionally, resistors can be coupled within the same structure to provide an ESD robust FINFET structure. By way of example, the second gate 155 ′ may be disposed in series with the drain structure where the second gate structure provides blocking of the heavily doped source / drain implants such that the slightly doped fins provide resistance. have. The gate structure serves two purposes. First, it provides a resistive region in the source or drain region. Secondly, it provides a means for preventing a salicide film placed in the source or drain region from shorting the resistance. This forms a "ballasting resistor" originally integrated with the FINFET. We will refer to this structure as a FIN-R-FET structure.

In addition, the second gate structure 155 ′ may be removed from the FIN-R-FET, as made in the FIN-Diode structure. Removal of the second gate structure after salicidation enables prevention of ESD issues or electrical overstress associated with the resistive element.

In addition, the device 150 used in the FIN-R-FET device may be configured as a self-standing resistor device. This is accomplished by placing n-channel FINFETs in n-well or n-body regions. This resistor or FIN-R device can be used to provide ESD robustness to FINFETs, FIN-Diodes, or for circuit applications. As previously discussed, the gate can be removed to prevent electrical overstress in the physical device.

Additionally, salicides can be removed from the source, drain and gate regions to improve the ESD robustness of the FIN-FET device. Because the gate length of the device is relatively small compared to planar devices, salicide can be removed from the gate region.

Referring now to FIG. 7, a schematic diagram of a schematic arrangement for protecting a circuit from ESD on terminal 51 is shown. Dotted lines indicated by numerals 72 and 74 represent the options discussed below. The two FIN-LUBISTORs according to the invention are connected between the protected node 53 and the voltage terminals 54 and 52 '. In this case, gate 60 is connected to terminal 54 such that an ESD event dynamically reduces the resistance of one of the diodes. Alternatively, terminals 60 may be connected to power supplies. To prevent electrical overstress into the gate structure, electrical circuits including FINFET devices can be used to electrically isolate the gate structure from electrical overstress. To provide electrical isolation from power supplies, electrical circuits with FINFET-based inverters or FINFET-based reference control networks set the potential to prevent overstress and to avoid leakage.

For use as an ESD network for human body models (HBMs), mechanical models (MMs), and other ESD events, multiple lateral FIN-Diode structures minimize the series resistance and eliminate the failure in a FIN-Diode device or circuit. It must be used in parallel so that a large amount of current can be discharged through. Since multiple parallel FIN-Diode devices are arranged, they are connected between the input pins and the power supplies.

For voltage tolerance, the ESD network shown in FIG. 7 is now comprised of FIN-Diode elements in series configuration, including the FIN-Diode 75 within the dashed line 72. The FIN-Diode structures may be configured such that a first FIN-Diode device anode is connected to a first pad and a cathode is connected to a second FIN-Diode anode. This may continue in line or in series configuration. For each step in the series, a plurality of parallel FIN-Diode elements can be placed for each "step" of the series of FIN-Diodes. These strings are between the input pad and the power supply, between two common power supply pads (eg, VDD1 and VDD1), and between any two dissimilar power supply pads (eg, VCC and VDD). May be disposed between any ground rails (eg, VSS1 and VSS2) and between any dissimilar ground rails (eg, VSS and VEE). These FIN-Diode series devices can be configured as a back-to-back configuration or as a single series string to allow bidirectional current flow between the two pads. For input pads to power supplies, typically, only a single FIN-Diode line will be present for unidirectional current flow.

For HBM and Charging Device Model (CDM) events, ESD circuits consisting of FIN-Diode devices, FIN-resistance (FIN-R) devices and FINFETs can be used to improve ESD results. 9 is an example of a circuit for providing ESD protection using FIN-Diode element 75, FIN-resistance 94 and FINFET 96 with a gate connected to ground. By way of example, the gate voltage of the FIN-Diodes is provided by the reference network, not by the ESD voltage itself. This allows better control of the current capacity of the diodes 75.

In addition, ESD protection can be provided using a resistor stabilized FIN-R-FET device. This circuit can be implemented in two ways. First, use a FIN-R resistor in series with the FINFET. To provide ESD protection, a plurality of parallel FIN-R resistors are placed in series with the plurality of FINFET devices. Another implementation may use multiple parallel FIN-R-FET structures for ESD protection. These structures described above can be arranged in a cascode configuration for higher snapback voltage or voltage tolerances. For ESD protection, as in the case of FIN-Diode devices, a series of steps of FINFETs with FIN-R resistor elements can be connected such that each step comprises a parallel set of devices.

Devices configured in accordance with the present invention are not limited to ESD use and may be used in traditional roles within circuitry such as digital, analog and radio frequency (RF) circuits. The invention is not limited to silicon wafers and other wafers such as SiGe alloys or GaAs that can be used. These structures can be disposed on a strained silicon film, using SiGe deposited or grown films. These structures are suitable for silicon on insulators (SOIs), RF SOIs, and ultra thin SOIs (TUSOIs).

While the invention has been described as one preferred embodiment, those skilled in the art will recognize that the invention may be practiced in various versions within the spirit and scope of the following claims.

The present invention is applicable to integrated circuit electronic devices and their manufacture.

Claims (14)

As a structure in an integrated circuit, Elongated vertical fin member comprising a semiconductor and having a thickness of 10 nm to 100 nm-the elongated vertical fin member protrudes from a bulk semiconductor substrate, the top and two opposite sides being opposite with elongated sides-, The first electrode is formed at the first end of the elongated vertical pin member, The second electrode of the opposite polarity to the first electrode is formed at a second end facing the first end of the elongated vertical pin member, Wherein the first and second electrodes are doped with an electrode concentration that is greater than a dopant concentration in the central portion between the first and second electrodes. The method of claim 1, One of the electrodes is doped with p ⁺ and the other of the electrodes is doped with n ⁺ . Claim 3 was abandoned when the setup registration fee was paid. The method of claim 1, Wherein one of the electrodes is doped with p ⁺ , the central portion is doped with p ⁻ , and the other of the electrodes is doped with n ⁺ . The method of claim 2, A first sub-portion of the central portion adjacent to the first electrode is doped with the same polarity and at a lower concentration as the first electrode, and the second portion of the central portion adjacent to the second electrode is the second electrode. A doped structure with the same polarity and at a lower concentration. Claim 5 was abandoned upon payment of a set-up fee. The method of claim 2, The dopant in (dopants) are p ⁺ / p ^- the structure arranged in a / n ⁺ sequence ^- / n. The method of claim 1, A gate close to the centers of the two sides and disposed above the center of the top surface, The gate is separated from the vertical member by a dielectric gate layer. An electrostatic discharge protection circuit (ESD) attached to an external terminal of an integrated circuit and comprising the structure according to claim 1. The method of claim 7, wherein Two more devices, And the external terminal is connected to the positive electrode of the first device and the negative electrode of another device. The method of claim 7, wherein The substrate is an SOI substrate having a layer of buried insulator, and the vertical fin member is disposed directly on the buried insulator layer. Claim 10 was abandoned upon payment of a setup registration fee. The method of claim 7, wherein The substrate is a bulk substrate, and the vertical member is disposed directly on the bulk substrate. The method of claim 7, wherein ESD protection circuitry comprising a plurality of FIN-Diode structures connected in parallel between an external terminal and a voltage terminal. The method of claim 7, wherein ESD protection circuitry that includes at least one FIN-Diode structure in series between two external terminals. The method of claim 7, wherein ESD protection circuitry comprising at least one FIN-Diode structure and at least one FIN-R resistive element. Claim 14 was abandoned when the registration fee was paid. The method of claim 7, wherein ESD protection circuitry comprising at least one FIN-Diode structure, at least one FIN-R resistive element and at least one FINFET element.

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