JP2006510125A5 - - Google Patents

Claims (21)

A reconfigurable computer system including a pipelined loop structure of control flow data flow, the system comprising :
A multi-adaptive processor, wherein the multi-adaptive processor includes a field programmable gate array;
Including a multi-adaptive processor compiler capable of generating code executable on a multi-adaptive processor, wherein the multi-adaptive processor compiler generates code that forms a pipelined loop structure and the pipelined The loop structure is
A loop body that processes input values and generates output values in successive iterations of the loop body, wherein the output values are captured by a circular node coupled to the loop body, the structure further comprising:
A loop valid node coupled to the loop body to determine a final loop iteration;
And an output value storage node coupled to the circulation node, said output value storing node ignores the output value of the loop valid node is generated after determining that loop iterations of the final ensued, the final A reconfigurable computer system that stores final loop values based on loop iterations.   The pipelined loop structure of claim 1, wherein the loop valid node outputs a loop valid end signal upon determining that the final loop iteration has occurred.   3. The pipelined loop structure of claim 2, wherein the loop valid node outputs the loop valid end signal at each loop iteration until the loop is resumed after the final loop iteration occurs.   The pipelined loop structure of claim 2, wherein the loop valid end signal includes a data bit.   The pipelined loop structure of claim 1 including an end node coupled to the loop valid node and the output value storage node.   6. The pipelined loop structure of claim 5, wherein the end node includes an end input for receiving a loop valid end signal from the loop valid node.   7. The pipelined loop structure of claim 6, wherein the end node includes an end output for sending a storage node end signal to the output value storage node.   The pipelined loop structure of claim 1 including a loop driver node coupled to the circular node, wherein the loop driver node sets a period for each iteration of the loop body.   The pipelined loop structure of claim 8, wherein clock latency is based on a period value input to the loop driver node. A reconfigurable computer system including a multi-adaptive processor and a multi-adaptive compiler, wherein the multi-adaptive compiler is capable of converting high-level instructions into code that can be executed by the multi-adaptive processor. Including instructions for forming a lined loop structure, the pipelined structure comprising :
A loop body that processes input values and generates output values in successive iterations of the loop body, wherein the output values are captured by a circular node coupled to the loop body, the structure further comprising:
A loop driver node coupled to the circular node, wherein the loop driver node sets a period for each iteration of the loop body, so that one or more clock periods are generated by the loop body at a second input value. A reconfigurable computer system that elapses before processing and wherein the loop drive node outputs a signal associated with a functional unit having a state .   The pipelined loop structure of claim 10, wherein the loop driver node outputs a CIRC_TRIGGER signal to inform the circular node that a loop has started. The pipelined loop structure of claim 10, wherein the loop driver node outputs a START signal for triggering the start of a loop. The pipelined loop structure of claim 10, wherein the loop driver node outputs a LOOP_STARTING signal for clearing a state of a node that requires a reset pulse.   The pipelined loop structure of claim 10, wherein the loop driver node outputs a LEADING signal to tell a periodic input node to load a value.   The pipelined loop structure of claim 10, wherein a period value is equal to a period of a longest scalar cycle carried in the pipelined loop structure.   The pipelined loop structure of claim 10, wherein the period is based on a period value input to the loop driver node.   The pipelined loop structure of claim 10 including a loop valid node coupled to the loop body to determine a final loop iteration.   18. The pipelined loop structure of claim 17, wherein the loop valid node outputs a loop valid end signal upon determining that the final loop iteration has occurred.   The pipelined loop structure of claim 18 including an output value storage node coupled to the circular node.   20. The pipelined loop structure of claim 19, wherein the output value storage node ignores output values generated after the loop valid node determines that the final loop iteration has occurred.   21. The pipelined loop structure of claim 20 including an end node coupled to the loop valid node and the output value storage node.