JP4330582B2 - Pipelined loop structure by MAP compiler - Google Patents

Description

CROSS REFERENCE TO RELATED PATENT APPLICATIONS This invention is a SRC Computers, Inc. of Colorado Springs, Colorado, the assignee of the present invention. U.S. Patent Application Serial No. 10 / 285,299, filed October 31, 2002, for assigning a high-level programming language program to a unified executable program for a hybrid computing platform. Including subject matter related to the subject matter of “Process For Converting Programs In High-Level Programming Languages To A Unified Executable For Hybrid Computing Platforms”, the disclosure of which is incorporated herein by reference.

Copyright Notice / Permission Part of the disclosure of this patent document includes material that is subject to copyright protection. The copyright owner does not object to any reproduction of the patent document of the patent disclosure as it appears in the US Patent and Trademark Office patent file or patent record, but otherwise holds any copyright. The following displays apply to the software and data described below, including the drawings, where applicable. (C) 2002 SRC Computers, Inc.

Background of the Invention
The present invention relates to pipelined loop structures created by reconfigurable hardware compilers. More specifically, the present invention relates to the compilation of pipelined loop structures having loop cycles that vary in number and clock latencies that vary in length.

Related background instruction processors are increasingly being used in computer-intensive computations that were once done exclusively by supercomputers, as processing power continues to improve rapidly. However, there are still computer intensive tasks that are not yet practical to perform with today's instruction processors, including, for example, computer intensive image processing and hydrodynamic simulation.

  Reconfigurable computation is a technology that is gaining more and more attention among computational technologies. Traditional general purpose computing is characterized by computer code that is executed sequentially on one or more general purpose processors. Reconfigurable computation is characterized by programming reconfigurable hardware, such as a field programmable gate array (FPGA), to perform logic routines.

  Reconfigurable computations provide significant performance advancements in computer intensive processing. For example, reconfigurable hardware can be programmed with a logical configuration that has more parallel processing and pipelining characteristics than conventional instruction processors. Furthermore, the reconfigurable hardware can be programmed with custom logic configurations that are very efficient to perform tasks assigned by the program. Furthermore, sharing the program processing requirements between the instruction processor and reconfigurable hardware can improve the overall processing power of the computer.

  For example, a software program written in a high-level language such as C or Fortran can be converted to software executable on reconfigurable hardware with a MAP compiler. The loop structure of the high-level language can be converted by the MAP compiler into a format that exhibits reconfigurable hardware parallel processing and pipelining characteristics.

  Unfortunately, existing MAP compilers, among other requirements, have all loop structures that have a predetermined number of loop iterations before the loop ends and that have a loop period of one clock. Only works for a small subset. Therefore, there is still a need for a compiler that can compile loop structures such that the loop does not end after a predetermined number of iterations and the loop has a period greater than one clock.

SUMMARY OF THE INVENTION Accordingly, one embodiment of the present invention is a pipelined loop structure of a control flow data flow graph that processes input values and generates output values in successive iterations of the loop body. Including the loop body, the output value is captured by a circular node coupled to the loop body, and the above structure is further coupled to the loop body to determine the final loop iteration, coupled to the loop body, and to the circular node. The output value storage node ignores output values generated after the loop valid node determines that the final loop iteration has occurred.

  Other embodiments of the present invention include a pipelined loop structure of a control flow data flow graph that includes a loop body that processes input values and generates output values in successive iterations of the loop body; The output value is captured by a circular node that is coupled to the loop body and further includes a loop driver node that is coupled to the circular node, the loop driver node occurring between periods of execution, ie two consecutive loop iterations. Set the number of clocks for the loop.

  Additional novel features will be set forth in part in the description which follows, and in part will be apparent to those of ordinary skill in the art upon review of the following specification, or may be learned by practice of the invention. . The features and advantages of the invention will be realized and attained by means of the instructions, combinations and methods particularly pointed out in the appended claims.

Detailed Description of the Invention In a simple loop function, the loop repeats a fixed scheduled number of times and then stops after the final loop iteration. In contrast, a more complex loop function may repeat an unpredictable number of times until a condition is met, rather than exiting after a fixed number of iterations. These more complex loop functions continue to run after the final loop iteration, which makes it difficult for the output storage node to capture the final loop iteration output value, not the output following the closing price.

The present invention includes a pipelined loop structure and a loop pipelining method that includes a loop function that repeats an unpredictable number of times until a condition is met. One embodiment of the present invention includes a loop valid node that receives information generated for each loop iteration and determines whether the information indicates a final loop iteration. For example, the information generated for each loop iteration is processed by the loop valid node to determine whether a condition requesting the end of the loop has been met. When the condition is met, the loop valid node can inform other nodes, such as the end node and output value storage node, that the next output value from the loop is the final loop iteration output value.

  Many pipelined loop functions further require a period greater than one clock per iteration. These loop functions may not be compatible with pipelined loop structures that operate only at a frequency of one input value or one output value per clock cycle. In the present invention, a loop driver node is provided that can adjust the period so that one or more clock cycles elapse between values entered into the loop body. In one embodiment of the invention, the loop driver node accepts a period value “D”, where the D value represents the number of clock cycles that elapse between the input and / or output of the loop function.

  Referring to FIG. 1, one embodiment of a pipelined loop structure 100 according to the present invention is shown. Pipelined loop structure 100 begins at start node 102 that signals load scalar nodes 104 and 106 and loop driver node 108 to begin execution of the loop function. The loop driver node 108 then signals the circular nodes 110, 112, 114 to load the initial values from the load scalar nodes 104 and 106 and indicate the values to the loop body 116. At each iteration of the loop body 116, the circular nodes 110, 112, 114 capture the output values generated at each iteration of the loop body 116 and send them as input values for the next iteration of the loop body 116. prepare.

  As described in further detail below, the loop driver node 108 can accept an input labeled “D”, where the D value represents the number of additional clock cycles that occur during the loop iteration. For example, if D = 0, there are 1 clock cycle per iteration, and if D = 1, there are 2 clock cycles per iteration.

  The D value may be fixed for all iterations of the loop function, or may vary between loop iterations in more complex loop function operations. The D value may be entered manually by the programmer or automatically calculated based on the analysis of the loop function. When the loop function is initiated, the loop driver node 108 uses the D value to determine the rate at which other nodes, such as the circular nodes 110, 112, 114, in the pipelined loop structure 100 are active.

  The end of the loop in the pipelined loop structure 100 can be initiated by a loop valid node 118 connected to the circulation node 114. In one embodiment, a loop end signal, which can be represented by a single bit value, is input to the loop valid node 118 to determine whether a condition for instructing the end of the loop is satisfied. The loop valid node 118 can send an “invalid” output signal (also referred to as a “false” signal) to the circular node 114 and latch itself into a state where it continues to send the invalid output signal until the loop function is resumed.

  After circular node 114 receives an invalid output signal from loop valid node 118, the signal is passed to end node 120. The end node 120 is then ready to trigger the output value storage nodes 122, 124 to capture the final loop iteration output value from the final loop iteration of the loop body 116. This mechanism allows the output value storage nodes 122 and 124 to capture the final loop iteration output value even if the loop continues to free run after the final iteration.

When the loop is finished and the final loop iteration output values are stored in the output value storage nodes 122, 124, those values are subsequently latched by the latch and node 126 and then distributed via the output node 128. . In the pipelined loop structure 100, the end node 120 is further coupled to a latch and node 126 to provide output value storage nodes 122,
Node 126 can be informed of when to capture the value from 124.

  Referring to FIG. 2, a timing diagram of timing signals that may be included in the loop driver node 108 of FIG. 1 is shown. The CLOCK signal is an input provided by the system clock signal that triggers the start of a clock cycle. The START signal triggers the start of the loop. This signal is received from the start node 102. The CIRC_TRIGGER signal informs the circular node that the loop has started. This signal is an output that the circular nodes 110, 112, 114 use to load the initial value. The LOOP_STARTING signal tells the node that needs a reset pulse to clear the state for a new loop execution. The LEADING signal tells the periodic input node to load the initial value. Finally, the ACTIVE_LAST signal goes high at the last clock of each iteration. This signal is used to indicate to the node that the node of the pipelined loop structure 100 has a valid input.

  Loop-carried scalar variables can generate periods in the pipelined loop structure of the control flow data flow. The period increases the number of clock cycles between loop iterations, which in turn increases the D value, ensuring that the loop body and the circular node are synchronized to ensure that the correct loop body output value is captured and each new loop iteration is started. It needs to be possible.

  FIG. 3 shows an example of a portion of a pipelined loop structure 300 where the D value of the loop driver node 308 must be set to 4 representing at least 4 additional clock cycles per loop iteration. Similar to FIG. 1 above, the pipelined loop structure 300 begins with a start node 302 that signals the load scalar nodes 304 and 306 and the loop driver node 308. In this example, a value of D = 4 is input to the loop driver node 308 to set the frequency of the loop structure to 5 clock cycles per loop iteration. The value of D = 4 is selected based on the inherent clock cycle latency of the multiplication macro that is embodied at the MULT node 314. By inputting D = 4 to the loop driver node 308, the circular nodes 310 and 312 input a value to the MULT node 314 every five clock cycles.

  In general, the D value is proportional to the longest path between the input and output of the circular node in the pipelined loop structure. FIG. 3 shows a simple example in which all the outputs of the circular nodes 310 and 312 are sent to the MULT node 314 and the inputs are sent directly back to the nodes 310 and 312 by the MULT node 314. Here are some examples of more complex loop functions and their pipelined loop structures:

  FIG. 4 illustrates a control where there is a first function (F1) node 414 having a latency of 4 clock cycles per loop iteration and a second function (F2) node 416 having a latency of 6 clock cycles per loop iteration. Fig. 5 shows a pipelined loop structure 400 of a flow data flow graph. Pipelined loop structure 400 begins at start node 402 that signals load scalar nodes 404 and 406 and loop driver node 408. In this example, the D value is selected based on the longest latency among the loop functions in the pipelined loop structure 400. The second function (F2) node has a longest latency of 6 clock cycles per iteration, so the D value is 6. The circular nodes 410, 412 receive signals from the loop driver that is timed based on the D value, so that the value is sent every seven clock cycles to the first function (F1) node 414 and the second function (F2) node. Input to 416.

FIG. 5 shows a more complex pipe with many circulation paths between the circular nodes 516, 518, 520, 522, 524 and the loop function bodies 526, 528, 530, 532, 534, 536, 538, 540. A lined loop structure 500 is shown. In this example, execution of loop function 500 begins at start node 502 that signals load scalar nodes 504, 506, 508, 510, 512 and load driver node 514. The D value input to the loop driver node 514 can be determined in the following manner.

  Pipelined loop structure 500 has circular nodes that can be divided into nodes that are related to the cycle and nodes that are not related to the cycle. For a circular node associated with a cycle, the circular path in a pipelined loop structure can be described as follows.

1. C1 → D1 → D6 → C1
2. C1 → D0 → D6 → C1
3. C1->D2->C2->C3->D4->D6-> C1
Here, C0, C1, C2, C3 and C4 are the labels of the circulating nodes 516, 518, 520, 522 and 524, respectively, and D0, D1, D2, D3, D4, D5, D6 and D7 are loop function nodes. 526, 528, 530, 632, 534, 536, 538 and 540, respectively.

  In determining the D value, circular nodes not associated with a cycle may be ignored. This is because it is pushed into the loop body by inserting delays into all inputs of the node. In this example, the circular (C4) node 524 is not associated with a cycle of the pipelined loop structure 500 and is ignored in determining the D value.

  For the remaining cyclic (C0, C1, C2, C3) nodes 516, 518, 520, and 522, a table such as Table 1 shown in FIG. 6 is created, and the value is changed from one cyclic node to another cyclic node. To indicate which loop function body to go to or return to the same circular node. For example, cells C0 and C0 specify the loop function body that the value must pass before exiting from the cycle (C0) node 516 and returning to its original position. In the pipelined loop structure 500, C0 has no circulation path back to its original position, and the cell is left empty. In contrast, there is a circular path through which the value can be taken to exit the circular (C1) node 518 and return to its original position, which is represented by D1 + D6 in cells C1, C1.

  Clock latencies are determined for each of the loop function bodies D0 to D6, and these latencies are applied to Table 1 to determine the circular path having the longest latency. The minimum value of D is then set using the longest latency value and the minimum value is input to the loop driver node 514 to determine the overall period of the pipelined loop structure 500.

Node with state: In the pipelined loop structure of the control flow data flow, clear the state of the node, tell the node when each iteration occurs, and tell the node when the node input is valid Stateful nodes need additional support to handle problems with stateful nodes, such as telling. FIG. 7 shows how the three signals of the loop driver node 708 can be used to convey this information.

The example pipelined loop structure 700 shown in FIG. 7 looks similar to other pipelined loop structure examples, except for the presence of stateful nodes 716. The loop function is executed by having the load scalar nodes 704 and 706 and the loop driver node 708 signal from the start node 702. While the loop driver node 708 sends an activation signal to the circulation nodes 710, 712, 714 at a speed determined by the period of the loop, the load scalar nodes 704, 706 load the circulation nodes 710, 712, 714 with initial values. The circular nodes 710, 712, 714 are coupled to one or more loop bodies (not shown), which in turn are coupled to a node 716 having a state.

  As described above, three signals are provided by loop driver node 708 to convey information to stateful node 716. The first of these is called the “valid” signal and arrives at a node 716 having a state by a circular node 714 coupled to the loop driver node 708. The valid signal can also go through a conditional expression if the stateful node is in the conditional expression.

  Depending on how the condition is constructed in the loop function, the valid signal may be ignored from the stateful node 716. Rather than placing the node in a conditional test, the valid signal may be ignored if the condition of the stateful node is handled by giving the node an explicit predicate input. Illustratively, consider two ways to handle an accumulator to sum all the values of an array greater than 42.

  Compare with:

In the second approach, the loop structure built by the compiler is simpler because there is no need to build a conditional data flow. Furthermore, in the first approach, a value is assigned to “res” only when the conditional expression is true, whereas in the second approach, a value is assigned to “res” at each iteration. Thus, when the accumulator is built by the second approach, no valid signal input to the stateful node is necessary and the signal may be ignored. If a valid signal is desired, the stateful node may be designed with a 1-bit input to accept the signal.

The second signal for stateful node 716 is a “starting” signal used to clear the internal state of the node. This signal may be generated by the loop driver 708 at the loop_startings output. If the signal from the loop driver 708 is delayed before reaching the stateful node 716, the stateful node 716 is not connected to the “code_block_reset” signal of the code block. Because when the loop enters the code block, it may continue to free run from the previous execution of the block, and if the "code_block_reset" signal has not been delayed, the node resets by using the "code_block_reset" signal, This is because there is a possibility that processing of values still occurring due to the previous execution of the code block may be started.

  The third signal input to stateful node 716 is the signal that goes high in the last clock cycle in each loop iteration. This signal may originally originate from the loop driver node 708 as an “active_last” signal. When the stateful node 716 sees this signal go high, it assumes that there is valid data at the input.

  Normally, a node 716 having a state is independent of the loop end. When the loop termination condition is met, the corresponding result is captured and the loop continues to run. However, there may be cases where the stateful node 716 has to hold that state until the next time the code block of the loop is executed, and the node needs to know when the loop has finished. In this case, the macro uses the “valid” input and does not reset when the “starting” signal is seen. This is because the state is to be held during the code block call.

  FIG. 8 shows an example of a timing diagram of signals that can be used for stateful node 716. In this example, the “valid” signal is high during the first iteration. This is because the loop is a bottom test loop that performs at least one iteration. Thereafter, a high “valid” signal indicates that if the loop has not yet terminated and the node is in condition, the conditional branch is taken. The “starting” signal goes high for one clock before the loop begins and can be used to clear the state of the stateful node 716. The “active_last” signal goes high on the last clock cycle in each loop iteration and continues this operation even after the loop is finished. Data input to stateful node 716 is assumed to be valid when the “active_last” signal is high.

  The “leading” signal provides proper synchronization to the periodic input node. Some nodes cannot accept a new input every clock cycle. For example, some integer multiplications can only accept inputs every 3 clocks using a single on-chip multiplier. This problem is orthogonal to the latency problem, which is the number of clock delays between the set of inputs and the corresponding output. If a node cannot accept an input every clock, it must be put in a correctly tuned state, and there must be a synchronization that establishes when the node receives a new input. This is a function given by the “leading” signal and can be connected to the “valid in” input of such a node. The D value of the loop driver node must also be set to delay the loop at least enough to allow the periodic input node to operate correctly.

  There are at least two types of nodes that may be used in the present invention. In one type, node latency is constant regardless of the loop iteration period (ie, regardless of the value of the D input to the loop driver node). In other types, the latency of stateful nodes varies based on the loop repetition period. For example, a node that has a state that receives N data items before it starts generating output consumes more clock cycles before the first result is generated if the loop is slowed by the loop driver node. . This kind of behavior of the node that maintains state is specified by its information file entry. The node writer chooses to write a node with such a state, makes the node function correctly only if the loop does not slow down, ie D = 0, and the node's information file entry You must identify the facts.

  As used in this specification and the appended claims, the terms “comprising”, “comprising”, “including”, and “included” identify the presence of the described feature, completeness, component, or step. It is intended that this is not to exclude the presence or addition of one or more other features, completeness, components, steps or groups.

FIG. 6 illustrates an example of a pipelined loop structure of a control flow data flow graph according to an embodiment of the present invention. FIG. 6 is an example timing diagram for a loop driver node with 2 clock cycles between loop iterations. FIG. 5 is a diagram illustrating an example of a pipelined loop structure of a control flow data flow graph having a loop with a scalar cycle carried by the loop. FIG. 7 illustrates an example of a pipelined loop structure of a control flow data flow graph having a loop with a loop-carrying scalar cycle using two or more circular nodes. FIG. 6 illustrates an example of a pipelined loop structure of a control flow data flow graph having many loop-carried scalar cycles. It is a figure which shows the example of the chart showing the path | route between circulation nodes of the loop structure shown by FIG. FIG. 6 is a diagram illustrating an example of a pipelined loop structure of a control flow data flow graph including nodes having states. It is a figure which shows the example of the timing diagram of the node macro which has a state.

Claims (21)

A reconfigurable computer system including a pipelined loop structure of control flow data flow, the system comprising:
A multi-adaptive processor, wherein the multi-adaptive processor includes a field programmable gate array;
Including a multi-adaptive processor compiler capable of generating code executable on a multi-adaptive processor, wherein the multi-adaptive processor compiler generates code that forms a pipelined loop structure and the pipelined The loop structure repeats after the final condition is met, and the pipelined loop structure is
A loop body that processes input values and generates output values in successive iterations of the loop body, wherein the output values are captured by a circular node coupled to the loop body, the structure further comprising:
A loop valid node coupled to the loop body to determine a final loop iteration;
An output value storage node coupled to the cyclic node, the output value storage node storing a last output value , the last output value being latched for distribution, the output value storage node continuing Ignoring the output value generated after the loop valid node determines that the final loop iteration has occurred, storing the final loop value based on the final loop iteration, and the loop structure further comprising:
Reconfigurable , including a loop driver node for adjusting the period for each iteration of the loop body such that one or more clock cycles elapse between values entered into the loop body Computer system.   The pipelined loop structure of claim 1, wherein the loop valid node outputs a loop valid end signal upon determining that the final loop iteration has occurred.   3. The pipelined loop structure of claim 2, wherein the loop valid node outputs the loop valid end signal at each loop iteration until the loop is resumed after the final loop iteration occurs.   The pipelined loop structure of claim 2, wherein the loop valid end signal includes a data bit.   The pipelined loop structure of claim 1 including an end node coupled to the loop valid node and the output value storage node.   6. The pipelined loop structure of claim 5, wherein the end node includes an end input for receiving a loop valid end signal from the loop valid node.   7. The pipelined loop structure of claim 6, wherein the end node includes an end output for sending a storage node end signal to the output value storage node. Before Symbol loop driver node is coupled to the circulation node, pipelined loop structure of claim 1.   The pipelined loop structure of claim 8, wherein clock latency is based on a period value input to the loop driver node. A reconfigurable computer system including a multi-adaptive processor and a multi-adaptive compiler, wherein the multi-adaptive compiler is capable of converting high-level instructions into code that can be executed by the multi-adaptive processor. Including instructions for forming a lined loop structure, wherein the pipelined loop structure repeats an unpredictable number of times after a final condition is satisfied, and the pipelined structure Is
A loop body that processes input values and generates output values in successive iterations of the loop body, wherein the output values are captured by a circular node coupled to the loop body and the final condition is met In response to the output value being latched and distributed to the output node, the subsequent output value is ignored, and the structure further comprises:
Including a loop driver node coupled to the circular node, wherein the loop driver node sets a period for each iteration of the loop body, so that one or more clock periods have the loop body set to a second input value. A reconfigurable computer system that passes before processing and the loop drive node outputs a signal associated with a functional unit having a state.   The pipelined loop structure of claim 10, wherein the loop driver node outputs a CIRC_TRIGGER signal to inform the circular node that a loop has started.   The pipelined loop structure of claim 10, wherein the loop driver node outputs a START signal for triggering the start of a loop.   The pipelined loop structure of claim 10, wherein the loop driver node outputs a LOOP_STARTING signal for clearing a state of a node that requires a reset pulse.   The pipelined loop structure of claim 10, wherein the loop driver node outputs a LEADING signal to tell a periodic input node to load a value.   The pipelined loop structure of claim 10, wherein a period value is equal to a period of a longest scalar cycle carried in the pipelined loop structure.   The pipelined loop structure of claim 10, wherein the period is based on a period value input to the loop driver node.   The pipelined loop structure of claim 10 including a loop valid node coupled to the loop body to determine a final loop iteration.   18. The pipelined loop structure of claim 17, wherein the loop valid node outputs a loop valid end signal upon determining that the final loop iteration has occurred.   The pipelined loop structure of claim 18 including an output value storage node coupled to the circular node.   20. The pipelined loop structure of claim 19, wherein the output value storage node ignores output values generated after the loop valid node determines that the final loop iteration has occurred.   21. The pipelined loop structure of claim 20 including an end node coupled to the loop valid node and the output value storage node.

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