JP2006501546A - 統合ディレクトリとプロセッサキャッシュを備えたコンピュータシステム - Google Patents
統合ディレクトリとプロセッサキャッシュを備えたコンピュータシステム Download PDFInfo
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- JP2006501546A JP2006501546A JP2004540279A JP2004540279A JP2006501546A JP 2006501546 A JP2006501546 A JP 2006501546A JP 2004540279 A JP2004540279 A JP 2004540279A JP 2004540279 A JP2004540279 A JP 2004540279A JP 2006501546 A JP2006501546 A JP 2006501546A
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- Prior art keywords
- cache
- directory
- computer system
- cache memory
- block
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0817—Cache consistency protocols using directory methods
- G06F12/082—Associative directories
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/25—Using a specific main memory architecture
- G06F2212/251—Local memory within processor subsystem
- G06F2212/2515—Local memory within processor subsystem being configurable for different purposes, e.g. as cache or non-cache memory
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Multi Processors (AREA)
Abstract
Description
Claims (10)
- コンピュータシステムであって、
プロセッサコア(50)、および
前記プロセッサコアによりアクセス可能なデータを記録するキャッシュメモリサブシステム(52)を有し、前記キャッシュメモリサブシステムは、複数のエントリを有し、前記キャッシュメモリサブシステムの少なくともいくつかのエントリが、前記キャッシュメモリサブシステムの動作モードに応じて、グローバルコヒーレンスアクティビティを制御するために、プロセッサデータあるいはディレクトリ情報のどちらかを選択的に記録するように構成されている、コンピュータシステム。 - 前記プロセッサコア(50)及び前記キャッシュメモリサブシステム(52)が第一処理ノード(12A)の一部を形成し、かつ、前記第一処理ノードが第二処理ノード(12B)と結合され、かつ、前記第一処理ノードが更に第一システムメモリ(14A)を含み、かつ前記第二処理ノードが第二システムメモリ(14B)を含む、請求項1記載のコンピュータシステム。
- 前記ディレクトリ情報が、前記第一システムメモリ内にマップされた、アドレス位置に対応するデータのキャッシュコピーが、ノードに存在するかどうかを示す、請求項2記載のコンピュータシステム。
- 前記ディレクトリ情報が、前記キャッシュコピーがModified、Exclusive、あるいは、Owned状態にあるかどうかを示す、請求項3記載のコンピュータシステム。
- 前記アドレス位置に対応する、前記キャッシュメモリサブシステム内のディレクトリエントリの不在が、前記データの前記キャッシュコピーが共有あるいは無効のどちらかであることを示す、請求項3記載のコンピュータシステム。
- 前記キャッシュメモリサブシステムの指定のウエイ(way)により、ディレクトリ情報の記録が選択的に可能にされる、請求項1記載のコンピュータシステム。
- 前記キャッシュメモリサブシステムの前記指定のウエイにより、モード記録ユニット(75)に記録される値に基づいて、ディレクトリ情報の記録が選択的に可能にされる、請求項6記載のコンピュータシステム。
- プローブコマンドが前記ディレクトリ情報に応じて一つ以上の処理ノード(12)へ選択的に送信される、請求項1記載のコンピュータシステム。
- 前記少なくともいくつかのエントリが、プロセッサデータあるいはディレクトリ情報を記録するかどうかをコントロールするために値を記録するために、モード記録ユニット(75)を更に有す、請求項1記載のコンピュータシステム。
- 前記キャッシュメモリサブシステムの所定のストレージラインが、複数のディレクトリエントリを含む、請求項1記載のコンピュータシステム。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/256,318 US6868485B1 (en) | 2002-09-27 | 2002-09-27 | Computer system with integrated directory and processor cache |
PCT/US2003/030880 WO2004029776A2 (en) | 2002-09-27 | 2003-09-18 | Computer system with integrated directory and processor cache |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006501546A true JP2006501546A (ja) | 2006-01-12 |
JP4237142B2 JP4237142B2 (ja) | 2009-03-11 |
Family
ID=32041767
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004540279A Expired - Fee Related JP4237142B2 (ja) | 2002-09-27 | 2003-09-18 | 統合ディレクトリとプロセッサキャッシュを備えたコンピュータシステム |
Country Status (8)
Country | Link |
---|---|
US (1) | US6868485B1 (ja) |
EP (1) | EP1543425A2 (ja) |
JP (1) | JP4237142B2 (ja) |
KR (1) | KR101014394B1 (ja) |
CN (1) | CN100357914C (ja) |
AU (1) | AU2003272795A1 (ja) |
TW (1) | TWI311707B (ja) |
WO (1) | WO2004029776A2 (ja) |
Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2008027435A (ja) * | 2006-06-29 | 2008-02-07 | Intel Corp | 排他的所有権のスヌープフィルタ |
JP2009134716A (ja) * | 2007-11-28 | 2009-06-18 | Internatl Business Mach Corp <Ibm> | マルチプロセッサ・データ処理システムにおいて共有キャッシュ・ラインを与える方法、コンピュータ読み取り可能な記録媒体及びマルチプロセッサ・データ処理システム |
JP2010097558A (ja) * | 2008-10-20 | 2010-04-30 | Toshiba Corp | 仮想アドレスキャッシュメモリ及び仮想アドレスキャッシュ方法 |
WO2010100679A1 (ja) | 2009-03-06 | 2010-09-10 | 富士通株式会社 | コンピュータシステム、制御方法、記録媒体及び制御プログラム |
WO2012035605A1 (ja) * | 2010-09-13 | 2012-03-22 | 富士通株式会社 | 情報処理装置および情報処理装置の制御方法 |
JP2012512491A (ja) * | 2008-12-30 | 2012-05-31 | インテル・コーポレーション | ハードウェアフィールドにロッシーなメタデータを保持するためのメタフィジカルアドレス空間 |
JP2012522290A (ja) * | 2009-03-27 | 2012-09-20 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | キャッシュにおけるウエイ割り当て及びウエイロックのための方法 |
JP2013546095A (ja) * | 2010-12-29 | 2013-12-26 | エンパイア テクノロジー ディベロップメント エルエルシー | ディレクトリベースのマルチコアアーキテクチャ上におけるキャッシュ状態の移動の加速 |
JP5435132B2 (ja) * | 2010-07-12 | 2014-03-05 | 富士通株式会社 | 情報処理システム |
US8725954B2 (en) | 2008-11-10 | 2014-05-13 | Fujitsu Limited | Information processing apparatus and memory control apparatus |
JP2014149859A (ja) * | 2009-12-30 | 2014-08-21 | Emprie Technology Development LLC | マルチコアプロセッサアーキテクチャにおけるデータ記憶およびアクセス |
JP2016015135A (ja) * | 2014-06-20 | 2016-01-28 | ブル・エス・アー・エス | キャッシュメモリ管理ディレクトリにおけるエビクションの低減 |
JP2017509985A (ja) * | 2014-03-26 | 2017-04-06 | アリババ・グループ・ホールディング・リミテッドAlibaba Group Holding Limited | データ処理のための方法及びプロセッサ |
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US7373466B1 (en) | 2004-04-07 | 2008-05-13 | Advanced Micro Devices, Inc. | Method and apparatus for filtering memory write snoop activity in a distributed shared memory computer |
US7797495B1 (en) | 2005-08-04 | 2010-09-14 | Advanced Micro Devices, Inc. | Distributed directory cache |
US7606981B2 (en) * | 2005-12-19 | 2009-10-20 | Intel Corporation | System and method for reducing store latency |
US7577795B2 (en) * | 2006-01-25 | 2009-08-18 | International Business Machines Corporation | Disowning cache entries on aging out of the entry |
US8527713B2 (en) | 2006-01-31 | 2013-09-03 | Qualcomm Incorporated | Cache locking without interference from normal allocations |
US7669011B2 (en) * | 2006-12-21 | 2010-02-23 | Advanced Micro Devices, Inc. | Method and apparatus for detecting and tracking private pages in a shared memory multiprocessor |
US7991963B2 (en) * | 2007-12-31 | 2011-08-02 | Intel Corporation | In-memory, in-page directory cache coherency scheme |
US8185695B2 (en) * | 2008-06-30 | 2012-05-22 | Advanced Micro Devices, Inc. | Snoop filtering mechanism |
US8364898B2 (en) * | 2009-01-23 | 2013-01-29 | International Business Machines Corporation | Optimizing a cache back invalidation policy |
US8868847B2 (en) * | 2009-03-11 | 2014-10-21 | Apple Inc. | Multi-core processor snoop filtering |
US8738863B2 (en) * | 2009-09-25 | 2014-05-27 | Intel Corporation | Configurable multi-level buffering in media and pipelined processing components |
US20120159080A1 (en) * | 2010-12-15 | 2012-06-21 | Advanced Micro Devices, Inc. | Neighbor cache directory |
CN103544269B (zh) * | 2013-10-17 | 2017-02-01 | 华为技术有限公司 | 目录的存储方法、查询方法及节点控制器 |
US10042773B2 (en) * | 2015-07-28 | 2018-08-07 | Futurewei Technologies, Inc. | Advance cache allocator |
US10255190B2 (en) | 2015-12-17 | 2019-04-09 | Advanced Micro Devices, Inc. | Hybrid cache |
US10019375B2 (en) * | 2016-03-02 | 2018-07-10 | Toshiba Memory Corporation | Cache device and semiconductor device including a tag memory storing absence, compression and write state information |
CN106776366B (zh) * | 2016-11-18 | 2019-11-22 | 华为技术有限公司 | 地址访问方法及装置 |
US10073783B2 (en) | 2016-11-23 | 2018-09-11 | Advanced Micro Devices, Inc. | Dual mode local data store |
US11119926B2 (en) | 2017-12-18 | 2021-09-14 | Advanced Micro Devices, Inc. | Region based directory scheme to adapt to large cache sizes |
CN110059026B (zh) | 2018-01-19 | 2021-06-29 | 华为技术有限公司 | 一种目录处理方法、装置及存储系统 |
US10705959B2 (en) | 2018-08-31 | 2020-07-07 | Advanced Micro Devices, Inc. | Region based split-directory scheme to adapt to large cache sizes |
US10922237B2 (en) | 2018-09-12 | 2021-02-16 | Advanced Micro Devices, Inc. | Accelerating accesses to private regions in a region-based cache directory scheme |
US11914517B2 (en) * | 2020-09-25 | 2024-02-27 | Advanced Micro Devices, Inc. | Method and apparatus for monitoring memory access traffic |
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2002
- 2002-09-27 US US10/256,318 patent/US6868485B1/en not_active Expired - Fee Related
-
2003
- 2003-09-18 AU AU2003272795A patent/AU2003272795A1/en not_active Abandoned
- 2003-09-18 CN CNB038231425A patent/CN100357914C/zh not_active Expired - Fee Related
- 2003-09-18 EP EP03754996A patent/EP1543425A2/en not_active Withdrawn
- 2003-09-18 WO PCT/US2003/030880 patent/WO2004029776A2/en active Application Filing
- 2003-09-18 JP JP2004540279A patent/JP4237142B2/ja not_active Expired - Fee Related
- 2003-09-18 KR KR1020057005293A patent/KR101014394B1/ko not_active IP Right Cessation
- 2003-09-25 TW TW092126444A patent/TWI311707B/zh not_active IP Right Cessation
Cited By (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008027435A (ja) * | 2006-06-29 | 2008-02-07 | Intel Corp | 排他的所有権のスヌープフィルタ |
JP2009134716A (ja) * | 2007-11-28 | 2009-06-18 | Internatl Business Mach Corp <Ibm> | マルチプロセッサ・データ処理システムにおいて共有キャッシュ・ラインを与える方法、コンピュータ読み取り可能な記録媒体及びマルチプロセッサ・データ処理システム |
JP2010097558A (ja) * | 2008-10-20 | 2010-04-30 | Toshiba Corp | 仮想アドレスキャッシュメモリ及び仮想アドレスキャッシュ方法 |
US8725954B2 (en) | 2008-11-10 | 2014-05-13 | Fujitsu Limited | Information processing apparatus and memory control apparatus |
JP2012512491A (ja) * | 2008-12-30 | 2012-05-31 | インテル・コーポレーション | ハードウェアフィールドにロッシーなメタデータを保持するためのメタフィジカルアドレス空間 |
WO2010100679A1 (ja) | 2009-03-06 | 2010-09-10 | 富士通株式会社 | コンピュータシステム、制御方法、記録媒体及び制御プログラム |
US8700863B2 (en) | 2009-03-06 | 2014-04-15 | Fujitsu Limited | Computer system having a cache memory and control method of the same |
JP2012522290A (ja) * | 2009-03-27 | 2012-09-20 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | キャッシュにおけるウエイ割り当て及びウエイロックのための方法 |
JP2014149859A (ja) * | 2009-12-30 | 2014-08-21 | Emprie Technology Development LLC | マルチコアプロセッサアーキテクチャにおけるデータ記憶およびアクセス |
JP5435132B2 (ja) * | 2010-07-12 | 2014-03-05 | 富士通株式会社 | 情報処理システム |
WO2012035605A1 (ja) * | 2010-09-13 | 2012-03-22 | 富士通株式会社 | 情報処理装置および情報処理装置の制御方法 |
JP2013546095A (ja) * | 2010-12-29 | 2013-12-26 | エンパイア テクノロジー ディベロップメント エルエルシー | ディレクトリベースのマルチコアアーキテクチャ上におけるキャッシュ状態の移動の加速 |
US9336146B2 (en) | 2010-12-29 | 2016-05-10 | Empire Technology Development Llc | Accelerating cache state transfer on a directory-based multicore architecture |
US9760486B2 (en) | 2010-12-29 | 2017-09-12 | Empire Technology Development Llc | Accelerating cache state transfer on a directory-based multicore architecture |
JP2017509985A (ja) * | 2014-03-26 | 2017-04-06 | アリババ・グループ・ホールディング・リミテッドAlibaba Group Holding Limited | データ処理のための方法及びプロセッサ |
JP2016015135A (ja) * | 2014-06-20 | 2016-01-28 | ブル・エス・アー・エス | キャッシュメモリ管理ディレクトリにおけるエビクションの低減 |
Also Published As
Publication number | Publication date |
---|---|
CN1685319A (zh) | 2005-10-19 |
KR101014394B1 (ko) | 2011-02-15 |
AU2003272795A8 (en) | 2004-04-19 |
US6868485B1 (en) | 2005-03-15 |
KR20050070012A (ko) | 2005-07-05 |
EP1543425A2 (en) | 2005-06-22 |
AU2003272795A1 (en) | 2004-04-19 |
JP4237142B2 (ja) | 2009-03-11 |
TW200406676A (en) | 2004-05-01 |
TWI311707B (en) | 2009-07-01 |
CN100357914C (zh) | 2007-12-26 |
WO2004029776A3 (en) | 2004-10-28 |
WO2004029776A2 (en) | 2004-04-08 |
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