JP2006352667A - Pseudo inductance circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a pseudo inductance circuit in which mass and volume reduction can be attained and any power source is not required. <P>SOLUTION: The pseudo inductance circuit comprises a circuit including a transistor Q1, two resistors R1 and R3 for determining its fixed bias condition and a capacitor C1 connected in parallel to the resistor R2, a circuit including a diode D1 for preventing a reverse current to the transistor Q1, and these two circuits are connected inversely to each other. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a pseudo-inductance circuit.

  As an inductance element used for improving the power factor of a commercial power supply network, a thick electric wire is used so that it can be applied to a large current. In order to prevent an increase in loss due to an increase in the number of windings, the electric wire may be wound around a thick core (iron core). Therefore, such an inductance element has a large mass and volume.

  Furthermore, even if high-frequency noise occurs in an environment such as a commercial power supply network, the power factor can be improved, and the mass and volume can be reduced. Application is expected. However, the pseudo-inductance circuit requires a power source for its operation and is not suitable for a high-power circuit.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a pseudo-inductance circuit that can reduce mass and volume and does not require a power source.

  In order to solve the above problems, the present invention of claim 1 is directed to a semiconductor element, two resistive elements connected to the semiconductor element to determine a fixed bias condition of the semiconductor element, and the resistive element Two circuits each including a circuit including a capacitive element connected in parallel to one of the semiconductor elements and a reverse current preventing semiconductor element connected in series to the circuit for preventing a reverse current to the semiconductor element, The solution is a pseudo-inductance circuit characterized in that the circuits are connected in opposite directions.

  According to a second aspect of the present invention, the semiconductor element is an N-channel MOSFET, one resistive element is connected in parallel between the drain and gate of the N-channel MOSFET, and the other resistive element and capacitive element are 2. The pseudo-inductance circuit according to claim 1, wherein the pseudo-inductance circuit is connected in parallel between a gate and a source of an N-channel MOSFET.

  According to the present invention, it is possible to provide a pseudo-inductance circuit that can reduce the mass and volume and does not require a power source.

Hereinafter, embodiments of a pseudo-inductance circuit according to the present invention will be described with reference to the drawings. [First Embodiment]
FIG. 1 is a circuit diagram of a pseudo-inductance circuit 1 according to the first embodiment.

  The terminal A and the anode of the diode D1 are connected, and the cathode of the diode D1 and the drain of the transistor Q1, which is a power type N-channel MOSFET, are connected. The source of the transistor Q1 and the terminal B are connected. A resistor R1 is connected in parallel between the drain and gate of the transistor Q1, and a resistor R2 and a capacitor C1 are connected in parallel between the gate and source of the transistor Q1.

  The terminal B and the anode of the diode D2 are connected, and the cathode of the diode D2 and the drain of the transistor Q2 which is a power type N-channel MOSFET are connected. The source of the transistor Q2 and the terminal A are connected. A resistor R11 is connected in parallel between the drain and gate of the transistor Q2, and a resistor R12 and a capacitor C2 are connected in parallel between the gate and source of the transistor Q2.

  Next, the operation of the pseudo inductance circuit 1 will be described.

  When the potential at the terminal A is higher than the potential at the terminal B, the diode D2 blocks the current that is about to flow to the transistor Q2, while charging of the capacitor C1 starts via the diode D1 and the resistor R1. At the beginning of charging, since the potential difference between both ends of the capacitor C1 is small and the gate-source voltage of the transistor Q1 is small, the bias of the transistor Q1 is shallow and the transistor Q1 is cut off. As the charging continues, the potential difference between both ends of the capacitor C1 increases, the voltage between the gate and the source of the transistor Q1 increases, that is, the bias of the transistor Q1 deepens, and a current starts to flow through the transistor Q1, and the current value is the resistance R1 And a value corresponding to the ratio of the resistor R2 (fixed bias condition).

  In this way, the current in the direction from the terminal A to the terminal B is transiently blocked and eventually flows.

  On the contrary, when the potential at the terminal B is higher, the diode D1 blocks the current that is about to flow to the transistor Q1, while the capacitor C2 starts to be charged via the diode D2 and the resistor R11. At the beginning of charging, since the potential difference between both ends of the capacitor C2 is small and the gate-source voltage of the transistor Q2 is small, the bias of the transistor Q2 is shallow and the transistor Q2 is cut off. As the charging continues, the potential difference between both ends of the capacitor C2 increases, the voltage between the gate and source of the transistor Q2 increases, that is, the bias of the transistor Q2 increases, and a current starts to flow through the transistor Q2. And the value corresponding to the ratio of the resistor R12 (fixed bias condition).

  In this way, the current in the direction from the terminal B to the terminal A is transiently blocked and eventually flows.

  That is, the pseudo-inductance circuit 1 can be used for a DC circuit and an AC circuit, and in either case, an operation is performed in which the current is transiently blocked and eventually flows.

[Second Embodiment]
FIG. 2 is a circuit diagram of the pseudo-inductance circuit 1A according to the second embodiment.

  The pseudo inductance circuit 1A is obtained by changing a part of the pseudo inductance circuit 1. In the pseudo-inductance circuit 1A, the collector of the output side phototransistor of the photocoupler PC1 is connected to the gate of the transistor Q1, the emitter of the output side phototransistor is connected to the source of the transistor Q1, and a pulse power source is connected between each input terminal of the photocoupler PC1. 11 is connected. In the pseudo-inductance circuit 1A, the collector of the output side phototransistor of the photocoupler PC2 is connected to the gate of the transistor Q2, the emitter of the output side phototransistor is connected to the source of the transistor Q2, and between the input terminals of the photocoupler PC2. A pulse power supply 21 is connected. By providing such a configuration, the pseudo-inductance circuit 1A does not include the resistor R2 and the resistor R12. Other parts are the same as those of the pseudo-inductance circuit 1.

  In the pseudo-inductance circuit 1A, by controlling at least one element among the amplitude, frequency, and duty ratio of the pulse signal applied from the pulse power supply 11 or the pulse power supply 21 to the photocoupler PC1 or the photocoupler PC2, the photocoupler PC1 or the photocoupler PC2 is controlled. Since the resistance value (output resistance) of the output side phototransistor can be changed, the fixed bias conditions of the transistor Q1 and the transistor Q2 can be changed. Therefore, the characteristics of the pseudo inductance circuit 1A can be changed. In the second embodiment, the same function and effect can be obtained even in a circuit in which one of the resistors R2 and R12 used in the first embodiment is left and a photocoupler and a pulse power supply are not provided in place of the resistor R2. can get. Further, a similar effect can be obtained whether or not a photocoupler and a pulse power supply that replace at least one of the resistor R1 and the resistor R11 are provided and the resistor R2 and the resistor R12 are replaced with the photocoupler and the pulse power supply. The waveform of the pulse signal applied to the photocoupler may be a waveform having an arbitrary shape such as a rectangular wave, a triangular wave, a trapezoidal wave, or a sawtooth wave. Further, a waveform obtained by combining these waveforms may be used.

[Third Embodiment]
FIG. 3 is a circuit diagram of a pseudo-inductance circuit 1B according to the third embodiment.

  The pseudo-inductance circuit 1B is obtained by replacing the pulse power source 11 and the pulse power source 21 of the pseudo-inductance circuit 1A with a sine wave signal power source 11a and a sine wave signal power source 21a that generate sine wave signals, respectively.

  In the pseudo-inductance circuit 1B, the photocoupler PC1 or the sine wave signal power source 11a or the sine wave signal power source 21a is controlled by controlling at least one of the amplitude, frequency, and DC component of the sine wave signal applied to the photocoupler PC1 and the photocoupler PC2. Since the resistance value (output resistance) of the output circuit of the photocoupler PC2 can be changed, the fixed bias conditions of the transistor Q1 and the transistor Q2 can be changed. Therefore, the characteristics of the pseudo inductance circuit 1A can be changed. In the third embodiment, the same operation can be achieved as a circuit in which one of the resistor R2 and the resistor R12 used in the first embodiment is left and a photocoupler and a sine wave signal power supply are not provided in place of the resistor R2. An effect is obtained. In addition, a photocoupler and a sine wave signal power supply that replace at least one of the resistor R1 and the resistor R11 are provided, and whether or not the resistor R2 and the resistor R12 are replaced with the photocoupler and the sine wave signal power supply can have the same operation effect. It is done.

  FIG. 4 is a characteristic diagram of the N-channel MOSFET prepared to show that the drain current can be controlled by the gate-source voltage obtained by dividing the source-drain voltage as described above. The characteristics of the drain-source voltage VDS with respect to the voltage VGS are shown.

  According to FIG. 4, when the voltage VGS is increased from 0V, the drain current ID starts flowing at a certain point. If the voltage VDS at this time is made higher than the voltage VGS, that is, if the hatched area in FIG. 2 is used, then a high transfer admittance (a value obtained by dividing the rate of change of the drain current ID by the rate of change of the voltage VGS). can get. Further, when the voltage VGS is lowered, the drain current ID does not flow at a certain point. Therefore, by changing the voltage VGS obtained by dividing the voltage VDS, the conduction / non-conduction and the magnitude of the current ID can be controlled.

  FIG. 5 is a diagram illustrating an example of an embodiment of the pseudo-inductance circuit according to each embodiment.

  The output side of the transformer 3 in the substation 2 and the terminal A of the pseudo-inductance circuit 1 provided in the substation 2 are connected. A terminal B such as the pseudo-inductance circuit 1 and a load 4 (inverter device, household electrical appliance, industrial machine, etc.) are connected via a power transmission line or an indoor wiring.

  The pseudo-inductance circuit 1 or the like prevents the malfunction of the load 4 due to this current by preventing the transient high-frequency noise current generated on the output side of the transformer 3 from being transmitted to the load 4 while being stationary. The current is supplied to the load 4 by conducting the current of the commercial frequency.

  Furthermore, since the pseudo-inductance circuit 1 or the like does not use inductance, the stored magnetic energy is not released or resonated.

  Although the pseudo-inductance circuit has been described above, an NPN bipolar transistor, a P-channel MOSFET, a PNP bipolar transistor, an IGBT (Insurated Gate Bipolar Transistor), a GTBT (Grounded trench mos structure assisted bipolar mode JFET) are used instead of the N-channel MOSFET. It may be used.

1 is a circuit diagram of a pseudo inductance circuit according to a first embodiment. FIG. It is a circuit diagram of the pseudo inductance circuit concerning a 2nd embodiment. It is a circuit diagram of the pseudo-inductance circuit which concerns on 3rd Embodiment. It is a characteristic view of N channel MOSFET used in order to show that drain current control is possible with the gate-source voltage which divided the source-drain voltage. It is a figure which shows an example of the embodiment about the pseudo-inductance circuit of each embodiment.

Explanation of symbols

1, 1A, 1B Pseudo inductance circuit 11, 21 Pulse power supply 11a, 21a Sinusoidal power supply Q1, Q2 Transistors R1, R2, R11, R12 Resistor C1, C2 Capacitor D1, D2 Diode (reverse current prevention semiconductor element)
PC1, PC2 Photocoupler

Claims (2)

Semiconductor elements,
Two resistive elements connected to the semiconductor element to determine a fixed bias condition of the semiconductor element;
And a circuit comprising a capacitive element connected in parallel to one of the resistive elements;
2 circuits comprising a reverse current prevention semiconductor element connected in series to the circuit for preventing reverse current to the semiconductor element,
A pseudo-inductance circuit, wherein the two circuits are connected in opposite directions.   The semiconductor element is an N-channel MOSFET, one resistive element is connected in parallel between the drain and gate of the N-channel MOSFET, and the other resistive element and capacitive element are the gate-source of the N-channel MOSFET. The pseudo-inductance circuit according to claim 1, wherein the pseudo-inductance circuit is connected in parallel.

Images