JP2006352302A - Multi-channel receiver - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multi-channel receiver with a low distortion characteristic over a wide frequency band. <P>SOLUTION: A decoder 11 separates composite data received from a microcomputer 9 into frequency setting data D<SB>n</SB>to D<SB>0</SB>and bias switching control data SW<SB>1</SB>, SW<SB>0</SB>. A switching control circuit 14 outputs switching control signals SWC1, SWC0 to bias switching circuits 15, 16 in response to the bias switching control data SW<SB>1</SB>, SW<SB>2</SB>. The bias switching circuit 15 switches a bias of an RF amplifier 4 to a desired value in response to the switching control signal SWC1. The bias switching circuit 16 switches the bias of a mixing circuit 5 to a desired value in response to the switching control signal SWC0. Thus, the multi-channel receiver can suppress secondary intermodulation distortion in response to a frequency of a received desired signal. Thus, the multi-channel receiver with the low distortion characteristic over the wide frequency band can be achieved. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a multi-channel receiver, and more particularly to a multi-channel receiver that receives a broadband and multi-channel television signal or data signal. More specifically, the present invention relates to a digital cable television broadcast tuner or a terrestrial digital broadcast tuner that requires low distortion characteristics over a wide frequency band, or a data receiver such as a cable modem.

  In recent years, with the progress of digitalization of television broadcasts and communications, there is a demand for television broadcast receivers that can receive broadband and multi-channel television signals, and cable modems for Internet connection using networks such as cable television. is increasing. For example, in digital cable television (hereinafter referred to as CATV) broadcasting in the United States, a 134-channel broadcasting service is provided using an RF (radio frequency) signal having a frequency band of 54 MHz to 864 MHz. The TV broadcast receiver that receives this digital CATV broadcast has low distortion characteristics, low noise characteristics, high suppression characteristics against interfering signals, flat deviation characteristics between channels, etc. in order to support multi-channel reception. It is requested. These characteristics depend on the performance of the tuner unit included in the television broadcast receiver. Here, the configuration and operation of a general tuner will be described.

  FIG. 15 is a block diagram showing a schematic configuration of a tuner of a conventional television broadcast receiver. In FIG. 15, the tuner includes an input terminal 100, bandpass filters 101 and 105, an automatic gain control circuit (AGC) 102, an RF amplifier 103, a mixing circuit 104, an IF amplifier 106, An output terminal 107, a microcomputer 108, a data bus 109, a frequency synthesizer 110, and a local oscillation circuit 111 are provided.

  The bandpass filter 101 receives an RF signal received by an antenna (not shown) via the input terminal 100, removes an unnecessary frequency band signal, and allows only a signal in a desired frequency band to pass. The automatic gain control circuit 102 converts the signal that has passed through the band-pass filter 101 to an appropriate level and outputs it while controlling the gain so that a constant level tuner output is always obtained. The RF amplifier 103 amplifies the output signal of the automatic gain control circuit 102 and supplies it to the mixing circuit 104. The mixing circuit 104 mixes the output signal of the RF amplifier 103 with the local oscillation signal from the local oscillation circuit 111 and converts the frequency into an IF (intermediate frequency) signal. The band pass filter 105 receives the IF signal from the mixing circuit 104 and passes only a signal in a desired frequency band. The IF amplifier 106 amplifies the signal that has passed through the band pass filter 105 and supplies the amplified signal to the output terminal 107.

  The microcomputer 108 provides frequency setting data to the frequency synthesizer 110 via the data bus 109. The frequency synthesizer 110 sets the oscillation frequency of the local oscillation circuit 111 according to the frequency setting data. The local oscillation circuit 111 gives a local oscillation signal to the mixing circuit 104. The frequency synthesizer 110 and the local oscillation circuit 111 constitute a phase locked loop circuit (PLL circuit). In general, in order to control the oscillation frequency of the local oscillation circuit 111, a frequency synthesizer 110 that is easily digitally controlled and has high frequency stability is often used. The oscillation frequency of the local oscillation circuit 111 is set to a value corresponding to the frequency of the desired channel signal (desired signal), and the desired channel is selected by the mixing circuit 104.

  FIG. 16 is a circuit diagram showing a configuration of the RF amplifier 103 shown in FIG. In a tuner for CATV broadcasting, a broadband amplifier having flat amplification characteristics over a wide frequency band and excellent in low distortion characteristics and return loss characteristics as shown in FIG. 16 is often used. Further, in terrestrial digital broadcast tuners, digital CATV broadcast tuners, and the like, a broadband amplifier as shown in FIG. 16 is often used at the first stage of the tuner.

  In FIG. 16, the RF amplifier 103 includes capacitors 120 to 123, resistance elements 124 to 127, a transistor 128, and an inductor 129.

  Capacitor 120 is connected between the output node of automatic gain control circuit 102 and node N100. Resistance elements 124 and 125 are connected in series between a power supply potential VCC line and a ground potential GND line. A node N100 between the resistance element 124 and the resistance element 125 is connected to the base of the transistor 128. The transistor 128 is an amplifying bipolar transistor. The collector of the transistor 128 is connected to the base of the transistor 128 via the resistance element 126 and the capacitor 121. The emitter of transistor 128 is connected to node N101. Node N101 is connected to a ground potential GND line through resistance element 127, and is connected to a ground potential GND line through capacitor 122. Inductor 129 is connected between the line of power supply potential VCC and the collector of transistor 128. Capacitor 123 is connected between the collector of transistor 128 and the input node of mixing circuit 104.

  Power supply potential VCC is divided by resistance elements 124 and 125 and applied to the base of transistor 128. Resistor element 126 and capacitor 121 constitute a feedback circuit for applying a negative feedback action to transistor 128. The inductor 129 cuts off high frequency components and supplies power to the transistor 128. In this way, a voltage feedback type broadband amplifier is configured.

  FIG. 17 is a circuit diagram showing a configuration of mixing circuit 104 shown in FIG. As the mixing circuit 104, a double balanced mixer having excellent isolation characteristics and low distortion characteristics as shown in FIG. 17 is often used.

  In FIG. 17, the mixing circuit 104 includes capacitors 140 to 146, a resistance element 147, transformers 148 to 150, and transistors 151 to 154.

  Capacitor 140 is connected between the output node of local oscillation circuit 111 and node N110 of transformer 148. Nodes N111 and N113 of transformer 148 are both connected to the ground potential GND line. Capacitor 141 is connected between the output node of RF amplifier 103 and node N115 of transformer 149. Node N116 of transformer 149 is connected to a ground potential GND line through resistance element 147, and is connected to a ground potential GND line through capacitor 142. Node N118 of transformer 149 is connected to a line of ground potential GND through capacitor 143.

  The transistors 151 to 154 are field effect transistors (FETs). The gates of transistors 151 and 154 are both connected to node N112 of transformer 148. The gates of the transistors 152 and 153 are both connected to the node N114 of the transformer 148. The drains of the transistors 151 and 153 are both connected to the node N120 of the transformer 150. The drains of the transistors 152 and 154 are both connected to the node N122 of the transformer 150. The sources of the transistors 151 and 152 are both connected to the node N117 of the transformer 149. The sources of the transistors 153 and 154 are both connected to the node N119 of the transformer 149.

  Node N121 of transformer 150 is connected to a line of ground potential GND through capacitor 144. Node N123 of transformer 150 is connected to an input node of bandpass filter 105 via capacitor 146. Node N124 of transformer 150 is connected to a line of power supply potential VDD, and is connected to a line of ground potential GND through capacitor 145.

  An RF signal from the RF amplifier 103 is converted by the transformer 149 into a differential signal having a phase difference of 180 degrees and an equal amplitude, and is provided to the sources of the transistors 151 to 154. The local oscillation signal having a large amplitude from the local oscillation circuit 111 is converted by the transformer 148 into a differential signal having a phase difference of 180 degrees and an equal amplitude, and is provided to the gates of the transistors 151 to 154. Transistors 151 to 154 perform a switching operation in response to a signal input to the gate. Thereby, the phase inversion of the RF signal is repeated according to the phase of the local oscillation signal. The transformer 150 converts the differential signal into a non-differential signal. As a result, the RF signal is frequency-converted to an IF signal and output. Note that the transformer 150 does not have to be provided when it is not necessary to convert to a non-differential signal.

  Here, in general, non-linear elements such as transistors and diodes are often used in broadband amplifiers and mixing circuits. For this reason, amplitude distortion occurs, causing intermodulation interference and harmonic interference. Intermodulation interference is particularly a problem when multi-channel television signals are input.

  18 and 19 are first and second diagrams showing intermodulation distortion characteristics of the tuner shown in FIG. Here, among the 134 channels of desired signals transmitted at intervals of 6 MHz in the frequency band of 54 MHz to 864 MHz, the RF amplifier 103 and the mixing are performed so that the intermodulation distortion is minimized when the desired signal having a frequency of 853.25 MHz is received. A case where the bias of the circuit 104 is set is shown.

  Referring to FIG. 18, when a desired signal having a frequency of 853.25 MHz is received, intermodulation distortion appears in the vicinity of 854.5 MHz. Referring to FIG. 19, when a desired signal having a frequency of 55.25 MHz is received, intermodulation distortion appears in the vicinity of 54 MHz. Although the intermodulation distortion is small in FIG. 18, the intermodulation distortion is large in FIG. As described above, there is a problem that even if the bias is set so that the intermodulation distortion is reduced with respect to the high frequency desired signal, the intermodulation distortion with respect to the low frequency desired signal is increased. Similarly, there is a problem that even if the bias is set so that the intermodulation distortion is reduced with respect to the low frequency desired signal, the intermodulation distortion with respect to the high frequency desired signal is increased.

  Patent Document 1 below discloses an automatic gain control circuit in which intermodulation distortion hardly occurs and NF is good. According to this, a satellite broadcast receiver is realized in which the NF is sufficiently low and good at the low input level, the input C / N is hardly deteriorated, and the intermodulation distortion hardly occurs at the high input level.

  Further, Patent Document 2 below discloses a tuner that can select the power consumption according to the performance (intermodulation performance or the like) required for the tuner.

Further, in Patent Document 3 below, by controlling the path of the current flowing through the amplification transistor section, the substantial size of the transistors constituting the amplification transistor section is controlled, and the gain of the variable gain amplifier and the IIP3 ( A method for controlling a third-order input intercept point) is disclosed.
JP-A-6-78241 JP 2002-252811 A JP 2002-330039 A

  As described above, in the conventional tuner, since the bias of the amplifier and the mixing circuit is always constant, the collector current flowing through the internal transistor is always constant. In this case, when the frequency of the desired signal to be received is different, the magnitude of the intermodulation distortion is different. For this reason, even if the bias is set so that the intermodulation distortion is reduced with respect to the high frequency desired signal, there is a problem that the intermodulation distortion with respect to the low frequency desired signal is increased. Similarly, there is a problem that even if the bias is set so that the intermodulation distortion is reduced with respect to the low frequency desired signal, the intermodulation distortion with respect to the high frequency desired signal is increased.

  Therefore, a main object of the present invention is to provide a multi-channel receiver having low distortion characteristics over a wide frequency band.

  A multi-channel receiver according to the present invention is a multi-channel receiver that receives a multi-channel signal, includes an amplification nonlinear element, and an amplifier that amplifies and outputs the received multi-channel signal. An oscillation circuit that generates a local oscillation signal with an oscillation frequency corresponding to the frequency of the channel signal, and a non-linear element for frequency conversion, which mixes the output signal of the amplifier with the local oscillation signal and converts it to an intermediate frequency signal The oscillation frequency of the oscillation circuit is set according to the frequency of the circuit and the signal of the desired channel, and the bias of at least one nonlinear element of the amplifier and the mixing circuit is switched and controlled so that the distortion level is reduced. And a control unit.

  Preferably, the control unit controls frequency setting data for controlling the oscillation frequency of the oscillation circuit according to the frequency of the signal of the desired channel, and bias switching control data for switching and controlling the bias of the corresponding nonlinear element, And a bias switching control unit that switches and controls the bias of the corresponding nonlinear element according to the bias switching control data. The oscillation circuit generates a local oscillation signal having an oscillation frequency corresponding to the frequency setting data.

  Preferably, the control unit outputs a control voltage corresponding to the frequency of the signal of the desired channel, a bias switching control unit that switches and controls the bias of the corresponding nonlinear element according to the control voltage, including. The oscillation circuit generates a local oscillation signal having an oscillation frequency corresponding to the control voltage.

  Preferably, the control unit outputs an oscillation frequency control unit that outputs serial data for controlling the oscillation frequency of the oscillation circuit in accordance with a frequency of a desired channel signal, and converts the serial data into parallel data and outputs the parallel data. And a bias switching control unit that switches and controls the bias of the corresponding nonlinear element based on a predetermined logical operation result on the parallel data. The oscillation circuit generates a local oscillation signal having an oscillation frequency corresponding to the serial data.

  Preferably, when the frequency of the signal of the desired channel is higher than a predetermined value, the control unit sets the bias voltage or the bias current of the corresponding non-linear element to the first bias value and sets the signal of the desired channel. When the frequency is lower than the predetermined value, the bias voltage or bias current of the corresponding nonlinear element is set to a second bias value different from the first bias value.

  In the multi-channel receiver according to the present invention, an amplifier for amplifying a received television signal including a non-linear element for amplification and a local oscillation signal having an oscillation frequency corresponding to the frequency of the desired channel signal is generated. An oscillation circuit, a non-linear element for frequency conversion, a mixing circuit that mixes the output signal of the amplifier with a local oscillation signal and frequency-converts it to an intermediate frequency signal, and an oscillation circuit according to the frequency of the desired channel signal. A control unit is provided for setting the oscillation frequency and switching and controlling the bias of at least one of the nonlinear elements of the amplifier and the mixing circuit so that the distortion level is reduced. This makes it possible to suppress both the distortion level when the frequency of the desired channel signal is high and the distortion level when the frequency of the desired channel signal is low. Therefore, a multi-channel receiver having low distortion characteristics over a wide frequency band can be realized.

[Embodiment 1]
1 is a block diagram showing a schematic configuration of a tuner of a television broadcast receiver according to Embodiment 1 of the present invention. In FIG. 1, the tuner includes an input terminal 1, bandpass filters 2 and 6, an automatic gain control circuit (AGC) 3, an RF amplifier 4, a mixing circuit 5, an IF amplifier 7, An output terminal 8, a microcomputer 9, a data bus 10, a decoder 11, a frequency synthesizer 12, a local oscillation circuit 13, a switching control circuit 14, and bias switching circuits 15 and 16 are provided.

  The band-pass filter 2 receives an RF signal received by an antenna (not shown) via the input terminal 1, removes an unnecessary frequency band signal, and passes only a signal in a desired frequency band. The automatic gain control circuit 3 converts the level of the signal that has passed through the bandpass filter 2 to an appropriate level and outputs it while automatically controlling the gain so that a constant level tuner output is always obtained. The RF amplifier 4 amplifies the output signal of the automatic gain control circuit 3 and supplies it to the mixing circuit 5. The mixing circuit 5 mixes the output signal of the RF amplifier 4 with the local oscillation signal from the local oscillation circuit 13 and converts the frequency into an IF (intermediate frequency) signal. The band pass filter 6 receives the IF signal from the mixing circuit 5 and passes only a signal in a desired frequency band. The IF amplifier 7 amplifies the signal that has passed through the band pass filter 6 and supplies the amplified signal to the output terminal 8.

  The microcomputer 9 provides composite data including frequency setting data and bias switching control data to the decoder 11 via a single data bus 10.

FIG. 2 is a diagram showing composite data given from the microcomputer 9 to the decoder 11. In FIG. 2, the synthesized data is used to control the frequency setting data D _{n to} D ₀ for setting the oscillation frequency of the local oscillation circuit 13 shown in FIG. 1 and the bias switching circuits 15 and 16 shown in FIG. Bias switching control data SW ₁ and SW ₀ . The frequency setting data D _{n to} D ₀ and the bias switching control data SW ₁ and SW ₀ are set according to the frequency of the desired signal to be received.

Returning to FIG. 1, the decoder 11 separates the synthesized data from the microcomputer 9 into frequency setting data D _{n to} D ₀ and bias switching control data SW ₁ and SW _0, and outputs the frequency setting data D _{n to} D ₀ . The frequency synthesizer 12 is supplied, and the bias switching control data SW ₁ and SW ₀ are supplied to the switching control circuit 14.

The frequency synthesizer 12 sets the oscillation frequency of the local oscillation circuit 13 according to the frequency setting data D _{n to} D ₀ from the decoder 11. The local oscillation circuit 13 gives a local oscillation signal to the mixing circuit 5. The frequency synthesizer 12 and the local oscillation circuit 13 constitute a phase locked loop circuit (PLL circuit). The oscillation frequency of the local oscillation circuit 13 is set to a value corresponding to the frequency of the desired channel signal (desired signal), and the desired channel is selected by the mixing circuit 5.

The switching control circuit 14 outputs switching control signals SWC1 and SWC0 to the bias switching circuits 15 and 16 in accordance with the bias switching control data SW ₁ and SW ₀ from the decoder 11. The bias switching circuit 15 switches the bias of the RF amplifier 4 to a desired value according to the switching control signal SWC1. The bias switching circuit 16 switches the bias of the mixing circuit 5 to a desired value according to the switching control signal SWC0.

  FIG. 3 is a circuit diagram showing configurations of the RF amplifier 4 and the bias switching circuit 15 shown in FIG. In FIG. 3, the RF amplifier 4 includes capacitors 20 to 23, resistance elements 24 to 27, a transistor 28, and an inductor 29. Bias switching circuit 15 includes resistance elements 30 and 31 and a transistor 32.

  In the RF amplifier 4, the capacitor 20 is connected between the output node of the automatic gain control circuit 3 and the node N1. Resistance elements 24 and 25 are connected in series between a power supply potential VCC line and a ground potential GND line. A node N 1 between the resistance element 24 and the resistance element 25 is connected to the base of the transistor 28. The transistor 28 is an amplifying bipolar transistor. The collector of the transistor 28 is connected to the base of the transistor 28 via the resistance element 26 and the capacitor 21. The emitter of transistor 28 is connected to node N2. Node N2 is connected to a ground potential GND line via resistance element 27, and is connected to a ground potential GND line via capacitor 22. Inductor 29 is connected between the line of power supply potential VCC and the collector of transistor 28. Capacitor 23 is connected between the collector of transistor 28 and the input node of mixing circuit 5.

  Power supply potential VCC is divided by resistance elements 24 and 25 and applied to the base of transistor 28. Resistive element 26 and capacitor 21 constitute a feedback circuit for applying a negative feedback action to transistor 28. The inductor 29 cuts off high frequency components and supplies power to the transistor 128. In this way, a voltage feedback type broadband amplifier is configured.

  In the bias switching circuit 15, the base of the transistor 32 receives the switching control signal SWC 1 from the switching control circuit 14 via the resistance element 30. The collector of the transistor 32 is connected to the node N <b> 2 of the RF amplifier 4 through the resistance element 31. The emitter of the transistor 32 is connected to the ground potential GND line.

  When the switching control signal SWC1 is at “L” level, the transistor 32 is turned off. At this time, a current flows from the power supply potential VCC line to the ground potential GND line via the inductor 29, the transistor 28, and the resistance element 27. On the other hand, when the switching control signal SWC1 is at “H” level, the transistor 32 becomes conductive. At this time, the current flows from the power supply potential VCC line to the ground potential GND line via the inductor 29, the transistor 28 and the resistance element 27, and from the transistor 28 to the ground potential GND line via the resistance element 31 and the transistor 32. Also flows. For this reason, the bias current of the transistor 28 increases and the collector current of the transistor 28 increases. In this way, the emitter resistance of the transistor 28 is switched by the switching control signal SWC1, and the collector current of the transistor 28 is changed.

  Here, the input / output characteristics of the transistor 28 of the RF amplifier 4 will be described. The input / output characteristics of nonlinear elements such as transistors and diodes used in the RF amplifier 4 and the mixing circuit 5 are generally expressed as the following formula (1).

However, y is an output signal, x is the input _{signal, a 0, a 1, a} 2, a 3 ··· denotes a coefficient. Here, when two signals Acos (ω ₁ t) and Acos (ω ₂ t) having the same amplitude and different frequencies are input, that is, when the input signal x = Acos (ω ₁ t) + Acos (ω ₂ t). think about. However, A is an amplitude, ω is an angular frequency, and t is time. At this time, the output signal y is expressed as the following mathematical formula (2).

The output signal y corresponds to fundamental wave components corresponding to angular frequencies ω ₁ and ω ₂ , second harmonic components corresponding to 2ω ₁ and 2ω ₂ , (ω ₁ + ω ₂ ), and (ω ₁ −ω ₂ ). It consists of second order intermodulation distortion components. Here, the second-order intermodulation distortion component becomes larger than the higher-order intermodulation distortion component when the amplitude A is small, which causes a problem when a broadband signal is received.

  As an example, a case of digital CATV broadcasting using a frequency band of 54 MHz to 864 MHz will be described. For example, when two signals with frequencies of 750 MHz and 100 MHz are received, second-order intermodulation distortion of 850 (= 750 + 100) MHz and 650 (= 750−100) MHz is generated. At this time, when a signal of a channel near 850 MHz is received, the generated 850 MHz second-order intermodulation distortion becomes a factor of intermodulation interference. Here, since there are a large number of combinations such as 700 MHz and 150 MHz in addition to 750 MHz and 100 MHz that have a sum of two frequencies of 850 MHz, a large number of second-order intermodulation distortion components overlap to generate large intermodulation interference.

  FIG. 4 is a diagram showing the number of combinations of the sum (f1 + f2) and the difference (f1−f2) of two frequencies f1 and f2 in the frequency band 54 MHz to 864 MHz. In US digital CATV broadcasting, signals of 134 channels are used at intervals of 6 MHz within a frequency band of 54 MHz to 864 MHz. The number of combinations (f1 + f2) corresponding to the frequency of each channel increases as the frequency increases. That is, the second-order intermodulation distortion of (f1 + f2) is larger as the frequency is higher. On the other hand, the number of combinations (f1-f2) corresponding to the frequency of each channel increases as the frequency decreases. That is, the second-order intermodulation distortion of (f1-f2) is larger as the frequency is lower.

  FIG. 5 is a diagram showing the relationship between the collector current of the transistor 28 shown in FIG. 3 and the intermodulation interference ratio. Here, the intermodulation interference ratio is a ratio between the level of the second-order intermodulation distortion and the level of the desired signal, and it is preferable that this level is low. In FIG. 5, the second-order intermodulation distortion of (f1 + f2) and the second-order intermodulation distortion of (f1−f2) change according to the collector current. The second order intermodulation distortion of (f1 + f2) is minimized when the collector current is 45 mA, and the second order intermodulation distortion of (f1−f2) is minimized when the collector current is 52 mA. However, the value of the collector current is an example and is not limited to this.

  Therefore, in the first embodiment, when a desired signal having a high frequency is received, disturbance caused by the second-order intermodulation distortion of (f1 + f2) becomes large, so that the collector current of the transistor 28 has a predetermined value I1 (for example, 45 mA) to suppress intermodulation interference. On the other hand, when a desired signal having a low frequency is received, interference caused by the second-order intermodulation distortion of (f1-f2) becomes large, so that the collector current of the transistor 28 is larger than a predetermined value I2 (for example, 52 mA). ) To suppress intermodulation interference.

That is, referring to FIG. 3, when a desired signal having a frequency higher than a predetermined frequency f _ref is received, the switching control signal SWC1 is set to the “L” level to make the transistor 32 nonconductive. The collector current of the transistor 28 is set to a predetermined value I1 (for example, 45 mA). On the other hand, when receiving a desired signal having a frequency lower than a predetermined frequency f _ref , the switching control signal SWC1 is set to the “H” level to turn on the transistor 32, whereby the collector current of the transistor 28 is made higher than I1. A large predetermined value I2 (for example, 52 mA) is set. Thereby, it is possible to suppress the second-order intermodulation distortion according to the frequency of the desired signal to be received.

  FIG. 6 is a diagram illustrating a modification of FIG. In FIG. 6, the collector of the transistor 32 of the bias switching circuit 15 is connected to the node N <b> 1 of the RF amplifier 4 through the resistance element 31.

  When the switching control signal SWC1 is at “L” level, the transistor 32 is turned off. At this time, the power supply potential VCC is divided by the resistance elements 24 and 25 and applied to the base of the transistor 28. On the other hand, when the switching control signal SWC1 is at “H” level, the transistor 32 becomes conductive. At this time, since a current flows from the node N1 to the line of the ground potential GND through the resistance element 31 and the transistor 32, the bias voltage applied to the base of the transistor 28 is reduced, and the collector current of the transistor 28 is reduced. As described above, the bias of the transistor 28 is switched to a desired value by the switching control signal SWC1, and the collector current of the transistor 28 is changed.

That is, when a desired signal having a frequency higher than the predetermined frequency f _ref is received, the switching control signal SWC1 is set to the “H” level to turn on the transistor 32, whereby the collector current of the transistor 28 is set to the predetermined value I1. (For example, 45 mA). On the other hand, when a desired signal having a frequency lower than the predetermined frequency f _ref is received, the switching control signal SWC1 is set to the “L” level to turn off the transistor 32, whereby the collector current of the transistor 28 is reduced to I1. Larger than a predetermined value I2 (for example, 52 mA). Thereby, it is possible to suppress the second-order intermodulation distortion according to the frequency of the desired signal to be received.

  3 and 6 exemplify a voltage feedback configuration in which a feedback circuit including the resistor element 26 and the capacitor 21 is provided. Instead of the voltage feedback configuration, a resistor is provided between the emitter of the transistor 28 and the node N2. You may make it the current feedback structure which provides an element. Further, both the voltage feedback configuration and the current feedback configuration may be applied.

  Here, a case where a bipolar transistor is used as the amplifying transistor 28 is shown, but a field effect transistor (FET) may be used.

  Further, both the bias switching circuit 15 corresponding to the node N2 shown in FIG. 3 and the bias switching circuit 15 corresponding to the node N1 shown in FIG. 6 may be provided. In this case, the margin for the maximum rating of the transistor 28 is increased, and more accurate bias switching control is possible.

  FIG. 7 is a circuit diagram showing a configuration of mixing circuit 5 and bias switching circuit 16 shown in FIG. In FIG. 7, mixing circuit 5 includes capacitors 40 to 46, resistance element 47, transformers 48 to 50, and transistors 51 to 54. Bias switching circuit 16 includes resistance elements 60 and 61 and a transistor 62.

  In the mixing circuit 5, the capacitor 40 is connected between the output node of the local oscillation circuit 13 and the node N 10 of the transformer 48. Nodes N11 and N13 of transformer 48 are both connected to the ground potential GND line. The capacitor 41 is connected between the output node of the RF amplifier 4 and the node N15 of the transformer 49. A node N16 of the transformer 49 is connected to the ground potential GND line through the resistance element 47 and is connected to the ground potential GND line through the capacitor. Node N18 of transformer 49 is connected to a line of ground potential GND through capacitor 43.

  The transistors 51 to 54 are field effect transistors (FETs). The gates of the transistors 51 and 54 are both connected to the node N12 of the transformer 48. The gates of the transistors 52 and 53 are both connected to the node N14 of the transformer 48. The drains of the transistors 51 and 53 are both connected to the node N20 of the transformer 50. The drains of the transistors 52 and 54 are both connected to the node N22 of the transformer 50. The sources of the transistors 51 and 52 are both connected to the node N17 of the transformer 49. The sources of the transistors 53 and 54 are both connected to the node N19 of the transformer 49.

  Node N21 of transformer 50 is connected to a line of ground potential GND through capacitor 44. A node N23 of the transformer 50 is connected to an input node of the bandpass filter 6 through a capacitor 46. Node N24 of transformer 50 is connected to the line of power supply potential VDD and is connected to the line of ground potential GND through capacitor 45.

  The RF signal from the RF amplifier 4 is converted by the transformer 49 into a differential signal having a phase difference of 180 degrees and an equal amplitude, and is provided to the sources of the transistors 51 to 54. The large-oscillation local oscillation signal from the local oscillation circuit 13 is converted by the transformer 48 into a differential signal having a phase difference of 180 degrees and an equal amplitude, and is provided to the gates of the transistors 51 to 54. Transistors 51 to 54 perform a switching operation in response to a signal input to the gate, respectively. Thereby, the phase inversion of the RF signal is repeated according to the phase of the local oscillation signal. The transformer 50 converts the differential signal into a non-differential signal. As a result, the RF signal is frequency-converted to an IF signal and output. Note that the transformer 50 need not be provided if it is not necessary to convert the transformer 50 into a non-differential signal.

  In the bias switching circuit 16, the base of the transistor 62 receives the switching control signal SWC 0 from the switching control circuit 14 via the resistance element 60. The collector of the transistor 62 is connected to the node N16 of the mixing circuit 5 through the resistance element 61. The emitter of transistor 62 is connected to the line of ground potential GND.

  When the switching control signal SWC0 is at “L” level, the transistor 62 is turned off. At this time, a current flows from the power supply potential VDD line to the ground potential GND line via the transformer 50, the transistors 51 to 54, the transformer 49, and the resistance element 47. On the other hand, when the switching control signal SWC0 is at “H” level, the transistor 62 becomes conductive. At this time, the current flows from the power supply potential VDD line to the ground potential GND line via the transformer 50, the transistors 51 to 54, the transformer 49, and the resistance element 47, and from the node N16 to the ground via the resistance element 61 and the transistor 62. It also flows through the potential GND line. For this reason, the bias currents of the transistors 51 to 54 increase, and the drain currents of the transistors 51 to 54 increase.

  Here, the relationship between the drain currents of the transistors 51 to 54 of the mixing circuit 5 and the intermodulation interference ratio is the same as the relationship between the collector current of the transistor 28 of the RF amplifier 4 and the intermodulation interference ratio shown in FIG. . That is, the second-order intermodulation distortion of (f1 + f2) and the second-order intermodulation distortion of (f1-f2) change according to the drain currents of the transistors 51 to 54, respectively, and the sum of the drain currents of the transistors 51 to 54 is predetermined. The second order intermodulation distortion of (f1 + f2) is minimized when the value is I11, and the second order intermodulation distortion of (f1−f2) when the sum of the drain currents of the transistors 51 to 54 is a predetermined value I12 (> I11). Is minimized.

When a desired signal having a frequency higher than the predetermined frequency f _ref is received, the drain current of the transistors 51 to 54 is set by setting the switching control signal SWC0 to the “L” level to turn off the transistor 62. Is set to a predetermined value I11. On the other hand, when a desired signal having a frequency lower than a predetermined frequency f _ref is received, the sum of drain currents of the transistors 51 to 54 is made by setting the switching control signal SWC0 to the “H” level and making the transistor 62 conductive. Is set to a predetermined value I12. As described above, the source resistances of the transistors 51 to 54 are switched by the switching control signal SWC0 to change the drain currents of the transistors 51 to 54. Thereby, it is possible to suppress the second-order intermodulation distortion according to the frequency of the desired signal to be received.

  FIG. 8 is a diagram showing a modified example of FIG. In FIG. 8, the collector of the transistor 62 of the bias switching circuit 16 is connected to the node N <b> 11 of the mixing circuit 5 via the resistance element 61. In the mixing circuit 5, capacitors 70 and 71 and resistance elements 72 and 73 are provided. Capacitor 70 is connected between node N11 of transformer 48 and a line of ground potential GND. Capacitor 71 is connected between node N13 of transformer 48 and the line of ground potential GND. Resistance elements 72 and 73 are connected in series between a power supply potential VDD line and a ground potential GND line, and a node between resistance element 72 and resistance element 73 is connected to a node N11 of transformer 48.

  When the switching control signal SWC0 is at “L” level, the transistor 62 is turned off. At this time, the power supply potential VDD is divided by the resistance elements 72 and 73 and supplied to the gates of the transistors 51 to 54. On the other hand, when the switching control signal SWC0 is at “H” level, the transistor 62 becomes conductive. At this time, since a current flows from the node N11 to the line of the ground potential GND through the resistance element 61 and the transistor 62, the bias voltage applied to the gates of the transistors 51 to 54 is reduced, and the drain currents of the transistors 51 to 54 are reduced. Get smaller. In this way, the bias of the transistors 51 to 54 is switched to a desired value by the switching control signal SWC0, and the drain currents of the transistors 51 to 54 are changed.

That is, when a desired signal having a frequency higher than the predetermined frequency f _ref is received, the drain current of the transistors 51 to 54 is set to a predetermined level by setting the switching control signal SWC0 to the “H” level to turn on the transistor 62. Set to the value I11. On the other hand, when a desired signal having a frequency lower than the predetermined frequency f _ref is received, the drain current of the transistors 51 to 54 is set by setting the switching control signal SWC0 to “L” level to turn off the transistor 62. Is set to a predetermined value I12 (> I11). Thereby, it is possible to suppress the second-order intermodulation distortion according to the frequency of the desired signal to be received.

  Here, a case where a field effect transistor (FET) is used as the transistors 51 to 54 is shown, but a bipolar transistor may be used.

  Further, both the bias switching circuit 16 corresponding to the node N16 shown in FIG. 7 and the bias switching circuit 16 corresponding to the node N11 shown in FIG. 8 may be provided. In this case, the margin for the maximum rating of the transistors 51 to 54 is increased, and more accurate bias switching control is possible.

  9 and 10 are first and second diagrams showing intermodulation distortion characteristics of the tuner shown in FIG. Referring to FIG. 9, when a desired signal having a frequency of 853.25 MHz is received among 134 desired signals transmitted at intervals of 6 MHz in a frequency band of 54 MHz to 864 MHz, (f1 + f2) 2 in the vicinity of 854.5 MHz. The next intermodulation distortion appears. Referring to FIG. 10, when a desired signal having a frequency of 55.25 MHz is received, a second-order intermodulation distortion of (f1-f2) appears in the vicinity of 54 MHz. In this case, it can be seen that the second-order intermodulation distortions of (f1 + f2) and (f1-f2) are both small and improved compared to the intermodulation distortion characteristics of the conventional tuner shown in FIGS.

  In the conventional tuner shown in FIG. 15, since the bias of the RF amplifier 103 and the mixing circuit 104 is always constant, the collector current flowing through the internal transistor and the like is always constant. Therefore, if the (f1 + f2) second-order intermodulation distortion is set to be small with respect to the high-frequency desired signal, the (f1-f2) second-order intermodulation distortion with respect to the low-frequency desired signal is increased. was there. On the other hand, if the second-order intermodulation distortion of (f1−f2) is set to be small with respect to the low-frequency desired signal, the second-order intermodulation distortion of (f1 + f2) with respect to the high-frequency desired signal is increased. There was a problem.

  However, in the first embodiment, the bias of the RF amplifier 4 and the mixing circuit 5 is switched by the bias switching circuits 15 and 16 according to the frequency of the desired signal to be received. This makes it possible to suppress both (f1 + f2) second-order intermodulation distortion for a high-frequency desired signal and (f1-f2) second-order intermodulation distortion for a low-frequency desired signal. Therefore, a multi-channel receiver having low distortion characteristics over a wide frequency band can be realized. Thereby, if the present invention is used for a television broadcast receiver, noise and beat are reduced, and if it is used for a data receiver, transmission errors are reduced, and the reception performance of the receiver is improved.

Although the case where the biases of both the RF amplifier 4 and the mixing circuit 5 are switched has been described here, the bias of only one of the RF amplifier 4 and the mixing circuit 5 may be switched. In this case, only _{one of} the 2-bit bias switching control data SW ₁ and SW ₀ shown in FIG. 2 may be used.

[Embodiment 2]
FIG. 11 is a block diagram showing a schematic configuration of a tuner of a television broadcast receiver according to Embodiment 2 of the present invention, and is a diagram compared with FIG. Referring to FIG. 11, the difference from FIG. 1 is that the microcomputer 9, the data bus 10, the decoder 11, the frequency synthesizer 12, the local oscillation circuit 13, and the switching control circuit 14 are deleted, and the control voltage A generation circuit 80, a voltage controlled oscillator (VCO) 81, and a switching control circuit 82 are added. In FIG. 11, portions corresponding to those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The control voltage generation circuit 80 generates a control voltage VC for controlling the oscillation frequency of the voltage controlled oscillator 81. This control voltage VC is set according to the frequency of the desired signal to be received. The voltage controlled oscillator 81 gives a local oscillation signal having an oscillation frequency corresponding to the control voltage VC from the control voltage generation circuit 80 to the mixing circuit 5. The switching control circuit 82 outputs a switching control signal SWC10 to the bias switching circuits 15 and 16 in accordance with the control voltage VC from the control voltage generation circuit 80.

  FIG. 12 is a diagram for explaining the operation of voltage controlled oscillator 81 shown in FIG. Referring to FIG. 12, the higher the control voltage VC, the higher the oscillation frequency of the voltage controlled oscillator 81. For example, when it is desired to set the oscillation frequency of the voltage controlled oscillator 81 to 300 MHz, the control voltage VC from the control voltage generation circuit 80 may be set to 5V.

  FIG. 13 is a circuit diagram showing a configuration of switching control circuit 82 shown in FIG. In FIG. 13, the switching control circuit 82 includes a comparator 83. The negative input node of comparator 83 receives control voltage VC from control voltage generation circuit 80. The positive input node of the comparator 83 receives the reference voltage Vref. A switching control signal SWC10 is output from the output node of the comparator 83. The comparator 83 compares the control voltage VC and the reference voltage Vref. When the control voltage VC is higher than the reference voltage Vref, the comparator 83 sets the output switching control signal SWC10 to the “L” level, and the control voltage VC is higher than the reference voltage Vref. When it is low, the output switching control signal SWC10 is set to the “H” level.

  For example, when the oscillation frequency of 300 MHz of the voltage controlled oscillator 81 is used as a reference for bias switching, the reference voltage Vref is preset to 5V. At this time, when the control voltage VC is higher than the reference voltage 5V, the switching control signal SWC10 is set to the “L” level, and when the control voltage VC is lower than the reference voltage 5V, the switching control signal SWC10 is set to the “H” level. To be.

  Returning to FIG. 11, the bias switching circuit 15 switches the bias of the RF amplifier 4 to a desired value in accordance with the switching control signal SWC10. The bias switching circuit 16 switches the bias of the mixing circuit 5 to a desired value according to the switching control signal SWC10. However, here, the bias switching circuit 15 and the RF amplifier 4 have the configuration shown in FIG. 3, and the bias switching circuit 16 and the mixing circuit 5 have the configuration shown in FIG.

In this case, when a desired signal having a frequency higher than a predetermined frequency f _ref is received, the switching control signal SWC10 is set to “L” level, and the collector current of the transistor 28 of the RF amplifier 4 is set to a predetermined value I1 ( For example, 45 mA). Further, the sum of the drain currents of the transistors 51 to 54 of the mixing circuit 5 is set to a predetermined value I11. On the other hand, when a desired signal having a frequency lower than the predetermined frequency f _ref is received, the switching control signal SWC10 is set to “H” level, and the collector current of the transistor 28 of the RF amplifier 4 is larger than I1. The value is set to I2 (for example, 52 mA). Further, the sum of the drain currents of the transistors 51 to 54 of the mixing circuit 5 is set to a predetermined value I12 (> I11). Thereby, it is possible to suppress the second-order intermodulation distortion according to the frequency of the desired signal to be received.

Therefore, in the second embodiment, bias switching is performed by determining whether the frequency of the desired signal to be received is higher or lower than a predetermined frequency f _ref using the control voltage VC from the control voltage generation circuit 80. Control can be performed. Thereby, the same effect as Embodiment 1 is acquired. In the first embodiment, the frequency setting data is transmitted from the microcomputer 9 via the data bus 10, but in the second embodiment, the bias is generated using the control voltage VC from the control voltage generating circuit 80. Since switching control is performed, the configuration is simpler and high-speed operation of bias switching control is possible.

  When the bias switching circuit 15 and the RF amplifier 4 have the configuration shown in FIG. 6 and the bias switching circuit 16 and the mixing circuit 5 have the configuration shown in FIG. 8, the switching control circuit 82 shown in FIG. The negative input node and the positive input node of the comparator 83 may be switched.

Further, the relationship between the control voltage VC of the voltage controlled oscillator 81 and the oscillation frequency varies somewhat depending on the manufacturing variation of the element. However, since strict bias switching control is not required here, there is no particular problem. Referring to FIG. 4, the difference between the second-order intermodulation distortion of (f1 + f2) and the second-order intermodulation distortion of (f1-f2) is the highest at the highest frequency in the received frequency band. This is because the frequency f _ref used as a reference for bias switching does not need to be determined strictly because the frequency becomes low.

[Embodiment 3]
FIG. 14 is a block diagram showing a schematic configuration of a tuner of a television broadcast receiver according to Embodiment 3 of the present invention, and is compared with FIG. Referring to FIG. 11, the difference from FIG. 1 is that the microcomputer 9, the data bus 10, the decoder 11, and the switching control circuit 14 are deleted, a PLL control circuit 90, a shift register 91, and a logic gate. 92 is added. In FIG. 14, portions corresponding to those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The PLL control circuit 90 outputs frequency setting data for setting the oscillation frequency of the local oscillation circuit 13. This frequency setting data is, for example, binary digital data representing a positive integer N (= local oscillation frequency / reference frequency). For example, when the local oscillation frequency is 508 MHz and the reference frequency is 62.5 kHz, the value of the integer N is 8128. In this case, the frequency setting data is “1111111000000000”. Here, the most significant bit MSB is 1, and the least significant bit LSB is 0.

  The shift register 91 performs serial / parallel conversion on the frequency setting data and outputs it. The logic gate 92 outputs a switching control signal SWC20 to the bias switching circuits 15 and 16 based on a predetermined logical operation result for the output data of the shift register 91.

  For example, when the local oscillation frequency of 508 MHz is used as a reference for bias switching, the logic gate 92 outputs the “L” level switching control signal SWC20 when the seventh and higher bits from the least significant bit LSB are all “1”. When at least one “0” is included in the seventh and higher bits from the least significant bit LSB, an “H” level switching control signal SWC20 is output. That is, when the local oscillation frequency is higher than 508 MHz, the switching control signal SWC20 is set to “L” level, and when the local oscillation frequency is lower than 508 MHz, the switching control signal SWC20 is set to “H” level.

  The bias switching circuit 15 switches the bias of the RF amplifier 4 to a desired value according to the switching control signal SWC20. The bias switching circuit 16 switches the bias of the mixing circuit 5 to a desired value according to the switching control signal SWC20. However, here, the bias switching circuit 15 and the RF amplifier 4 have the configuration shown in FIG. 3, and the bias switching circuit 16 and the mixing circuit 5 have the configuration shown in FIG.

In this case, when a desired signal having a frequency higher than a predetermined frequency f _ref is received, the switching control signal SWC20 is set to the “L” level, and the collector current of the transistor 28 of the RF amplifier 4 is set to a predetermined value I1 ( For example, 45 mA). Further, the sum of the drain currents of the transistors 51 to 54 of the mixing circuit 5 is set to a predetermined value I11. On the other hand, when a desired signal having a frequency lower than the predetermined frequency f _ref is received, the switching control signal SWC20 is set to “H” level, and the collector current of the transistor 28 of the RF amplifier 4 is larger than I1. The value is set to I2 (for example, 52 mA). Further, the sum of the drain currents of the transistors 51 to 54 of the mixing circuit 5 is set to a predetermined value I12 (> I11). Thereby, it is possible to suppress the second-order intermodulation distortion according to the frequency of the desired signal to be received.

Therefore, in the third embodiment, the bias setting control is performed by determining whether the frequency of the desired signal to be received is higher or lower than the predetermined frequency f _ref using the frequency setting data from the PLL control circuit 90. Can be performed. Thereby, the same effect as in the second embodiment can be obtained.

  When the bias switching circuit 15 and the RF amplifier 4 have the configuration shown in FIG. 6, and the bias switching circuit 16 and the mixing circuit 5 have the configuration shown in FIG. 8, the output switching control signal SWC20 of the logic gate 92 is used. What is necessary is just to invert the logic level.

In the first to third embodiments, the case where it is determined whether the frequency of the desired signal to be received is higher or lower than the predetermined frequency f _ref has been described. Compared with _ref1 , f _ref2 ..., finer bias switching control may be performed. In this case, the configuration becomes more complicated, but better low distortion characteristics can be realized.

  Here, the case where the nonlinear elements included in the RF amplifier 4 and the mixing circuit 5 have characteristics as shown in FIG. 5 has been described as an example, but the present invention is not limited to this. Specifically, the case where the current value when the second-order intermodulation distortion of (f1 + f2) is minimum is lower than the current value when the second-order intermodulation distortion of (f1−f2) is minimized is taken as an example. However, depending on the element, the current value when the second order intermodulation distortion of (f1 + f2) is minimized is higher than the current value when the second order intermodulation distortion of (f1−f2) is minimized. is there. In this case, invert the polarity of the switching control signal so that a high frequency desired signal is received so that the collector current or drain current of the corresponding non-linear element increases, and a low frequency desired signal is received. The same effect can be obtained by reducing the collector current or drain current of the nonlinear element.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is a block diagram which shows schematic structure of the tuner of the television broadcast receiver by Embodiment 1 of this invention. It is a figure which shows the synthetic | combination data given to a decoder from the microcomputer shown in FIG. FIG. 2 is a circuit diagram illustrating a configuration of an RF amplifier 4 and a bias switching circuit 15 illustrated in FIG. 1. It is a figure which shows the number of combinations of the sum (f1 + f2) and difference (f1-f2) of two frequency f1, f2 in the frequency band 54MHz-864MHz. It is a figure which shows the relationship between the collector current of the transistor 28 shown in FIG. 3, and an intermodulation interference ratio. It is a figure which shows the example of a change of FIG. FIG. 2 is a circuit diagram illustrating configurations of a mixing circuit 5 and a bias switching circuit 16 illustrated in FIG. 1. It is a figure which shows the example of a change of FIG. FIG. 3 is a first diagram illustrating intermodulation distortion characteristics of the tuner illustrated in FIG. 1. FIG. 4 is a second diagram showing intermodulation distortion characteristics of the tuner shown in FIG. 1. It is a block diagram which shows schematic structure of the tuner of the television broadcast receiver by Embodiment 2 of this invention. It is a figure for demonstrating operation | movement of the voltage controlled oscillator shown in FIG. It is a circuit diagram which shows the structure of the switching control circuit shown in FIG. It is a block diagram which shows schematic structure of the tuner of the television broadcast receiver by Embodiment 3 of this invention. It is a block diagram which shows schematic structure of the tuner of the conventional television broadcast receiver. FIG. 16 is a circuit diagram illustrating a configuration of the RF amplifier illustrated in FIG. 15. FIG. 16 is a circuit diagram illustrating a configuration of a mixing circuit illustrated in FIG. 15. FIG. 16 is a first diagram illustrating intermodulation distortion characteristics of the tuner illustrated in FIG. 15. FIG. 16 is a second diagram showing intermodulation distortion characteristics of the tuner shown in FIG. 15.

Explanation of symbols

  1,100 input terminal, 2,6,101,105 band pass filter, 3,102 automatic gain control circuit, 4,103 RF amplifier, 5,104 mixing circuit, 7,106 IF amplifier, 8,107 output terminal, 9 , 108 microcomputer, 10, 109 data bus, 11 decoder, 12, 110 frequency synthesizer, 13, 111 local oscillation circuit, 14 switching control circuit, 15, 16 bias switching circuit, 20-23, 40-46, 70, 71 , 120 to 123, 140 to 146 capacitors, 24 to 27, 30, 31, 47, 60, 61, 72, 73, 124 to 127, 147 resistance elements, 28, 32, 51 to 54, 62, 128, 151 to 154 transistor, 29, 129 inductor, 48-50, 148-150 transformer, 8 Control voltage generating circuit, 81 a voltage controlled oscillator, 82 switching control circuit, 83 a comparator, 90 PLL control circuit, 91 a shift register, 92 logic gates.

Claims (5)

A multi-channel receiver for receiving multi-channel signals,
An amplifier that includes a non-linear element for amplification and amplifies and outputs the received multi-channel signal;
An oscillation circuit that generates a local oscillation signal having an oscillation frequency corresponding to the frequency of the signal of the desired channel,
A mixing circuit that includes a non-linear element for frequency conversion, mixes the output signal of the amplifier with the local oscillation signal and converts the frequency into an intermediate frequency signal, and, depending on the frequency of the signal of the desired channel, A multi-channel receiver including a control unit that switches and controls a bias of at least one of the amplifier and the mixing circuit so as to set an oscillation frequency and reduce a distortion level. The controller is
A microcomputer that outputs frequency setting data for controlling the oscillation frequency of the oscillation circuit and bias switching control data for switching and controlling the bias of the corresponding nonlinear element according to the frequency of the signal of the desired channel. And a bias switching control unit that switches and controls the bias of the corresponding nonlinear element according to the bias switching control data,
The multi-channel receiver according to claim 1, wherein the oscillation circuit generates the local oscillation signal having an oscillation frequency corresponding to the frequency setting data. The controller is
A control voltage generation circuit that outputs a control voltage according to the frequency of the signal of the desired channel, and a bias switching control unit that switches and controls the bias of the corresponding nonlinear element according to the control voltage;
The multi-channel receiver according to claim 1, wherein the oscillation circuit generates the local oscillation signal having an oscillation frequency according to the control voltage. The controller is
An oscillation frequency control unit that outputs serial data for controlling the oscillation frequency of the oscillation circuit according to the frequency of the signal of the desired channel,
A shift register that converts the serial data into parallel data and outputs the shift data; and a bias switching control unit that controls the bias of the corresponding nonlinear element based on a predetermined logical operation result for the parallel data;
The multi-channel receiver according to claim 1, wherein the oscillation circuit generates the local oscillation signal having an oscillation frequency corresponding to the serial data.   When the frequency of the signal of the desired channel is higher than a predetermined value, the control unit sets the bias voltage or bias current of the corresponding nonlinear element to the first bias value, and the frequency of the signal of the desired channel 5 is lower than a predetermined value, the bias voltage or bias current of the corresponding nonlinear element is set to a second bias value different from the first bias value. Multi-channel receiver.

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