CN115276690B - Radio frequency receiving system and output third-order intermodulation point OIP3 calibration method - Google Patents
Radio frequency receiving system and output third-order intermodulation point OIP3 calibration method Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
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- H—ELECTRICITY
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- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/16—Multiple-frequency-changing
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/56—Modifications of input or output impedances, not otherwise provided for
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
- H03F3/193—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
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- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
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- H—ELECTRICITY
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- H04B—TRANSMISSION
- H04B17/00—Monitoring; Testing
- H04B17/20—Monitoring; Testing of receivers
- H04B17/21—Monitoring; Testing of receivers for calibration; for correcting measurements
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- H—ELECTRICITY
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- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/294—Indexing scheme relating to amplifiers the amplifier being a low noise amplifier [LNA]
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- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
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- H—ELECTRICITY
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- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
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Abstract
The embodiment of the disclosure provides a radio frequency receiving system and an OIP3 calibration method, and relates to the field of signal processing. The system comprises a radio frequency receiving end, a low noise amplifier LNA, a Mixer Mixer, a local oscillator LO, a digital-to-analog converter ADC, an operational amplifier OPA, a feedback circuit and a negative resistance circuit, wherein the operational amplifier OPA comprises a transimpedance amplifier TIA, a low pass filter LPF, a variable gain amplifier PGA, and the negative resistance circuit comprises a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a variable P tube current source and a variable N tube current source; the negative resistance circuit is connected between the non-inverting input terminal and the inverting input terminal of the transimpedance amplifier TIA, and the output terminal of the variable gain amplifier PGA is connected to the negative resistance circuit through the feedback circuit. In this way, the problem of insufficient linearity of the radio frequency receiver can be solved, the automatic calibration of the OIP3 in the radio frequency receiver can be realized, and the linearity of the radio frequency receiver can be improved.
Description
Technical Field
The present disclosure relates to the field of signal processing, and in particular, to the field of radio frequency receiver technology.
Background
The current OIP3 method for improving the OPA of the operational amplifier is mainly three, the first method is to improve the power supply voltage, the power supply voltage is improved to allow larger input and output swing, thus improving OIP3, but the voltage cannot be improved at will, in order to pursue high-speed large-bandwidth performance, the existing design is increasingly provided with high-speed MOS tubes, the risk of breakdown is caused by the excessively high power supply voltage of the high-speed MOS tubes, so that the reliability problem is brought, and the second method is to increase the current of the OPA, improve the driving capability of the OPA, and improve OIP3, but the method has large power consumption and low cost performance; the third method adopts a low-voltage design technology, and can have larger output swing under the limited power supply voltage, so that OIP3 is improved, the defect is that the gain is insufficient, the multi-stage cascade compensation gain is needed, the bandwidth is reduced, the area is increased, and therefore, the existing method for improving the OIP3 of the OPA cannot meet the current requirement.
Disclosure of Invention
The present disclosure provides a radio frequency receiving system and an output third-order intermodulation point OIP3 calibration method, wherein a negative resistance circuit is connected between a non-inverting input end and an inverting input end of a transimpedance amplifier TIA to cancel an original resistance, so that virtual ground characteristics are recovered, and linearity is improved.
According to a first aspect of the present disclosure, there is provided a radio frequency receiving system, the system comprising:
the radio frequency receiving end, the low noise amplifier LNA, the Mixer, the local oscillator LO, the digital-to-analog converter ADC, the operational amplifier OPA, the feedback circuit and the negative resistance circuit, wherein,
the operational amplifier OPA comprises a transimpedance amplifier TIA, a low-pass filter LPF and a variable gain amplifier PGA, the feedback circuit comprises a polyphase filter PPF, an ERROR amplifier ERROR AMP and an auxiliary digital-to-analog converter AUX ADC, and the negative resistance circuit comprises a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a variable P tube current source and a variable N tube current source;
the negative resistance circuit is connected between the non-inverting input end and the inverting input end of the transimpedance amplifier TIA, and the output end of the variable gain amplifier PGA is connected to the negative resistance circuit through the feedback circuit.
In the aspect and any possible implementation manner as described above, there is further provided an implementation manner, in which a non-inverting input terminal of the low noise amplifier LNA is connected to the radio frequency receiving terminal; the first port of the Mixer is connected with the output end of the low noise amplifier LNA, the second port is connected with the local oscillator LO, and the third port is connected with the input end of the transimpedance amplifier TIA; a negative resistance circuit is connected between the non-inverting input end and the inverting input end of the transimpedance amplifier TIA, and the output end is connected with the input end of the low-pass filter LPF; the input end of the variable gain amplifier PGA is connected with the output end of the low-pass filter LPF, and the output end is connected with the input end of the polyphase filter PPF and the input end of the digital-to-analog converter ADC; the input end of the ERROR amplifier ERROR AMP is connected with the output end of the polyphase filter PPF, and the output end is connected with the input end of the auxiliary digital-to-analog converter AUX ADC; and the output end of the auxiliary digital-to-analog converter AUX ADC is connected with a negative resistance circuit.
Aspects and any possible implementation manner as described above further provide an implementation manner, where the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, and the fourth MOS transistor M4 are cross-coupled MOS transistors.
The aspects and any possible implementation manner as described above further provide an implementation manner, where the drains of the first MOS transistor M1 and the second MOS transistor M2 are connected to the non-inverting input terminal of the transimpedance amplifier TIA; the drain electrodes of the third MOS tube M3 and the fourth MOS tube M4 are connected with the inverting input end of the transimpedance amplifier TIA; the sources of the first MOS tube M1 and the third MOS tube M3 are connected with the drain electrode of the variable P tube current source; the source electrodes of the second MOS tube M2 and the fourth MOS tube M4 are connected with the drain electrode of the variable N-tube current source; the grid electrodes of the first MOS tube M1 and the second MOS tube M2 are connected with the inverting input end of the transimpedance amplifier TIA; the grid electrodes of the third MOS tube M3 and the fourth MOS tube M4 are connected with the non-inverting input end of the transimpedance amplifier TIA; the source of the variable P-tube current source is connected with VDD, and the source of the variable N-tube current source is grounded.
The above aspect and any possible implementation manner further provide an implementation manner, where the variable P-tube current source includes a plurality of PMOS tubes arranged in parallel, sources of the plurality of PMOS tubes are connected to VDD, drains of the plurality of PMOS tubes are connected to sources of the first MOS tube M1 and the third MOS tube M3, gates of the first PMOS tube of the plurality of PMOS tubes are connected to a first power supply, gates of other PMOS tubes are connected to the first power supply through a switch, and an output end of the auxiliary digital-to-analog converter AUX ADC controls corresponding switches of gates of the other PMOS tubes, where the first power supply is used to provide a first bias voltage pbias;
the variable N-tube current source comprises a plurality of NMOS tubes which are arranged in parallel, the source electrodes of the NMOS tubes are grounded, the drain electrodes of the NMOS tubes are connected with the source electrodes of the second MOS tube M2 and the fourth MOS tube M4, wherein the grid electrodes of the first NMOS tube in the PMOS tubes are connected with a second power supply, the grid electrodes of other NMOS tubes are connected with the second power supply through switches, the output end of the auxiliary digital-to-analog converter AUX ADC correspondingly controls the switches corresponding to the grid electrodes of other NMOS tubes, and the second power supply is used for providing a second bias voltage nbias.
According to a second aspect of the present disclosure, there is provided an OIP3 calibration method of a radio frequency receiving system, the method comprising:
the radio frequency receiving end receives the frf signal and the flo signal;
the frf signal and the flo signal of the low noise amplifier LNA are mixed with preset frequency generated by a local oscillator LO in a Mixer to generate a-fif signal and a 0 signal, and the-fif signal and the 0 signal are modulated to generate third-order modulation signals-2 x fif and +fif, wherein flo-frf=fif;
the-fif signal, the 0 signal, the-2 x fif signal and the +fif signal pass through a polyphase filter PPF, an ERROR amplifier AMP and an auxiliary digital-to-analog converter AUX ADC to generate digital signals;
and controlling the resistance value of the negative resistance circuit according to the digital signal.
In the aspect and any possible implementation manner described above, there is further provided an implementation manner, where the generating the digital signal after the-fif signal, the 0 signal, -2 x fif signal, and the +fif signal pass through the polyphase filter PPF, the ERROR amplifier AMP, and the auxiliary digital-to-analog converter AUX ADC includes:
the-fif signal, the 0 signal, -2 x fif signal and the +fif signal are filtered by a polyphase filter PPF in a feedback loop to obtain the +fif signal;
the + fif signal is amplified by an ERROR amplifier ERROR AMP in the feedback loop and quantized by an auxiliary digital-to-analog converter AUX ADC in the feedback loop to generate a digital signal.
In the aspect and any possible implementation manner as described above, further providing an implementation manner, controlling, according to the digital signal, a resistance value of the negative resistance circuit includes:
and according to the digital signals, controlling the turn-off of corresponding MOS (metal oxide semiconductor) tubes in the variable P-tube current source and the variable N-tube current source, changing the current values in the variable P-tube current source and the variable N-tube current source, and controlling the resistance value of the negative resistance circuit by changing the current values.
It should be understood that what is described in this summary is not intended to limit the critical or essential features of the embodiments of the disclosure nor to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following description.
Drawings
The above and other features, advantages and aspects of embodiments of the present disclosure will become more apparent by reference to the following detailed description when taken in conjunction with the accompanying drawings. For a better understanding of the present disclosure, and without limiting the disclosure thereto, the same or similar reference numerals denote the same or similar elements, wherein:
fig. 1 is a schematic structural diagram of a radio frequency transceiver system according to an embodiment of the disclosure;
FIG. 2 is a schematic diagram of a negative resistance circuit according to an embodiment of the present disclosure;
fig. 3 is a schematic diagram of a variable P-tube current source and a variable N-tube current source according to an embodiment of the disclosure;
fig. 4 is a flowchart of an OIP3 calibration method of a radio frequency receiving system according to an embodiment of the present disclosure;
the device comprises a 1-radio frequency receiving end, a 2-low noise amplifier LNA, a 3-Mixer Mixer, a 4-transimpedance amplifier TIA, a 5-low pass filter LPF, a 6-variable gain amplifier PGA, a 7-digital-analog converter ADC, an 8-polyphase filter PPF, a 9-ERROR amplifier ERROR AMP and a 10-auxiliary digital-analog converter AUX ADC.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are some embodiments of the present disclosure, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments in this disclosure without inventive faculty, are intended to be within the scope of this disclosure.
In addition, the term "and/or" herein is merely an association relationship describing an association object, and means that three relationships may exist, for example, a and/or B may mean: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.
In the method for improving the OIP3 of the OPA in the prior art, the power supply voltage is improved, and a high-speed MOS tube has the risk of breakdown, so that the problem of reliability is solved; the current of OPA is increased, the power consumption is high, and the cost performance is low; and the low-voltage design technology is adopted, the gain is insufficient, multistage cascade compensation gain is needed, the bandwidth is reduced, and the area is increased.
In view of the above problems, the present disclosure provides a radio frequency receiving system and an output third-order intermodulation point OIP3 calibration method, where the system includes: a radio frequency receiving end 1, a low noise amplifier LNA2, a Mixer Mixer3, a local oscillator LO, a digital-to-analog converter ADC7, an operational amplifier OPA, a feedback circuit and a negative resistance circuit, wherein,
the operational amplifier OPA comprises a transimpedance amplifier TIA4, a low-pass filter LPF5 and a variable gain amplifier PGA6, the feedback circuit comprises a polyphase filter PPF8, an ERROR amplifier ERROR AMP9 and an auxiliary digital-to-analog converter AUX ADC10, and the negative resistance circuit comprises a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a variable P tube current source and a variable N tube current source; the negative resistance circuit is connected between the non-inverting input end and the inverting input end of the transimpedance amplifier TIA4, and the output end of the variable gain amplifier PGA6 is connected to the negative resistance circuit through the feedback circuit.
The digital signals output by the feedback loop control the turn-off of the corresponding MOS tube in the variable P-tube current source and the variable N-tube current source in the negative resistance circuit, change the current value of the negative resistance circuit, control the resistance value of the negative resistance circuit, and minimize the +fif signal generated by intermodulation, thereby achieving the purpose of calibrating OIP 3.
A radio frequency receiving system and an OIP3 calibration method of the system provided by the embodiments of the present disclosure are described in detail below with reference to the accompanying drawings by way of specific embodiments.
Fig. 1 shows a schematic structural diagram of a radio frequency receiving system in which an embodiment of the present disclosure can be implemented, as shown in fig. 1, the radio frequency receiving system includes:
a radio frequency receiving end 1, a low noise amplifier LNA2, a Mixer Mixer3, a local oscillator LO, a digital-to-analog converter ADC7, an operational amplifier OPA, a feedback circuit and a negative resistance circuit, wherein,
the operational amplifier OPA comprises a transimpedance amplifier TIA4, a low-pass filter LPF5, a variable gain amplifier PGA6, a feedback circuit comprises a polyphase filter PPF8, an ERROR amplifier ERROR AMP9 and an auxiliary digital-to-analog converter AUX ADC10, and a negative resistance circuit comprises a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a variable P tube current source and a variable N tube current source;
the negative resistance circuit is connected between the non-inverting input terminal and the inverting input terminal of the transimpedance amplifier TIA4, and the output terminal of the variable gain amplifier PGA6 is connected to the negative resistance circuit through a feedback circuit.
In some embodiments, the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, and the fourth MOS transistor M4 are cross-coupled MOS transistors.
In some embodiments, the non-inverting input of low noise amplifier LNA2 is connected to the radio frequency receiver; the first port of the Mixer Mixer3 is connected with the output end of the low noise amplifier LNA2, the second port is connected with the local oscillator LO, and the third port is connected with the input end of the transimpedance amplifier TIA 4; a negative resistance circuit is connected between the non-inverting input end and the inverting input end of the transimpedance amplifier TIA4, and the output end is connected with the input end of the low-pass filter LPF 5; the input end of the variable gain amplifier PGA6 is connected with the output end of the low-pass filter LPF5, and the output end is connected with the input end of the polyphase filter PPF8 and the input end of the digital-to-analog converter ADC 7; the input end of the ERROR amplifier ERROR AMP9 is connected with the output end of the polyphase filter PPF8, and the output end is connected with the input end of the auxiliary digital-to-analog converter AUX ADC 10; the output of the auxiliary digital-to-analog converter AUX ADC10 is connected to a negative resistance circuit.
Fig. 2 shows a schematic diagram of a negative resistance circuit provided by the embodiment of the disclosure, in which a negative resistance circuit is connected between a non-inverting input terminal and an inverting input terminal of a transimpedance amplifier TIA4, so as to cancel an original resistance, restore a virtual ground characteristic, and improve linearity.
As shown in fig. 2, the negative resistance circuit includes: the first MOS tube, the second MOS tube, the third MOS tube, the fourth MOS tube M4, the variable P tube current source and the variable N tube current source, wherein,
the drains of the first MOS tube M1 and the second MOS tube M2 are connected with the non-inverting input end of the transimpedance amplifier TIA 4; the drain electrodes of the third MOS tube M3 and the fourth MOS tube M4 are connected with the inverting input end of the transimpedance amplifier TIA 4;
the sources of the first MOS tube M1 and the third MOS tube M3 are connected with the drain electrode of the variable P tube current source; the source electrodes of the second MOS tube M2 and the fourth MOS tube M4 are connected with the drain electrode of the variable N-tube current source;
the grid electrodes of the first MOS tube M1 and the second MOS tube M2 are connected with the inverting input end of the transimpedance amplifier TIA 4; the grid electrodes of the third MOS tube M3 and the fourth MOS tube M4 are connected with the non-inverting input end of the transimpedance amplifier TIA 4; the source of the variable P-tube current source is connected with VDD, and the source of the variable N-tube current source is grounded.
In some embodiments, the first MOS transistor M1 and the third MOS transistor M3 are PMOS transistors, and the second MOS transistor M2 and the fourth MOS transistor M4 are NMOS transistors.
Fig. 3 shows a schematic structural diagram of a variable P-tube current source and a variable N-tube current source according to an embodiment of the disclosure.
As shown in fig. 3, taking the example that the variable P-tube current source includes 7 PMOS tubes P1-P7 and the variable N-tube current source includes 7 NMOS tubes N1-N7:
referring to fig. 2, the sources of P1-P7 are connected to VDD, the drains of P1-P7 are connected to the sources of the first MOS transistor M1 and the second MOS transistor M2, the gate of P1 is directly connected to the first power supply, the gates of P2-P7 are connected to the first power supply through switches, the output end of the auxiliary digital-to-analog converter AUX ADC10 is connected to the corresponding switches of the gates of P2-P7, and the first power supply is used for providing the first bias voltage pbias;
referring to fig. 2, the sources of N1-N7 are grounded, the drains of N1-N7 are connected to the sources of the second MOS transistor M2 and the fourth MOS transistor M4, the gate of N1 is directly connected to the bias power nbias, the gates of N2-N7 are connected to the bias power nbias through switches, the output end of the auxiliary digital-to-analog converter AUX ADC10 is connected to the corresponding switch of the gates of N2-N7, and the second power supply is used for providing the second bias voltage nbias.
In some embodiments, the on-off of corresponding switches in the PMOS transistors P2-P7 and the NMOS transistors N2-N7 are controlled respectively by the bit (0) -bit (5) multipath signals output by the auxiliary digital-to-analog converter AUX ADC10, so as to change the resistance values in the variable P-tube current source and the variable N-tube current source, and further change the currents in the variable P-tube current source and the variable N-tube current source.
The foregoing is a description of embodiments of the system, and the following further describes the aspects of the disclosure with reference to method embodiments.
Fig. 4 is a flowchart illustrating an OIP3 calibration method 400 of a radio frequency receiving system according to an embodiment of the disclosure.
In step S401, the rf receiving end receives the frf signal and the flo signal.
Step S402, after the frf signal and the flo signal of the low noise amplifier LNA2, the frf signal and the flo signal are mixed with a preset frequency generated by the local oscillator LO in the Mixer3 to generate a-fif signal and a 0 signal, and the-fif signal and the 0 signal are intermodulation to generate third-order modulated signals-2×fif and +fif, where flo-frf=fif.
Step S403, the +fif signal, and the 0 signal are passed through the polyphase filter PPF8, the ERROR amplifier AMP9, and the auxiliary digital-to-analog converter AUX ADC10 to generate digital signals.
Step S404, controlling the resistance of the negative resistance circuit according to the digital signal.
In some embodiments, the-2 x fif signal, the +fif signal, the-fif signal and the 0 signal are filtered when passing through the polyphase filter PPF8, and the +fif signal obtained after the filtering is sent to an error amplifier for amplification, and then quantized by an auxiliary digital-to-analog converter AUX ADC10 to generate a digital signal.
Further, the generated digital signal can be a 6bit signal, and the on-off of the MOS tube in the variable P tube current source and the variable N tube current source is controlled through the 6bit signal.
In some embodiments, according to the generated 6bit signal, the turn-off of the corresponding MOS transistor in the variable P-tube current source and the variable N-tube current source is controlled, specifically, as shown in fig. 3, bit (0), bit (1), bit (2), bit (3), bit (4), and bit (5) signals respectively control the switches corresponding to the gates in the PMOS transistor and the NMOS transistor, that is, the turn-off of the PMOS transistor in the variable P-tube current source and the NMOS transistor in the variable N-tube current source can be correspondingly controlled.
Furthermore, as the on-off of the corresponding PMOS tube and NMOS tube form a corresponding parallel circuit, the resistance values in the variable P tube current source and the variable N tube current source are changed, and the current in the variable P tube current source and the variable N tube current source is changed, so that the resistance value of the negative resistance circuit can be controlled.
According to the embodiment of the disclosure, the negative resistance circuit is connected between the non-inverting input end and the inverting input end of the transimpedance amplifier TIA4, and the feedback circuit is connected to the negative resistance circuit, so that the turn-off of the corresponding MOS (metal oxide semiconductor) tubes in the variable P-tube current source and the variable N-tube current source can be controlled according to the digital signal output by the feedback circuit, the current values of the variable P-tube current source and the variable N-tube current source in the negative resistance circuit are changed, the resistance value of the negative resistance circuit is controlled, the purpose of automatically calibrating the OIP3 is achieved, and the linearity of the radio frequency receiver is improved.
It should be noted that, for simplicity of description, the foregoing method embodiments are all described as a series of acts, but it should be understood by those skilled in the art that the present disclosure is not limited by the order of acts described, as some steps may be performed in other orders or concurrently in accordance with the present disclosure. Further, those skilled in the art will also appreciate that the embodiments described in the specification are all alternative embodiments, and that the acts and modules referred to are not necessarily required by the present disclosure.
It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps recited in the present disclosure may be performed in parallel, sequentially, or in a different order, provided that the desired results of the technical solutions of the present disclosure are achieved, and are not limited herein.
The above detailed description should not be taken as limiting the scope of the present disclosure. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present disclosure are intended to be included within the scope of the present disclosure.
Claims (7)
1. A radio frequency receiving system, the system comprising:
the radio frequency receiving end, the low noise amplifier LNA, the Mixer, the local oscillator LO, the operational amplifier OPA, the digital-to-analog converter ADC, the feedback circuit and the negative resistance circuit, wherein,
the operational amplifier OPA comprises a transimpedance amplifier TIA, a low-pass filter LPF and a variable gain amplifier PGA,
the feedback circuit comprises a polyphase filter PPF, an ERROR amplifier ERROR AMP and an auxiliary digital-to-analog converter AUX ADC,
the negative resistance circuit comprises a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a variable P tube current source and a variable N tube current source;
the non-inverting input end of the low noise amplifier LNA is connected with a radio frequency receiving end;
the first port of the Mixer is connected with the output end of the low noise amplifier LNA, the second port of the Mixer is connected with the local oscillator LO, and the third port of the Mixer is connected with the input end of the transimpedance amplifier TIA;
the non-inverting input end and the inverting input end of the transimpedance amplifier TIA are connected with the negative resistance circuit, and the output end of the transimpedance amplifier TIA is connected with the input end of the low-pass filter LPF;
the input end of the variable gain amplifier PGA is connected with the output end of the low-pass filter LPF, and the output end is connected with the input end of the polyphase filter PPF and the input end of the digital-to-analog converter ADC;
the input end of the ERROR amplifier ERROR AMP is connected with the output end of the polyphase filter PPF, and the output end of the ERROR amplifier ERROR AMP is connected with the input end of the auxiliary digital-to-analog converter AUX ADC;
the output end of the auxiliary digital-to-analog converter AUX ADC is connected with the negative resistance circuit.
2. The system of claim 1, wherein the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, and the fourth MOS transistor M4 are cross-coupled MOS transistors.
3. The system according to claim 1, characterized in that it comprises:
the drains of the first MOS tube M1 and the second MOS tube M2 are connected with the non-inverting input end of the transimpedance amplifier TIA;
the drains of the third MOS tube M3 and the fourth MOS tube M4 are connected with the inverting input end of the transimpedance amplifier TIA,
the sources of the first MOS tube M1 and the third MOS tube M3 are connected with the drain electrode of the variable P tube current source;
the sources of the second MOS tube M2 and the fourth MOS tube M4 are connected with the drain electrode of the variable N-tube current source,
the grid electrodes of the first MOS tube M1 and the second MOS tube M2 are connected with the inverting input end of the transimpedance amplifier TIA;
the grid electrodes of the third MOS tube M3 and the fourth MOS tube M4 are connected with the non-inverting input end of the transimpedance amplifier TIA,
and the source electrode of the variable P-tube current source is connected with VDD, and the source electrode of the variable N-tube current source is grounded.
4. A system according to claim 3, comprising:
the variable P-tube current source comprises a plurality of PMOS tubes which are arranged in parallel, the source electrodes of the PMOS tubes are connected with VDD, the drain electrodes of the PMOS tubes are connected with the source electrodes of the first MOS tube M1 and the third MOS tube M3, wherein the grid electrode of the first PMOS tube in the PMOS tubes is connected with a first power supply, the grid electrodes of other PMOS tubes are connected with the first power supply through switches, the output end of the auxiliary digital-to-analog converter AUX ADC correspondingly controls the switches corresponding to the grid electrodes of the other PMOS tubes, and the first power supply is used for providing a first bias voltage pbias;
the variable N-tube current source comprises a plurality of NMOS tubes which are arranged in parallel, the source electrodes of the NMOS tubes are grounded, the drain electrodes of the NMOS tubes are connected with the source electrodes of the second MOS tube M2 and the fourth MOS tube M4, the grid electrode of a first NMOS tube in the NMOS tubes is connected with a second power supply, the grid electrodes of other NMOS tubes are connected with the second power supply through switches, the output ends of the auxiliary digital-to-analog converter AUX ADC correspondingly control the switches corresponding to the grid electrodes of the other NMOS tubes, and the second power supply is used for providing a second bias voltage nbias.
5. A method for calibrating an output third-order intermodulation point OIP3 of a system according to any of the claims 1-4, said method comprising:
the radio frequency receiving end receives the frf signal and the flo signal;
through the frf signal and the flo signal of the low noise amplifier LNA, mixing with a preset frequency generated by the local oscillator LO in the Mixer to generate a-fif signal and a 0 signal, and intermodulation the-fif signal and the 0 signal to generate third-order modulation signals-2×fif and +fif, where flo-frf=fif;
the-fif signal, the 0 signal, the-2 x fif signal and the +fif signal pass through a polyphase filter PPF, an ERROR amplifier AMP and an auxiliary digital-to-analog converter AUX ADC to generate digital signals;
and controlling the resistance value of the negative resistance circuit according to the digital signal.
6. The method of claim 5, wherein the generating the digital signal after the-fif signal, the 0 signal, -2 x fif signal, and the +fif signal pass through the polyphase filter PPF, the ERROR amplifier AMP, and the auxiliary digital-to-analog converter AUX ADC comprises:
the-fif signal, the 0 signal, -2 x fif signal and the +fif signal are filtered by a polyphase filter PPF in the feedback circuit to obtain the +fif signal;
the +fif signal is amplified by an ERROR amplifier (ERROR AMP) in the feedback circuit and quantized by an auxiliary digital-to-analog converter (AUX ADC) in the feedback circuit to generate a digital signal.
7. The method of claim 5, wherein controlling the resistance of the negative resistance circuit according to the digital signal comprises:
and according to the digital signals, controlling the turn-off of corresponding MOS (metal oxide semiconductor) tubes in the variable P-tube current source and the variable N-tube current source, changing the current values in the variable P-tube current source and the variable N-tube current source, and controlling the resistance value of the negative resistance circuit by changing the current values.
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