CN115276690A - Radio frequency receiving system and output third-order intermodulation point OIP3 calibration method - Google Patents

Radio frequency receiving system and output third-order intermodulation point OIP3 calibration method Download PDF

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CN115276690A
CN115276690A CN202210665363.1A CN202210665363A CN115276690A CN 115276690 A CN115276690 A CN 115276690A CN 202210665363 A CN202210665363 A CN 202210665363A CN 115276690 A CN115276690 A CN 115276690A
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signal
variable
tube
input end
current source
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CN115276690B (en
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季晓燕
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Beijing Jun Microelectronics Technology Co ltd
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Beijing Jun Microelectronics Technology Co ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/16—Multiple-frequency-changing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/56—Modifications of input or output impedances, not otherwise provided for
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/193—High frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B17/00—Monitoring; Testing
    • H04B17/20—Monitoring; Testing of receivers
    • H04B17/21—Monitoring; Testing of receivers for calibration; for correcting measurements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/294—Indexing scheme relating to amplifiers the amplifier being a low noise amplifier [LNA]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Abstract

The embodiment of the disclosure provides a radio frequency receiving system and an output third-order intermodulation point OIP3 calibration method, and relates to the field of signal processing. The system comprises a radio frequency receiving end, a Low Noise Amplifier (LNA), a Mixer (Mixer), a Local Oscillator (LO), a digital-to-analog converter (ADC), an operational amplifier (OPA), a feedback circuit and a negative resistance circuit, wherein the operational amplifier (OPA) comprises a transimpedance amplifier (TIA), a low-pass filter (LPF) and a variable gain amplifier (PGA), and the negative resistance circuit comprises a first MOS (metal oxide semiconductor) transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a variable P-transistor current source and a variable N-transistor current source; and a negative resistance circuit is connected between the non-inverting input end and the inverting input end of the transimpedance amplifier TIA, and the output end of the variable gain amplifier PGA is connected to the negative resistance circuit through a feedback circuit. In this way, the problem of insufficient linearity in the radio frequency receiver can be solved, the automatic calibration of the OIP3 in the radio frequency receiver is realized, and the linearity of the radio frequency receiver is improved.

Description

Radio frequency receiving system and output third-order intermodulation point OIP3 calibration method
Technical Field
The present disclosure relates to the field of signal processing, and more particularly, to the field of radio frequency receiver technology.
Background
At present, there are three methods for improving the OIP3 of the OPA, the first method is to improve the supply voltage, and the supply voltage is improved to allow a larger input and output swing amplitude, so as to improve the OIP3, but the voltage cannot be arbitrarily improved, in order to pursue high-speed and large-bandwidth performance, the existing design increasingly adopts high-speed MOS transistors, and the high-speed MOS transistors have a risk of breakdown due to an excessively high supply voltage, so as to bring a problem of reliability, and the second method is to increase the current of the OPA, improve the driving capability of the OPA, so as to improve the OIP3, but the method has large power consumption and low cost performance; the third method adopts a low-voltage design technology, and has larger output swing amplitude under limited power supply voltage so as to improve the OIP3, and has the defects that the gain is insufficient, and multi-stage cascade compensation gain is needed, so that the bandwidth is reduced and the area is increased, and therefore, the existing method for improving the OIP3 of the operational amplifier OPA cannot meet the current requirement.
Disclosure of Invention
The utility model provides a radio frequency receiving system and output third-order intermodulation point OIP3 calibration method, insert the negative resistance circuit between the noninverting input end and the inverting input end of transimpedance amplifier TIA, offset original resistance, let the virtual ground characteristic resume, improve the linearity.
According to a first aspect of the present disclosure, there is provided a radio frequency receiving system, the system comprising:
a radio frequency receiving end, a low noise amplifier LNA, a Mixer Mixer, a local oscillator LO, a digital-to-analog converter ADC, an operational amplifier OPA, a feedback circuit and a negative resistance circuit, wherein,
the operational amplifier OPA comprises a transimpedance amplifier TIA, a low-pass filter LPF and a variable gain amplifier PGA, the feedback circuit comprises a polyphase filter PPF, an ERROR amplifier ERROR AMP and an auxiliary digital-to-analog converter AUX ADC, and the negative resistance circuit comprises a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a variable P tube current source and a variable N tube current source;
the negative resistance circuit is connected between the non-inverting input end and the inverting input end of the TIA, and the output end of the PGA is connected to the negative resistance circuit through the feedback circuit.
The above-mentioned aspects and any possible implementation manner further provide an implementation manner, where a non-inverting input terminal of the low noise amplifier LNA is connected to the radio frequency receiving terminal; a first port of the Mixer is connected with the output end of a Low Noise Amplifier (LNA), a second port of the Mixer is connected with a Local Oscillator (LO), and a third port of the Mixer is connected with the input end of a transimpedance amplifier (TIA); a negative resistance circuit is connected between the non-inverting input end and the inverting input end of the TIA, and the output end of the TIA is connected with the input end of the LPF; the input end of the variable gain amplifier PGA is connected with the output end of the low pass filter LPF, and the output end of the variable gain amplifier PGA is connected with the input end of the polyphase filter PPF and the input end of the digital-to-analog converter ADC; the input end of the ERROR amplifier ERROR AMP is connected with the output end of the multiphase filter PPF, and the output end of the ERROR amplifier ERROR AMP is connected with the input end of the auxiliary digital-to-analog converter AUX ADC; and the output end of the auxiliary digital-to-analog converter AUX ADC is connected with a negative resistance circuit.
The above aspect and any possible implementation manner further provide an implementation manner, where the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, and the fourth MOS transistor M4 are cross-coupled MOS transistors.
In the aspect and any possible implementation manner described above, an implementation manner is further provided, where drains of the first MOS transistor M1 and the second MOS transistor M2 are connected to a non-inverting input terminal of the transimpedance amplifier TIA; the drain electrodes of the third MOS tube M3 and the fourth MOS tube M4 are connected with the inverting input end of the TIA; the source electrodes of the first MOS tube M1 and the third MOS tube M3 are connected with the drain electrode of the variable P tube current source; the source electrodes of the second MOS tube M2 and the fourth MOS tube M4 are connected with the drain electrode of the variable N-tube current source; the grid electrodes of the first MOS tube M1 and the second MOS tube M2 are connected with the inverting input end of the TIA; the grid electrodes of the third MOS tube M3 and the fourth MOS tube M4 are connected with the in-phase input end of the TIA; the source electrode of the variable P tube current source is connected with VDD, and the source electrode of the variable N tube current source is grounded.
In accordance with the above-mentioned aspects and any possible implementation manner, there is further provided an implementation manner, in which the variable P-transistor current source includes a plurality of PMOS transistors arranged in parallel, sources of the plurality of PMOS transistors are connected to VDD, drains of the plurality of PMOS transistors are connected to sources of the first MOS transistor M1 and the third MOS transistor M3, wherein, the grid electrode of a first PMOS tube in the PMOS tubes is connected with a first power supply, the grid electrodes of other PMOS tubes are connected with the first power supply through switches, the output end of the auxiliary digital-to-analog converter AUX ADC correspondingly controls the corresponding switches of the grid electrodes of the other PMOS tubes, and the first power supply is used for providing a first bias voltage pbias;
the variable N-tube current source comprises a plurality of NMOS tubes arranged in parallel, the source electrodes of the NMOS tubes are grounded, the drain electrodes of the NMOS tubes are connected with the source electrodes of a second MOS tube M2 and a fourth MOS tube M4, the grid electrode of a first NMOS tube in the PMOS tubes is connected with a second power supply, the grid electrodes of other NMOS tubes are connected with the second power supply through switches, the output end of the auxiliary digital-to-analog converter AUX ADC correspondingly controls the switches corresponding to the grid electrodes of the other NMOS tubes, and the second power supply is used for providing a second bias voltage nbias.
According to a second aspect of the present disclosure, there is provided an OIP3 calibration method for a radio frequency reception system, the method including:
receiving the frf signal and the flo signal by a radio frequency receiving end;
the frf signal and the flo signal passing through a Low Noise Amplifier (LNA) are mixed with a preset frequency generated by a Local Oscillator (LO) in a Mixer to generate a-fif signal and a 0 signal, and the-fif signal and the 0 signal are subjected to intermodulation to generate third-order modulation signals-2 x fif and + fif, wherein flo-frf = fif;
the-fif signal, the 0 signal, -2 x fif signal and the + fif signal are processed by a multi-phase filter PPF, an ERROR amplifier ERROR AMP and an auxiliary digital-to-analog converter AUX ADC to generate digital signals;
and controlling the resistance value of the negative resistance circuit according to the digital signal.
The above-described aspect and any possible implementation further provide an implementation in which the-fif signal, the 0 signal, the-2 x fif signal, and the + fif signal are processed by the polyphase filter PPF, the ERROR amplifier ERROR AMP, and the auxiliary digital-to-analog converter AUX ADC to generate digital signals, including:
filtering the-fif signal, the 0 signal, -2 x fif signal and the + fif signal by a polyphase filter PPF in a feedback loop to obtain a + fif signal;
the + fif signal is amplified by an ERROR amplifier ERROR AMP in the feedback loop and quantized by an auxiliary digital-to-analog converter AUX ADC in the feedback loop to generate a digital signal.
The aspect described above and any possible implementation manner further provide an implementation manner, wherein controlling the resistance value of the negative resistance circuit according to the digital signal includes:
according to the digital signal, the turn-off of the corresponding MOS tube in the variable P tube current source and the variable N tube current source is controlled, the current values in the variable P tube current source and the variable N tube current source are changed, and the resistance value of the negative resistance circuit is controlled by changing the current values.
It should be understood that the statements herein reciting aspects are not intended to limit the critical or essential features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description.
Drawings
The above and other features, advantages and aspects of various embodiments of the present disclosure will become more apparent by referring to the following detailed description when taken in conjunction with the accompanying drawings. The accompanying drawings are included to provide a further understanding of the present disclosure, and are not intended to limit the disclosure thereto, and the same or similar reference numerals will be used to indicate the same or similar elements, where:
fig. 1 is a schematic structural diagram of a radio frequency transceiving system according to an embodiment of the present disclosure;
fig. 2 is a schematic diagram of a negative resistance circuit according to an embodiment of the disclosure;
fig. 3 is a schematic diagram of a variable P-transistor current source and a variable N-transistor current source according to an embodiment of the disclosure;
fig. 4 is a flowchart of an OIP3 calibration method of a radio frequency receiving system according to an embodiment of the present disclosure;
the system comprises a 1-radio frequency receiving end, a 2-low noise amplifier LNA, a 3-Mixer Mixer, a 4-transimpedance amplifier TIA, a 5-low pass filter LPF, a 6-variable gain amplifier PGA, a 7-digital-to-analog converter ADC, an 8-polyphase filter PPF, a 9-ERROR amplifier ERROR AMP and a 10-auxiliary digital-to-analog converter AUX ADC.
Detailed Description
To make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are some, but not all embodiments of the present disclosure. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.
In addition, the term "and/or" herein is only one kind of association relationship describing an associated object, and means that there may be three kinds of relationships, for example, a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
In the method for improving the OIP3 of the operational amplifier OPA in the prior art, the power supply voltage is improved, and the high-speed MOS tube has the risk of breakdown, thereby bringing the problem of reliability; the current of the OPA is increased, the power consumption is high, and the cost performance is low; and the low-voltage design technology is adopted, the gain is insufficient, multi-stage cascade compensation gain is needed, the bandwidth is reduced, and the area is increased.
In view of the above problems, the present disclosure provides a radio frequency receiving system and an output third-order intermodulation point OIP3 calibration method, where the system includes: a radio frequency receiving end 1, a low noise amplifier LNA2, a Mixer3, a local oscillator LO, a digital-to-analog converter ADC7, an operational amplifier OPA, a feedback circuit, and a negative resistance circuit, wherein,
the operational amplifier OPA comprises a transimpedance amplifier TIA4, a low-pass filter LPF5 and a variable gain amplifier PGA6, the feedback circuit comprises a multiphase filter PPF8, an ERROR amplifier ERROR AMP9 and an auxiliary digital-to-analog converter AUX ADC10, and the negative resistance circuit comprises a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a variable P tube current source and a variable N tube current source; the negative resistance circuit is connected between the non-inverting input end and the inverting input end of the transimpedance amplifier TIA4, and the output end of the variable gain amplifier PGA6 is connected to the negative resistance circuit through the feedback circuit.
The digital signal output by the feedback loop controls the turn-off of the corresponding MOS tube in the variable P tube current source and the variable N tube current source in the negative resistance circuit, changes the current value of the negative resistance circuit, controls the resistance value of the negative resistance circuit, and enables the + fif signal generated by intermodulation to be minimum, thereby achieving the purpose of calibrating the OIP 3.
A radio frequency receiving system and an OIP3 calibration method of the system provided by the embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.
Fig. 1 shows a schematic structural diagram of a radio frequency receiving system in which an embodiment of the present disclosure can be implemented, and as shown in fig. 1, the radio frequency receiving system includes:
a radio frequency receiving end 1, a low noise amplifier LNA2, a Mixer3, a local oscillator LO, a digital-to-analog converter ADC7, an operational amplifier OPA, a feedback circuit, and a negative resistance circuit, wherein,
the operational amplifier OPA comprises a trans-impedance amplifier TIA4, a low-pass filter LPF5 and a variable gain amplifier PGA6, a feedback circuit comprises a multiphase filter PPF8, an ERROR amplifier ERROR AMP9 and an auxiliary digital-to-analog converter AUX ADC10, and a negative resistance circuit comprises a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a variable P tube current source and a variable N tube current source;
and a negative resistance circuit is connected between the non-inverting input end and the inverting input end of the transimpedance amplifier TIA4, and the output end of the variable gain amplifier PGA6 is connected to the negative resistance circuit through a feedback circuit.
In some embodiments, the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, and the fourth MOS transistor M4 are cross-coupled MOS transistors.
In some embodiments, the non-inverting input terminal of the low noise amplifier LNA2 is connected to the radio frequency receiving terminal; a first port of the Mixer3 is connected with the output end of the low noise amplifier LNA2, a second port is connected with the local oscillator LO, and a third port is connected with the input end of the transimpedance amplifier TIA 4; a negative resistance circuit is connected between the non-inverting input end and the inverting input end of the transimpedance amplifier TIA4, and the output end of the transimpedance amplifier TIA4 is connected with the input end of the low-pass filter LPF 5; the input end of the variable gain amplifier PGA6 is connected with the output end of the low pass filter LPF5, and the output end is connected with the input end of the polyphase filter PPF8 and the input end of the digital-to-analog converter ADC 7; the input end of the ERROR amplifier ERROR AMP9 is connected with the output end of the polyphase filter PPF8, and the output end of the ERROR amplifier ERROR AMP9 is connected with the input end of the auxiliary digital-to-analog converter AUX ADC 10; the output of the auxiliary digital-to-analog converter AUX ADC10 is connected to a negative resistance circuit.
Fig. 2 shows a schematic diagram of a negative resistance circuit structure provided by an embodiment of the present disclosure, where a negative resistance circuit is connected between a non-inverting input terminal and an inverting input terminal of a transimpedance amplifier TIA4 to cancel an original resistance, recover a virtual ground characteristic, and improve linearity.
As shown in fig. 2, the negative resistance circuit includes: a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor M4, a variable P-transistor current source and a variable N-transistor current source,
the drain electrodes of the first MOS tube M1 and the second MOS tube M2 are connected with the non-inverting input end of the TIA 4; the drain electrodes of the third MOS tube M3 and the fourth MOS tube M4 are connected with the inverting input end of the transimpedance amplifier TIA 4;
the source electrodes of the first MOS transistor M1 and the third MOS transistor M3 are connected with the drain electrode of the variable P-tube current source; the source electrodes of the second MOS tube M2 and the fourth MOS tube M4 are connected with the drain electrode of the variable N-tube current source;
the grid electrodes of the first MOS tube M1 and the second MOS tube M2 are connected with the inverting input end of the transimpedance amplifier TIA 4; the grid electrodes of the third MOS tube M3 and the fourth MOS tube M4 are connected with the non-inverting input end of the TIA 4; the source electrode of the variable P tube current source is connected with VDD, and the source electrode of the variable N tube current source is grounded.
In some embodiments, the first MOS transistor M1 and the third MOS transistor M3 are PMOS transistors, and the second MOS transistor M2 and the fourth MOS transistor M4 are NMOS transistors.
Fig. 3 shows a schematic structural diagram of a variable P-transistor current source and a variable N-transistor current source provided by the embodiment of the disclosure.
As shown in fig. 3, for example, the variable P-transistor current source includes 7 PMOS transistors P1 to P7, and the variable N-transistor current source includes 7 NMOS transistors N1 to N7:
as can be seen from fig. 2, the sources of P1 to P7 are connected to VDD, the drains of P1 to P7 are connected to the sources of the first MOS transistor M1 and the second MOS transistor M2, the gate of P1 is directly connected to the first power supply, the gates of P2 to P7 are connected to the first power supply through switches, the output terminal of the auxiliary digital-to-analog converter AUX ADC10 is connected to the switches corresponding to the gates of P2 to P7, and the first power supply is configured to provide the first bias voltage pbias;
referring to fig. 2, the sources of N1-N7 are grounded, the drains of N1-N7 are connected to the sources of the second MOS transistor M2 and the fourth MOS transistor M4, the gate of N1 is directly connected to the bias power nbias, the gates of N2-N7 are connected to the bias power nbias through switches, the output terminal of the auxiliary digital-to-analog converter AUX ADC10 is connected to the switches corresponding to the gates of N2-N7, and the second power supply is used for providing the second bias voltage nbias.
In some embodiments, the on-off of the corresponding switches in the PMOS transistors P2-P7 and the NMOS transistors N2-N7 is controlled by bit (0) -bit (5) multi-path signals output by the auxiliary digital-to-analog converter AUX ADC10, respectively, so as to change the resistance values in the variable P-transistor current source and the variable N-transistor current source, and further change the currents in the variable P-transistor current source and the variable N-transistor current source.
The foregoing is a description of system embodiments, and the following is a further description of the aspects of the disclosure by way of method embodiments.
Fig. 4 shows a flowchart of an OIP3 calibration method 400 of a radio frequency receiving system according to an embodiment of the present disclosure.
In step S401, the rf receiving end receives the frf signal and the flo signal.
In step S402, the frf signal and the flo signal passing through the low noise amplifier LNA2 are mixed in the Mixer3 with the preset frequency generated by the local oscillator LO to generate a-fif signal and a 0 signal, and the-fif signal and the 0 signal are intermodulated to generate third-order modulation signals-2 × fif and + fif, where flo-frf = fif.
In step S403, the-2 × fif signal, the + fif signal, the-fif signal, and the 0 signal pass through the polyphase filter PPF8, the ERROR amplifier ERROR AMP9, and the auxiliary digital-to-analog converter AUX ADC10 to generate a digital signal.
And S404, controlling the resistance value of the negative resistance circuit according to the digital signal.
In some embodiments, the-2 × fif signal, the + fif signal, the-fif signal, and the 0 signal are filtered while passing through the polyphase filter PPF8, and the filtered + fif signal is sent to the error amplifier for amplification and then quantized by the auxiliary digital-to-analog converter AUX ADC10 to generate a digital signal.
Further, the generated digital signal can be a 6-bit signal, and the on-off of the MOS tube in the variable P tube current source and the variable N tube current source is controlled through the 6-bit signal.
In some embodiments, the turn-off of the corresponding MOS transistor in the variable P-transistor current source and the variable N-transistor current source is controlled according to the generated 6-bit signal, specifically, as shown in fig. 3, the signals of bit (0), bit (1), bit (2), bit (3), bit (4), and bit (5) respectively control the switches corresponding to the gates in the PMOS transistor and the NMOS transistor, that is, the turn-off of the PMOS transistor in the variable P-transistor current source and the NMOS transistor in the variable N-transistor current source can be correspondingly controlled.
Furthermore, due to the fact that the corresponding PMOS tube and the corresponding NMOS tube are connected in parallel, resistance values in the variable P tube current source and the variable N tube current source are changed, and then current in the variable P tube current source and the variable N tube current source is changed, and therefore the resistance value of the negative resistance circuit can be controlled.
According to the embodiment of the disclosure, the negative resistance circuit is connected between the in-phase input end and the anti-phase input end of the transimpedance amplifier TIA4, and the feedback circuit is connected to the negative resistance circuit, so that the turn-off of the corresponding MOS transistor in the variable P-tube current source and the variable N-tube current source can be controlled according to the digital signal output by the feedback loop, and the current values of the variable P-tube current source and the variable N-tube current source in the negative resistance circuit are changed, thereby controlling the resistance value of the negative resistance circuit, achieving the purpose of automatically calibrating the OIP3, and improving the linearity of the radio frequency receiver.
It is noted that while for simplicity of explanation, the foregoing method embodiments have been described as a series of acts or combination of acts, it will be appreciated by those skilled in the art that the present disclosure is not limited by the order of acts, as some steps may, in accordance with the present disclosure, occur in other orders and concurrently. Further, those skilled in the art should also appreciate that the embodiments described in the specification are exemplary embodiments and that acts and modules referred to are not necessarily required by the disclosure.
It should be understood that various forms of the flows shown above may be used, with steps reordered, added, or deleted. For example, the steps described in the present disclosure may be executed in parallel or sequentially or in different orders, and are not limited herein as long as the desired results of the technical solutions of the present disclosure can be achieved.
The above detailed description should not be construed as limiting the scope of the disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may be made in accordance with design requirements and other factors. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present disclosure should be included in the scope of protection of the present disclosure.

Claims (8)

1. A radio frequency receiving system, the system comprising:
a radio frequency receiving end, a low noise amplifier LNA, a Mixer Mixer, a local oscillator LO, a digital-to-analog converter ADC, an operational amplifier OPA, a feedback circuit and a negative resistance circuit, wherein,
the operational amplifier OPA comprises a transimpedance amplifier TIA, a low-pass filter LPF and a variable gain amplifier PGA,
the feedback circuit comprises a polyphase filter PPF, an ERROR amplifier ERROR AMP and an auxiliary digital-to-analog converter AUX ADC,
the negative resistance circuit comprises a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a variable P tube current source and a variable N tube current source;
the negative resistance circuit is connected between the non-inverting input end and the inverting input end of the TIA, and the output end of the PGA is connected to the negative resistance circuit through the feedback circuit.
2. The system of claim 1, comprising:
the non-inverting input end of the low noise amplifier LNA is connected with a radio frequency receiving end;
a first port of the Mixer is connected with an output end of the low noise amplifier LNA, a second port of the Mixer is connected with the local oscillator LO, and a third port of the Mixer is connected with an input end of the TIA;
the negative resistance circuit is connected between the non-inverting input end and the inverting input end of the TIA, and the output end of the TIA is connected with the input end of the LPF;
the input end of the variable gain amplifier PGA is connected with the output end of the low pass filter LPF, and the output end of the variable gain amplifier PGA is connected with the input end of the polyphase filter PPF and the input end of the digital-to-analog converter ADC;
the input end of the ERROR amplifier ERROR AMP is connected with the output end of the multiphase filter PPF, and the output end of the ERROR amplifier ERROR AMP is connected with the input end of the auxiliary digital-to-analog converter AUX ADC;
and the output end of the auxiliary digital-to-analog converter AUX ADC is connected with the negative resistance circuit.
3. The system according to claim 1, wherein the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, and the fourth MOS transistor M4 are cross-coupled MOS transistors.
4. The system of claim 1, comprising:
the drain electrodes of the first MOS tube M1 and the second MOS tube M2 are connected with the non-inverting input end of the TIA;
the drains of the third MOS transistor M3 and the fourth MOS transistor M4 are connected to the inverting input terminal of the transimpedance amplifier TIA,
the source electrodes of the first MOS tube M1 and the third MOS tube M3 are connected with the drain electrode of the variable P tube current source;
the sources of the second MOS transistor M2 and the fourth MOS transistor M4 are connected with the drain of the variable N-transistor current source,
the grid electrodes of the first MOS tube M1 and the second MOS tube M2 are connected with the inverting input end of the TIA;
the grid electrodes of the third MOS transistor M3 and the fourth MOS transistor M4 are connected with the non-inverting input end of the TIA,
the source electrode of the variable P-tube current source is connected with VDD, and the source electrode of the variable N-tube current source is grounded.
5. The system of claim 4, comprising:
the variable P-tube current source comprises a plurality of PMOS tubes arranged in parallel, the source electrodes of the PMOS tubes are connected with VDD, the drain electrodes of the PMOS tubes are connected with the source electrodes of the first MOS tube M1 and the third MOS tube M3, the grid electrode of the first PMOS tube in the PMOS tubes is connected with a first power supply, the grid electrodes of the other PMOS tubes are connected with the first power supply through switches, the output end of an auxiliary digital-to-analog converter AUX ADC controls the switches corresponding to the grid electrodes of the other PMOS tubes correspondingly, and the first power supply is used for providing a first bias voltage pbias;
the variable N-tube current source comprises a plurality of NMOS tubes arranged in parallel, the source electrodes of the NMOS tubes are grounded, the drain electrodes of the NMOS tubes are connected with the source electrodes of the second MOS tube M2 and the fourth MOS tube M4, the grid electrode of the first NMOS tube in the NMOS tubes is connected with a second power supply, the grid electrodes of the other NMOS tubes are connected with the second power supply through switches, the output end of the auxiliary digital-to-analog converter AUX ADC correspondingly controls the switches corresponding to the grid electrodes of the other NMOS tubes, and the second power supply is used for providing a second bias voltage nbias.
6. Method for calibrating the output third order intermodulation point OIP3 of a system according to any of claims 1-5, characterized in that it comprises:
receiving the frf signal and the flo signal by a radio frequency receiving end;
the frf signal and the flo signal passing through the low noise amplifier LNA are mixed with a preset frequency generated by the local oscillator LO in the Mixer to generate a-fif signal and a 0 signal, and the-fif signal and the 0 signal are intermodulated to generate third-order modulation signals-2 x fif and + fif, wherein flo-frf = fif;
the-fif signal, the 0 signal, -2 x fif signal and the + fif signal are processed by a multi-phase filter PPF, an ERROR amplifier ERROR AMP and an auxiliary digital-to-analog converter AUX ADC to generate digital signals;
and controlling the resistance value of the negative resistance circuit according to the digital signal.
7. The method of claim 6, wherein the-fif signal, the 0 signal, -2 x fif signal, and the + fif signal are processed by a polyphase filter (PPF), an ERROR amplifier (ERROR AMP), and an auxiliary digital-to-analog converter (AUX ADC) to generate digital signals, and the method comprises:
the-fif signal, the 0 signal, -2 x fif signal and the + fif signal are filtered by a polyphase filter PPF in the feedback loop to obtain a + fif signal;
the + fif signal is amplified by an ERROR amplifier ERROR AMP in the feedback loop and quantized by an auxiliary digital-to-analog converter AUX ADC in the feedback loop to generate a digital signal.
8. The method of claim 6, wherein controlling the resistance of the negative resistance circuit according to the digital signal comprises:
according to the digital signal, the turn-off of the corresponding MOS tube in the variable P tube current source and the variable N tube current source is controlled, the current values in the variable P tube current source and the variable N tube current source are changed, and the resistance value of the negative resistance circuit is controlled by changing the current values.
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