JP2006352184A - Signal delay transmission circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a delay signal sequence of a time interval shorter than the shortest delay transmission time of a signal transmission element or a delay time variable transmission element, and solve a disadvantage of the obtained delay signal sequence. <P>SOLUTION: A plurality of signal transmission elements having a different delay time and a plurality of delay time variable transmission elements having a different delay time are combined and used, and this enables obtaining the delay signal sequence of the time interval shorter than the shortest delay transmission time of the signal transmission element or the delay time variable transmission element. However, the disadvantage in which an initial delay output is more than the shortest delay transmission time of the signal transmission element or the delay time variable transmission element is solved by delaying a signal related to the delay signal sequence similarly to a new time reference signal. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a signal transmission delay element circuit that outputs a delay signal sequence having an extremely short time interval.

  In today's signal recording devices, where the recording density is extremely high, recording with a laser beam or the like focused on a recording medium causes the light energy to affect not only the recording point but also the vicinity of the recording point. The emitted laser beam signal is not recorded on the medium in the form of a signal level waveform, resulting in a different recording result, and a defective phenomenon occurs such that the reproduced signal is different from the recording signal and high-density recording cannot be realized. In order to remedy this problem, the output level and emission time of the laser light signal during recording are determined by the values of the previous and subsequent signals, the signal to be recorded, the format of the recording medium, the material of the recording medium, the moving speed of the recording medium, etc. A correction method has been devised and has been put to practical use in recordable CD recorders and recordable DVD recorders.

  Recently, due to demands for improved convenience and time efficiency, shortening the recording time has become an important issue for recordable CD recorders and recordable DVD recorders, and how many times the standard playback speed can be recorded. It is one of the largest elements of judgment indicators. In order to realize high-speed recording in response to this, it is indispensable to realize a high-speed control response performance of a mechanism and an optical device, improve a signal frequency that can be used by a recording electronic circuit, and realize a high-speed response performance.

  In order to reduce the power consumption and product price of the recording apparatus, it is not optimal to use an unconditionally expensive and high-speed semiconductor material or an expensive and high-speed state-of-the-art manufacturing process. It is necessary to use inexpensive semiconductor materials and manufacturing processes that are currently most widely used. However, a signal delay transmission circuit that outputs a delayed signal sequence of an extremely short time interval required by a near-recording effect correction modulation signal generation circuit in a recording laser light driving signal generation unit that requires the fastest signal is usually used. It is difficult to obtain with cascaded signal transmission elements, and variable delay time transmission is required to generate the above-mentioned delayed signal sequence so as to correspond to changes in the relative speed between the recording medium and the laser light signal irradiation recording point. It is indispensable to use the element, but in the delay time variable transmission element created by the most widely used inexpensive semiconductor material and manufacturing process, the time interval of the delay signal sequence that requires the shortest delay transmission time Therefore, it is impossible to obtain the required delay signal string by simply cascading delay time variable transmission elements.

Usually, this countermeasure includes the use of expensive, high-speed semiconductor materials and faster variable delay time transmission elements created using expensive, high-speed, advanced manufacturing processes at the expense of reduced power consumption and product price. By simply cascading, a delay signal sequence having a required time interval was created. Or, by creating a variable delay time transmission element using the cheapest semiconductor materials and manufacturing processes currently in widespread use and simply cascading them, the required high-speed recording can be given up to reduce power consumption and product price. The reduction was ensured.
JP 2004-159161 A

  The problem to be solved is to obtain a delay signal sequence having a time interval shorter than the shortest delay transmission time of the signal transmission element or the variable delay time transmission element.

  The main feature of the present invention is to use a plurality of signal transmission elements having different delay times or a plurality of variable delay time transmission elements having different delay times.

  Since the signal delay transmission circuit of the present invention can obtain a delay signal sequence having a time interval shorter than the shortest delay transmission time of the signal transmission element and variable delay time transmission element, semiconductor materials and manufacturing processes that are widely used at present Can be used, and there is an advantage that the required high-speed recording can be realized simultaneously with reduction of power consumption and product price.

  Even when using widely used semiconductor materials and manufacturing processes without using expensive and high-speed semiconductor materials that lead to increased power consumption and product price, and expensive and high-speed cutting-edge manufacturing processes It was possible to generate a delayed signal sequence with extremely short time intervals, and realized the minimum power consumption and product price.

FIG. 2 is an embodiment of the apparatus of the present invention, and is a circuit connection diagram of a configuration in the case of n = 1 in claim 3. Reference numeral 1 denotes a first signal transmission element, and reference numeral 2 denotes a first signal transmission element array in which the first signal transmission elements are connected in cascade.
Signals and clocks are input to the input terminal 3 of the first signal transmission element array and taken out from the first signal transmission element cascade connection point 4 and the output terminal 5.
The transmission delay time of the first signal transmission element when n = 1 is 2d,
A signal delayed by an integer multiple of 2d is extracted from 4 and 5.
On the other hand, as shown in FIG. 2, the second signal transmission element 6 is connected to the input terminal 3 of the first signal transmission element array 2 and the first signal transmission element cascade connection point 4. The transmission delay time of the second signal transmission element when n = 1 is 3d, and a signal delayed by an integral multiple of 3d is extracted from the output terminal 7 of the second signal transmission element.
As can be seen from FIG. 2, in the embodiment of FIG. 2, the signal transmission element array 2d or the like obtained by cascading the first signal transmission element 1 or the second signal transmission element 6 alone or the like. It is possible to extract a signal or a clock signal sequence delayed by a time interval of a difference in transmission delay time between the first signal transmission element 1 and the second signal transmission element 6 which is a time interval of half or one third of 3d. .
As a result, the delay was delayed by an extremely short time interval shorter than the transmission delay time limit of the signal transmission element, which could not be realized by the conventional method, such as cascade connection of one type of signal delay transmission element shown in FIG. Signals and clock signal trains can be extracted.

FIG. 3 shows a configuration connection example of a transmission delay time variable element used as a signal transmission element for varying the transmission delay time according to claim 5.
The variable transmission delay time element is composed of an inverting amplifier (called an inverter) 10 and 11 made of a CMOS transistor or the like connected in series, a current source 14 for supplying a power supply current, and capacitive loads 12 and 13 of the inverter. The
In FIG. 3, the power source current is supplied to the inverters 10 and 11 by the current source 14 in which the maximum drive current IMAX is variable at the control terminal CTL, but the power source current is supplied to each of 10 and 11 by two independent current sources. The same is true.
When the inverters 10 and 11, the capacitive loads 12 and 13, and the signal value identification voltage Vrefr at the time of voltage rise are determined in the circuit of FIG. 3, the maximum power supply current IMAX (referred to as the maximum drive current) that can be supplied by the current source 14 Eleven output voltage rise times and voltage rise transmission delay times Tdr are determined, which are represented by FIGS.
On the other hand, the output voltage drop time and the voltage drop transmission delay time Tdf are determined by the element resistance (Vss side conduction) Rf, capacitive load 12, power supply voltage Vdd, voltage drop signal value identification voltage Vreff, etc. It is represented by FIG. 3, FIG.
3 and 4, inverting amplifiers (referred to as inverters) 10 and 11 are connected in series to form one transmission delay time variable element, so the delay time when the output voltage rises in the previous stage is the output voltage drop in the subsequent stage. The input / output transmission delay time Td of one element added to the time delay time is symmetrical with Tdr + Tdf when the output voltage rises and falls.

FIG. 5 is an embodiment of the device of the present invention, and is a circuit connection diagram of the configuration in the case of n = 1 in claim 4. Reference numeral 1 denotes a first signal transmission element, and reference numeral 2 denotes a first signal transmission element array in which the first signal transmission elements are connected in cascade.
Signals and clocks are input to the input terminal 3 of the first signal transmission element array and taken out from the first signal transmission element cascade connection point 4 and the output terminal 5.
The transmission delay time of the first signal transmission element when n = 1 is 3d,
A signal delayed by an integer multiple of 3d from 4 and 5 is extracted.
On the other hand, as shown in FIG. 5, the second signal transmission element array in which the second signal transmission elements 6 are cascade-connected is the input terminal 3 of the first signal transmission element array 2 and the first signal transmission element cascade connection. Connected to point 4. The transmission delay time of the second signal transmission element when n = 1 is 2d, and a signal delayed by an integral multiple of 3d is extracted from the output terminals 7 and 8 of the second signal transmission element.
In the embodiment of FIG. 5, 2d or a half or a third of 2d or 3d obtained by a signal transmission element array formed by cascading the first signal transmission element 1 or the second signal transmission element 6 alone or the like. It is possible to extract a signal or a clock signal sequence delayed by the time interval of the difference between the transmission delay times of the first signal transmission element 1 and the second signal transmission element 6 which is the time interval of
As a result, the delay was delayed by an extremely short time interval shorter than the transmission delay time limit of the signal transmission element, which could not be realized by the conventional method, such as cascade connection of one type of signal delay transmission element shown in FIG. Signals and clock signal trains can be extracted.

FIG. 6 shows a configuration connection example of a transmission delay time variable element used as a signal transmission element that varies the transmission delay time according to claim 5.
The variable transmission delay time element consists of a differential inverting amplifier (called a differential inverter) 10 and 11 made of a CMOS transistor or the like connected in series, and a current source 14 for supplying power supply current and a differential inverter. Consists of capacitive loads 12 and 13.
When the differential inverters 10 and 11, the capacitive loads 12 and 13, and the signal value identification voltage Vrefr at the time of voltage rise are determined in the circuit of FIG. 6, the maximum power supply current IMAX (referred to as the maximum drive current) that can be supplied by the current source 14 The output voltage rise time and the voltage rise transmission delay time Tdr of the differential inverters 10 and 11 are determined, which are represented by FIGS.
The output voltage drop time and the voltage drop transmission delay time Tdf are the maximum power supply current IMAX (referred to as the maximum drive current) that can be supplied by the current source 14 when the capacitive load 12, power supply voltage Vdd, voltage drop signal value identification voltage Vreff, etc. are determined. ), Which is also represented by FIGS.
Here, the maximum drive current IMAX of the current source 14 on the Vdd side and the maximum drive current IMAX of the current source 14 on the Vss side are equal, and amplification of the Vdd side amplification element and the Vss side amplification element of the differential inverters 10 and 11 is performed. When the rate and driving force are the same, the voltage rise characteristics vs. time voltage drop characteristics are symmetrical and Vrefr and Vreff are approximately equal to the center potential of Vdd and Vss, so Tdr and Tdf are equal and the two-stage differential inverter So Td = Tdr + Tdf =
2Tdr = 2Tdf.
In the same manner as described in (0011), the signal delay transmission circuit shown in claim 4 and claim 5 using the transmission delay time variable element shown in FIG. It is possible to take out a signal or a clock signal sequence that is variably delayed at an extremely short time interval that is shorter than the transmission delay time limit of the variable transmission delay time element, which could not be realized by the conventional method using the To do.
6 and 7, a differential inverting amplifier (referred to as a differential inverter) 10 and 11 is connected in series to form one transmission delay time variable element, but the output voltage rises even in a single stage. Since the time delay time and the output voltage drop delay time can be made symmetric, the transmission delay time variable element can be configured in a single stage.
Furthermore, the influence of the noise on the power supply Vdd, Vss and the differential inverter input, which affects the delay time, has the characteristic that the effects on the + side and-side cancel each other out. Can be avoided.
The signal delay transmission circuit of the present invention shown in claim 4 and claim 5 using the transmission delay time variable element shown in FIG. 6 cannot be realized by the conventional method FIG. 1 etc. It is possible to extract a signal and a clock signal train that are variably delayed at an extremely short time interval shorter than the delay time limit with almost no influence of noise.

Claim 1 shows a case where the transmission delay times of the first and second signal transmission elements of Claims 3 and 4 are set freely without being fixed to a specific relationship. As a result, a signal delay transmission circuit that outputs a signal sequence delayed by a time interval corresponding to the difference between the transmission delay times of the first and second signal transmission elements set freely can be obtained.
Claim 2 shows a case where the number of types of signal transmission elements having different transmission delay times in claim 1 is increased. As a result, a signal delay transmission circuit that outputs a signal sequence delayed by a time interval corresponding to a difference in transmission delay times of a large number of signal transmission elements can be obtained.

Claim 6 is designed such that the internal circuit of the element as shown in FIGS. 3 and 5 or the capacitance value of the capacitive load C in the element is different, or the signal transmission element and the variable transmission delay time element are designed in an IC or the like. Transmission delay time by making the capacitance value of the capacitive load C, which is produced in the manufacturing process and derived from the insulating part and the conductive part or region, different depending on the length, area, number, thickness, etc. A plurality of types of signal transmission elements and transmission delay time variable elements different from each other.
An example of this is that a variable capacitor used by reverse biasing the PN junction is used to vary the area, number, and voltage, and change the voltage to apply to a variable transmission delay time element.

According to the seventh aspect of the present invention, impedance elements such as resistors and inductances having different values are inserted in series in the element internal circuit of the signal transmission element and the transmission delay time variable element or the output of the element, and the transmission delay time differs depending on the capacitive load component To obtain a plurality of types of signal transmission elements and transmission delay time variable elements.
This is made in the process of designing and manufacturing a signal transmission element and a variable transmission delay time element in an IC etc., and includes derived impedance elements such as different resistances and inductances, and includes length, area, number, thickness, etc. It also includes obtaining a plurality of types of signal transmission elements and transmission delay time variable elements having different transmission delay times by making them different.
Capacitive load components are produced in the process of designing and manufacturing signal transmission elements and variable transmission delay time elements in ICs, etc., and are derived from capacitive parts due to parts that have conductivity and parts that have conductivity. A load is also included, and a plurality of types of signal transmission elements and transmission delay time variable elements having different transmission delay times can be obtained by changing the length, area, number, thickness, and the like simultaneously with the impedance element.

Claim 8 is to obtain a plurality of types of signal transmission elements and transmission delay time variable elements having different transmission delay times by varying the element internal circuit of the signal transmission element and the transmission delay time variable element or the load driving capability of the element. .
This can also be obtained by making the element internal circuits of the signal transmission element and the variable transmission delay time element or the length, area, number, etc. of the elements different.

  Claim 9 uses the current source 14 that can vary the maximum drive current IMAX as shown in the examples of FIGS. 3 and 5 as the power source of the element or the internal circuit of the element, and the driving force of the current source 14 is determined by the length, area, It is to obtain a plurality of types of signal transmission elements and transmission delay time variable elements having different transmission delay times by varying the number, thickness, etc., or by controlling them to different values with the control terminal CTL.

  Claim 10 is to obtain a plurality of types of signal transmission elements and transmission delay time variable elements having different transmission delay times by varying the input signal value identification levels of the signal transmission elements and the transmission delay time variable elements. It is.

  Claim 11 is a level comparator with different input signal value identification levels attached to the signal transmission element and the transmission delay time variable element, and a plurality of types having different transmission delay times depending on areas such as elements and ICs having the same function The signal transmission element and the transmission delay time variable element are obtained.

Claim 12 uses a signal delay transmission circuit created or configured by the method of claim 1 to claim 11 to “Delay Locked”.
"Loop circuit" (hereinafter referred to as DLL circuit).

As shown in FIG. 8, one embodiment of claim 12 includes a CLOCK input to the input terminal 24 of the variable transmission delay time signal delay transmission circuit and a predetermined loop.
The transmission delay output 26 delayed by 2nd, which is the delay, is input to the reference (REF) input terminal 29 and the comparison (COMP) input terminal 30 of the phase comparator 21, respectively, and the output 31 of the phase comparator 21 is input to the charge pump 22 and the phase. The DLL 23 is configured by generating the control signal 32 by the compensator 23 and inputting the control signal 32 to the transmission delay time variable control input terminal 28 of the transmission delay time variable signal delay transmission circuit 20.
Here, the first transmission delay output 25 of the variable transmission delay time signal delay transmission circuit has a transmission delay time of 2d with respect to CLOCK which is a signal of the input terminal 24, and does not satisfy the required time interval d.

  Therefore, claim 13 uses the first transmission delay output 25 as the time reference signal instead of the input signal CLOCK, and extends the transmission delay output that was originally 2nd delayed transmission delay output 26 by 2d (2n +2) By generating and using up to d output 27, a transmission delay output sequence is obtained.

In another embodiment of the present invention, as shown in FIG. 9, the first transmission delay output 25 in which the CLOCK inputted to the input terminal 24 of the variable transmission delay time signal delay transmission circuit is delayed by 2d, and further the Loop Delay amount. The delayed (2n + 2) d transmission delay output 27 is input to the reference (REF) input terminal 29 and the comparison (COMP) input terminal 30 of the phase comparator 21, respectively, and the output 31 of the phase comparator 21 is connected to the charge pump 22 and The phase compensator 23 generates the control signal 32 and inputs it to the transmission delay time variable control input terminal 28 of the transmission delay time variable signal delay transmission circuit 20 to constitute a DLL circuit.
Here, the first transmission delay output 25 of the variable transmission delay time signal delay transmission circuit has a transmission delay time of 2d with respect to CLOCK which is a signal of the input terminal 24, and does not satisfy the required time interval d.

  Here, the transmission delay time variable signal delay transmission circuit outputs 25, 26, 27 and the like are the same as those in the fourth embodiment, and as described in claim 13, the first transmission delay output 25 is used as a time reference signal to extend 2d. Up to (2n + 2) d output 27 is used as a transmission delay output string.

  Since the delay signal sequence of the signal delay transmission circuit created by the method of claims 1 to 13 is used in claim 14, the delay signal is delayed because the first delay signal output is delayed from the required time interval. As a result of having to use any one of the signals as a new time reference signal, the signal used in combination with the delayed signal sequence of the signal delay transmission circuit is changed in some way to the original time reference signal or time reference signal. The delay time is the same as the delay time of the new time reference signal with respect to the clock.

  Claim 15 is one of the methods for realizing Claim 14. A new time reference using the same time reference signal or time reference clock as the transmission element or circuit or the transmission delay time variable element or circuit that generated the new time reference signal of the delay signal sequence under the same conditions. This is delayed in the same way as the signal, and is given as a clock for a register composed of D-type flip-flops (hereinafter referred to as DFF), and the signal used in combination with the delay signal sequence is delayed by this register in the same way as a new time reference signal Means things.

As an embodiment of claim 15, the Laser shown in FIG.
An application example to the Driver drive signal generation circuit will be described.
PCK is a time reference clock 46 of the system, and its frequency changes depending on the recording speed of the optical recording apparatus.
The DLL 36 applies a time delay of the PCK period to the transmission delay time variable element array of the DLL loop, and generates a delay signal string 50 having a time interval corresponding to the change of the PCK.
Write DATA 51 is the original DATA of the signal to be recorded, but the signal 54 generated by the encoder encoder 41, the register 41, and the decoder decoder 42 in order to improve the influence caused by the energy that the laser beam gives to the recording medium during recording. And the delay signal sequence 50 generated by DLL36 is shaped into a laser driver drive signal 58 with the output level and output time corrected using Matrix 37, and in addition to Laser Driver 38, the output level and light emission of the laser 39 optical signal Correct the time.

The delay signal string 50 is a clock having a frequency half that of the time reference clock 46 generated by inputting the CLOCK 47 obtained by dividing the PCK system time reference clock 46 by the frequency divider 35 by the frequency divider 35 into the DLL 36 for the convenience of signal generation. . The new time reference in the delayed signal train is also a clock having a frequency half that of the time reference clock 46.
Therefore, this new time reference signal 48 cannot be used as a delay clock for the decoder decoder output 54.
Therefore, PCK46 is delayed by the same time as the new time reference signal 48 using the same circuit 44 and variable CTL transmission delay time control signal 49 as the signal delay time variable transmission circuit that generates the new time reference signal 48, and is configured by DFF etc. By using it as the clock 56 of the registered register 43, a signal 55 obtained by delaying the Decoder output 54 with the new time reference signal 48 is generated.
The signal 55 and the delay signal sequence 50 which is the output signal of the DLL are shaped by the Matrix 37 to generate a laser driver drive signal 58.
The frequency divider 35 has a negative clock input because the timing of the new time reference signal 48 and clock 56 conflicts with the signal 42 of the decoder 42 generated using the system time reference clock 46. This is to prevent the register 43 constituted by DFF or the like from malfunctioning with a ½ clock shift.

  Claim 16 is one of the methods for realizing Claim 14. A new time reference signal in the delay signal sequence and another signal in the delay signal sequence are shaped by a combinational logic circuit such as EXOR, which is equivalent to the original time reference clock being delayed by the same time as the new time reference signal. The signal is supplied as a clock of a register composed of a D-type flip-flop, and the signal used in combination with the delay signal sequence is delayed by the same time as the new time reference signal.

As an embodiment of claim 16, the Laser shown in FIG.
An application example to the Driver drive signal generation circuit will be described.
PCK is a time reference clock 46 of the system, and its frequency changes depending on the recording speed of the optical recording apparatus.
The DLL 36 applies a time delay of the PCK period to the transmission delay time variable element array of the DLL loop, and generates a delay signal string 50 having a time interval corresponding to the change of the PCK.
Write DATA 51 is the original DATA of the signal to be recorded, but the signal 54 generated by the encoder encoder 41, the register 41, and the decoder decoder 42 in order to improve the influence caused by the energy that the laser beam gives to the recording medium during recording. And the delay signal sequence 50 generated by DLL36 is shaped into a laser driver drive signal 58 with the output level and output time corrected using Matrix 37, and in addition to Laser Driver 38, the output level and light emission of the laser 39 optical signal Correct the time.

The delay signal string 50 is a clock having a frequency half that of the time reference clock 46 generated by inputting the CLOCK 47 obtained by dividing the PCK system time reference clock 46 by the frequency divider 35 by the frequency divider 35 into the DLL 36 for the convenience of signal generation. . A new time reference signal in the signal sequence obtained by delaying the signal is also a signal having a frequency half that of the time reference clock 46.
Therefore, this new time reference signal 48 cannot be used as a delay clock for the decoder decoder output 54.
Therefore, the new time reference signal 48 and another signal 49 in the delayed signal sequence are shaped by a combinational logic circuit 45 such as EXOR, and the original time reference clock 46 is delayed by the same time as the new time reference signal 48. The clock signal is equivalent to
The clock signal 57 is given as a clock of the register 43 configured by DFF or the like, and the signal 55 used in combination with the delay signal sequence is delayed by the same time as the new time reference signal 48 by the register 43 configured by DFF or the like. .
The delayed signal 55 and the delayed signal string 50, which is the output signal of the DLL, are shaped using the Matrix 37 to generate a laser driver drive signal 58.
The frequency divider 35 has a negative clock input because the timing of the clock signal 57 equivalent to the PCK delayed by the same time as the new time reference signals 48 and 48 is generated using the system time reference clock 46. This is to prevent the register 43 constituted by DFF and the like from malfunctioning due to timing conflict with the signal 54 of the decoder 42, which is shifted by 1/2 clock.
FIG. 12 shows an example of a combinational logic circuit equivalent to EXOR.
FIG. 13 is a timing chart of PCK 46, CLOCK 47, new time reference signal 48, and clock signal 57 equivalent to PCK delayed by the same time as other signals 49, 48 in the delayed signal train.

  It can be applied not only to high-speed optical recording devices but also to a wide range of applications such as high-speed semiconductor memory control circuits and high-speed signal waveform generators.

The connection diagram of the signal delay transmission circuit by one type of signal delay transmission element. (Conventional example 1) The signal delay transmission circuit connection diagram of this invention. (Example 1) The block diagram of the transmission delay time variable element of this invention. (Example 2) FIG. 6 is a time vs. voltage change diagram for explaining the operation of the variable transmission delay time element used in the present invention. (Example 2) The signal delay transmission circuit connection diagram of this invention. (Example 3) The block diagram for operation | movement description of the transmission delay time variable element used for this invention. (Example 3) FIG. 6 is a time vs. voltage change diagram for explaining the operation of the variable transmission delay time element used in the present invention. (Example 3) The Delay Locked Loop circuit connection diagram of the present invention. Example 4 The Delay Locked Loop circuit connection diagram of the present invention. (Example 5) The laser driver signal generation circuit connection diagram of this invention. (Example 6) The laser driver signal generation circuit connection diagram of this invention. (Example 7) Circuit example equivalent to EXOR circuit. (Example 7) Timing diagram of double frequency clock generation by an EXOR circuit equivalent circuit. (Example 7)

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 1st signal transmission element 2 Signal transmission element cascade connection point 3 1st signal transmission element row | line | column 4 Input of signal delay transmission circuit 5 Output of signal delay transmission circuit 6 Second signal transmission element input 7 Second signal transmission Element output 8-No. 9-No. 10 Inverting amplifier (inverter) in the previous stage that constitutes variable transmission delay time element
11 Inverting amplifier (inverter) in the latter stage that constitutes a variable transmission delay time element
12 Capacitive load of the previous stage constituting variable transmission delay time element C
13 Capacitive load of the latter stage constituting the variable transmission delay time element C
14 Maximum drive current variable current source (IMAX)
15 Transmission delay time variable element signal input (IN)
16 Transmission delay time variable element signal output (OUT)
17 Maximum drive current variable control input (CTL)
18-No. 19-No. 20 Transmission delay time variable signal delay transmission circuit 21 Phase comparator (PHC)
22 Charge pump (CP)
23 Filter (LPF)
24 Transmission Delay Time Variable Signal Delay Transmission Circuit Signal Input 25 Transmission Delay Time Variable Signal Delay Transmission Circuit First Delay Signal Output (Time Reference Signal)
26 Transmission Delay Time Variable Signal Delay Transmission Circuit 2nd Delay Signal Output 27 Transmission Delay Time Variable Signal Delay Transmission Circuit (2n + 2) d Delay Signal Output 28 Transmission Delay Time Variable Control Input 29 Phase Comparator (PHC) Reference Signal Input (REF)
30 Phase comparator (PHC) comparison signal input (COMP)
31 Phase comparator (PHC) output 32 Transmission delay time variable control signal 33-No. 34-No. 35 Divider 36 Delay Locked Loop circuit (DLL)
37 Laser Driver Drive Signal Generation Matrix Circuit (Matrix)
38 Laser Driver
39 Laser 40 Encoder
41 Register
42 Decoder
43 Register composed of D-type flip-flop (DFF), etc. 44 Same circuit as variable signal delay time transmission circuit that generates new time reference signal 48 45 Combination logic circuit such as EXOR 46 Time reference clock (PCK) of system
47 System time base clock (PCK) divided by 2 (CLOCK)
48 A new time reference signal with a delay time 2d in the delay CLOCK signal sequence of time interval d corresponding to the change of PCK 49 A signal of the delay time n + 1d in the delay CLOCK signal sequence of time interval d corresponding to the change of PCK 50 Delayed clock signal sequence with time interval d corresponding to PCK change 51 Original DATA (Write DATA) of recorded signal
52 Encoder Output 53 Register Output 54 Decoder Output Signal 55 Output 56 of Register Registered by DFF etc. Signal delayed by the same time as the new time reference signal (configured by DFF etc.) Registered clock)
57 Clock signal equivalent to PCK46 delayed by the same time as the new time reference signal 48 (register clock composed of DFF, etc.)
58 Laser Driver Drive Signal 59 Laser Driver Output Signal

Claims (16)

  A second signal transmission element having a transmission delay time different from that of the first signal transmission element at the signal input / output point and the signal transmission element cascade connection point in the first signal transmission element row in which the first signal transmission elements are cascaded. Alternatively, the second signal transmission element array in which the second signal transmission elements are cascade-connected is connected, and the signal output point of the second signal transmission element or the signal output point of the second signal transmission element array and the signal transmission element cascade connection are connected. A signal delay transmission circuit for taking out a signal from a point and simultaneously taking out and outputting a signal from a signal input / output point and a signal transmission element cascade connection point of the first signal transmission element row, When outputting only the signal extracted from the signal input / output point and the signal transmission element cascade connection point, or using the second signal transmission element instead of the first signal transmission element to create a signal transmission element array The delay of the time interval that is the difference between the transmission delay times of the first signal transmission element and the second signal transmission element, which is a shorter time interval than when only the signal extracted from the point and the signal transmission element cascade connection point is output A signal delay transmission circuit that outputs a signal train.   In the first signal transmission element array in which the first signal transmission elements are cascade-connected, a second signal transmission element or a second signal transmission element having a transmission delay time different from that of the signal transmission element is connected to the signal input / output point and the signal transmission element cascade connection point. A third or a plurality of types of signal transmission elements having different transmission delay times, including a first signal transmission element and a second signal transmission element, connected to a second signal transmission element array in which the signal transmission elements are cascade-connected. A signal delay transmission circuit formed by connecting the first signal transmission element array, the second signal transmission element array, and the other signal transmission element array in the same manner as the second signal transmission element, The signal is extracted from the signal output point of the plurality of signal transmission elements including two or the signal output point of the signal transmission element array and the cascade connection point of the signal transmission elements, and is output, thereby causing a difference in transmission delay time of the plurality of signal transmission elements. Signal delay transmission circuit for outputting a delay signal sequence between intervals.   In the signal transmission element array in which the first signal transmission elements are cascade-connected, when the delay time of the first signal transmission element is 2d at the signal input / output point and the signal transmission element cascade connection point, the delay time is approximately d × ( 2n + 1) a second signal transmission element connected to a second signal transmission element or a second signal transmission element cascade in which the second signal transmission elements are connected to each other, where n is a positive integer of 1 or more. The signal was taken out from the signal output point or the signal output point of the second signal transmission element array and the signal transmission element cascade connection point, and taken out from the signal input / output point and signal transmission element cascade connection point of the first signal transmission element string A signal delay transmission circuit that, when used together with a signal, outputs a delayed signal sequence with a shorter time interval than when only the signal extracted from the signal input / output point and the signal transmission device cascade connection point of the first signal transmission device row is used. .   In the signal transmission element array in which the first signal transmission elements having a delay time of approximately d × (2n + 1) “n is a positive integer greater than or equal to 1” are cascaded, signal input / output points and signal transmission element cascade connection points Is connected to the second signal transmission element or the second signal transmission element string in which the second signal transmission elements are cascade-connected, and the signal output point of the second signal transmission element or the second signal A signal is taken out from the signal output point of the transmission element row and the signal transmission element cascade connection point, and used together with the signal taken out from the signal input / output point and the signal transmission element cascade connection point of the first signal transmission element row, the first Signal transmission element array when using only the signal taken out from the signal input / output point and signal transmission element cascade connection point of the signal transmission element array, or when using the second signal transmission element instead of the first signal transmission element Signal input / output points And a signal delay transmission circuit for outputting a delayed signal sequence having a shorter time interval than when only the signal extracted from the signal transmission element cascade connection point is used.   5. The signal delay transmission circuit according to claim 1, wherein the first signal transmission element and the second signal transmission element are variable transmission delay time elements.   In claim 1, claim 2, claim 3, claim 4, and claim 5, loading an output with an element having a different capacity or an element having a different capacity as a partial element to the output, Alternatively, a signal delay transmission circuit using the first signal transmission element and the second signal transmission element in which the difference in the transmission delay time is determined by the electric capacitive load having different sizes generated in the process of manufacturing and configuring the transmission element .   In claim 1, claim 2, claim 3, claim 4, claim 5 and claim 6, elements or regions having different or both of electrical resistance and electrical inductivity, or the like, or As an element, a region or the like having an electrical resistance of a different size as an element or a region or the like having either or both of a different size of electrical resistance and a different size of electrical inductivity. A first signal transmission element in which a difference in transmission delay time is determined by loading an element or region having electrical capacitance as a sub-element or by an electric capacitive load generated in the process of manufacturing and configuring the transmission element And a signal delay transmission circuit using the second signal transmission element.   In claim 1, claim 2, claim 3, claim 4, claim 5, claim 6 and claim 7, the difference in transmission delay time is determined by using transmission drive elements having different drive capabilities. A signal delay transmission circuit using one signal transmission element and a second signal transmission element.   Claim 1, claim 2, claim 3, claim 4, claim 5, claim 6, claim 7 and claim 8, an element, device or element for supplying a power supply voltage or power supply current to a transmission drive element The first signal transmission element and the second signal transmission element were used to determine the difference in transmission delay time by changing the environment that affects the driving capability of the transmission drive element, such as the device setting conditions and control conditions. Signal delay transmission circuit.   Claim 1, claim 2, claim 3, claim 4, claim 5, claim 6, claim 7, claim 8, and claim 9, wherein different signal value identification voltage or signal value identification current levels are input. A signal delay transmission circuit using a first signal transmission element and a second signal transmission element in which a difference in transmission delay time is determined by using a transmission element or a region having a part or a region.   In claim 1, claim 2, claim 3, claim 4, claim 5, claim 6, claim 7, claim 8, 9 and 10, signal value identification voltage or signal value identification current The difference in transmission delay time is determined by using buffer amplifiers having different levels of input units, level comparators having different signal value identification voltages or signal value identification current levels, or elements and regions having the same function. A signal delay transmission circuit using one signal transmission element and a second signal transmission element.   Any one output in the delayed signal train of the signal delay transmission circuit using the method of claim 5, claim 6, claim 7, claim 8, claim 9, claim 10 and claim 11, and DLL configured by inputting one of the other outputs in the delay signal sequence different from the output of one of the delayed signal sequences or the input signal of the signal delay transmission circuit to the phase comparator. "Delay Locked Loop" circuit.   13. A signal delay transmission circuit that outputs any one of the delay signal sequences of the signal delay transmission circuit using the method according to claim 1 as a temporal reference signal together with other delay signal sequences.   In an apparatus using the delayed signal sequence output of the signal delay transmission circuit, the reference signal or delay of the delayed signal sequence generated by using the method of claims 1 to 13 for generating the signal delay transmission circuit or delayed signal sequence output Add the same time delay as the signal delay to the signal of the circuit or device that uses the delayed signal sequence output before, after, in the middle, inside the circuit, etc. As a result, a circuit and a device in which the original time reference signal or the reference clock of the device using the delayed signal sequence output and the problem due to the time signal and the delayed signal sequence output signal being shifted are eliminated. Using the same signal transmission element, transmission delay time variable element, circuit and transmission delay time variable control signal as the signal delay transmission circuit used for generating the temporal reference signal of the delay signal string that is the signal delay transmission circuit output signal, To generate a signal or clock obtained by delaying the original temporal reference signal or reference clock of the device using the delayed signal train output of the signal delay transmission circuit in the same manner as the temporal reference signal of the delayed signal train.
Giving this clock as a clock to a register composed of a D-type flip-flop and the like and a circuit and a device using the clock.
Thus, a time delay similar to the temporal reference signal of the delay signal sequence is added to the signal of the circuit or device using the delay signal sequence output, and the circuit and device using the same. Any one of the time reference signal of the delay signal train that is the signal delay transmission circuit output signal and the other signal delay transmission circuit output signal, for example, using a combinational logic circuit such as exclusive OR (EXOR) And generating a clock in which the rising edge and the falling edge of the temporal reference signal of the delay signal sequence are edges in the same direction. The combinational logic circuit or the like is not specified.
Giving this clock as a clock to a register composed of a D-type flip-flop and the like and a circuit and a device using the clock.
Thus, a time delay similar to the temporal reference signal of the delay signal sequence is added to the signal of the circuit or device using the delay signal sequence output, and the circuit and device using the same.

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