JP2000163999A - Self-timing control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the adjusted phase of a timing clock, generated by a self-timing control circuit using a DLL circuit, from varying from its optimum value due to manufacturing variance. SOLUTION: This self-timing control circuit is provided with a variable dummy load 7, which is electrically adjustable in capacity load instead of a dummy load which has its capacity load fixed. In a wafer testing process of a device, the capacity load of the variable dummy load 7 can be adjusted to its optimum value. The capacity load of the variable dummy load 7 adjusted to the optimum value has a set value fixed in the programmable memory of a fuse, etc. Consequently, variation in dummy load capacity load due to the variance of manufacture can be corrected, and the phase adjustment of a clock generator can be made more accurately.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a self-timing control circuit for generating a timing clock having a predetermined phase relationship with an external clock, and in particular, to preventing a desired phase relationship from being obtained due to manufacturing variations. The present invention relates to a self-timing control circuit.

[0002]

2. Description of the Related Art Synchronous DRAMs (SDRAMs)
An integrated circuit device that inputs an input signal and outputs an output signal in synchronization with an external clock can operate at high speed. Such an integrated circuit device inputs and outputs a signal in synchronization with a rising edge of an external clock. Conventionally, an external clock is used as it is as an internal timing clock. However, as the frequency of the clock increases, the clock propagation delay time inside the integrated circuit device cannot be ignored.

Therefore, it has been proposed that a high-speed integrated circuit device such as an SDRAM is provided with a self-timing control circuit for generating a timing clock having the same phase as an external clock or a predetermined phase relationship. This self-timing control circuit
For example, it is configured by a DLL (Delay Locked Loop) circuit.

FIG. 1 is a diagram showing a configuration example of a self-timing control circuit using a conventional DLL circuit. In this DLL circuit, the external clock signal CLK is
Captured by the input buffer 1, the internal clock CLK
1 is supplied to the variable delay circuit 2. Variable delay circuit 2
, The timing clock CLK2 is generated by delaying by a delay time controlled according to the frequency of the clock. The output buffer 3 uses the timing clock C
Output data DATA from the internal circuit in synchronization with LK2
Is output to the output terminal Dout.

On the other hand, the internal clock CLK1 is
And the frequency is divided by 1 / N. The divided reference clock signal c-clk is supplied to the variable delay circuit 5 and, at the same time, is supplied as a first input c-clk of the phase comparator. Clock signal CLK output from variable delay circuit 5
3 is supplied as a second input di-clk of the phase comparator 9 via an additional fixed delay circuit group including a dummy output buffer 6, a fixed dummy load 7, and a dummy input buffer 8.

The phase comparator 9 compares the phases of two input signals, and outputs comparison results φR and φS to the delay control circuit 10. The delay control circuit 10 adjusts the delay amounts of the two variable delay circuits 2 and 5 according to the phase comparison result so that the phases of both input signals match.

As a result, the delay amount of the variable delay circuit 2 is controlled so that the output timing of the output data output from the output buffer 3 matches the timing of the external clock. The above-mentioned DLL circuit has been disclosed by the present applicant in, for example, Japanese Patent Application Laid-Open No. H10-112182 (April 28, 1998).
Public).

In an actual integrated circuit device, an output terminal Dout
Has an external capacitance load Co of about 50 pF. The external capacitance load Co is, for example, a wiring capacitance on a motherboard on which the integrated circuit device is mounted. Therefore, the switching timing of the output data signal output from the output buffer 3 in synchronization with the timing clock CLK2 depends on the external capacitive load Co.

In order to make the phase of the output clock CLK4 of the dummy output buffer 6 coincide with the phase of the output signal Dout, a fixed dummy load 7 is provided at the output stage of the dummy output buffer 6 in the feedback loop of the DLL circuit. Can be The capacity load of this dummy load 7 is
The clock CLK4 is set so as to be equivalent to the output waveform of the output terminal Dout when the external capacitive load Co actually exists. By performing the phase adjustment using the reproduced output waveform, the output data D is output at the output terminal Dout.
ATA switching timing and external clock signal CLK
Can be more accurately matched with the rising edge of.

[0010]

As described above, in the prior art, a dummy load 7 having a fixed capacitive load is provided in a delay circuit of a DLL circuit in consideration of an external capacitive load connected to an output terminal Dout. . However, the capacitance load of the dummy load 7 may fluctuate from the set value due to manufacturing variations of the integrated circuit device or the like. For example, when the dummy load 7 is configured by a resistance element or a capacitor element, it varies due to manufacturing variations. Since there is no means for correcting the fluctuation in such a case, the phase adjustment in the DLL circuit cannot be performed accurately. As a result, the output terminal Dou
The switching timing of the waveform of the data output signal at t differs from the rising edge of the external clock signal CLK.

Further, there is a case where an external capacitance load connected to the output terminal Dout is required to have a different value depending on a device. In such a case, the dummy load 7 having a fixed capacitance load cannot cope with such a different external capacitance load.

An object of the present invention is to provide a DLL circuit that can generate a timing clock having a desired phase in accordance with the cycle of an external clock without being affected by manufacturing variations.

A further object of the present invention is to provide a self-timing control circuit capable of generating a timing clock whose delay amount is adjusted in accordance with the frequency of an external clock without being affected by manufacturing variations. .

It is a further object of the present invention to provide a DLL circuit or a self-timing control circuit that can set an optimum capacitive load for a dummy load in accordance with manufacturing variations.

[0015]

In order to achieve the above object, a self-timing control circuit according to the present invention comprises:
Instead of a dummy load having a fixed capacity load, a variable dummy load capable of electrically adjusting the capacity load is provided.
According to the present invention, in the device wafer testing process,
The capacity load of the variable dummy load can be adjusted to an optimum value. The set value of the variable dummy load set to the optimum value is fixed in a programmable memory such as a fuse. This makes it possible to correct a change in the dummy load capacity load due to a manufacturing variation or the like, and to more accurately perform the phase adjustment in the clock generator.

[0016] To achieve the above object, the present invention provides:
In a self-timing control circuit for generating a timing clock having a predetermined phase relationship with the supplied clock by delaying the supplied clock, the supplied clock is input, and a delay amount controlled according to the frequency of the supplied clock. A first variable delay circuit for delaying the supply clock only, and an additional delay connected to the first variable delay circuit for delaying the supply clock by a predetermined delay amount set regardless of the frequency of the supply clock. And the additional delay circuit has a variable dummy load in which the delay amount is variably set, and the delay amount of the variable dummy load is variably set by a programmable memory that sets the delay amount. Features.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. However, such embodiments do not limit the technical scope of the present invention.

FIG. 2 is a diagram showing an embodiment of the present invention. The self-timing control circuit shown in FIG. 2 has the same configuration as that of the conventional example shown in FIG. 1, and corresponding parts are denoted by the same reference numerals. That is, the clock CLK supplied from the outside is taken in by the input buffer 1,
The clock CLK1 is input to the second variable delay circuit 2,
The timing clock CLK2 delayed according to the clock frequency is supplied to the output buffer 3. The output buffer 3 outputs output data DATA from an output terminal Dout in synchronization with the timing clock CLK2. An external capacitive load Co is connected to the output terminal.

The timing of the timing clock CLK2 is controlled by the following DLL circuit. That is, the DLL circuit uses the reference clock c-clk obtained by dividing the internal clock CLK1 by the frequency divider 4. Reference clock c
-clk is delayed by the delay amount controlled by the first variable delay circuit 5. The delayed clock CLK3 further passes through an additional delay circuit including a dummy output buffer 6, a variable dummy load 7, and a dummy input buffer 8, and is supplied to the phase comparator 9 as a variable clock di-clk. .
The dummy output buffer 6 has a delay time equivalent to that of the output buffer 3, and the dummy input buffer 8 has a delay time equivalent to that of the clock input buffer 1.

The operation of this DLL circuit is the same as in the conventional example. As will be apparent from the detailed description described later, the delay amount of the first and second variable delay circuits 5 and 2 is controlled according to the frequency or cycle of the clock CLK. Further, the positions of the dummy output buffer 6 and the variable dummy load 7 can be provided before the first variable delay circuit 5 or can be provided after the dummy input buffer 8.

The self-timing control circuit of the present embodiment is configured such that the magnitude of the capacitive load of the variable dummy load 7 can be changed and set by the program circuit 11. That is, by storing a predetermined set value in a programmable memory in the program circuit 11, the variable dummy load 7 is stored in accordance with the corresponding set signals Fi and Ei.
Can be variably set. By changing and setting the capacity load of the variable dummy load 7,
The delay amount of the clock CLK4 is changed and set. As described in the related art, even if the value of the capacitive load of the dummy load 7 fluctuates due to manufacturing variations, the phase of the timing clock CLK2 when the DLL circuit is locked on in the test mode after manufacturing is detected. By doing
The capacity load of the variable dummy load 7 can be variably set so that the phase is set to an optimum timing.

[Configuration Example of Variable Dummy Load (1)] FIG.
FIG. 4 is a diagram showing a configuration example of a first variable dummy load.
The variable dummy load 7 includes a variable resistor Rp connected in series between the dummy output buffer 6 and the dummy input buffer 8,
And a capacitor Cp connected between the output side of the variable resistor Rp and the ground electrode. The resistance value of the variable resistor Rp is controlled by the program circuit 11 via a control signal Fi, as described later. The capacitor Cp can use the parasitic capacitance of the wiring.

The program circuit 11 includes a register circuit 32 for setting a control signal Fi of a resistance value from an external terminal, a programmable memory circuit 30 including a fuse for fixedly setting the control signal Fi of a resistance value, and a register circuit 32. And a switching circuit 33 for switching between the settings from the programmable memory circuit 30.

The variable resistor Rp in the variable dummy load 7 is changed and set via the register circuit 32 in the program circuit 11, and an optimum resistance value of the variable resistor Rp is detected. After that, in order to fixedly set the variable resistor Rp to the optimum resistance value, the set value is recorded in the programmable memory 30. Then, during normal operation, the control signal Fi is supplied by the switching circuit 33 according to the set value recorded in the programmable memory 30, and the resistance value of the variable resistor Rp is set.

FIG. 4 is a diagram showing a configuration example of the variable resistor Rp. As shown in FIG. 4, the variable resistor Rp includes a plurality of switches S0 to Sn and a plurality of resistors R1 to Rn having the same resistance value. The switches S0 to Sn are turned on / off by load control signals F0 to Fn respectively supplied from the switching circuit 33.
Controlled off. The plurality of switches S0 to Sn are configured by CMOS transfer gates as shown in FIG. Only one of the load control signals F0 to Fn is set to the L level, and the corresponding switch is turned on (conduction state). If the load control signal Fi is set to L level, the resistance value of the variable resistor Rp is set to Rp = R1 + R2 +... + Ri. Therefore, by selecting this load control signal Fi, the resistance value of the variable resistor Rp can be adjusted. The temperature dependence of the resistance value can be reduced by using polysilicon as the material of the resistors R1 to Rn.

FIG. 5 is a diagram showing a configuration example (1) of the program circuit 11. Program circuit 11 of this configuration example
Selects a signal set by the register 32 or the fuse 30 by the switching circuit 33 and outputs a load control signal F0
FF2 is supplied to the variable resistor Rp. FIG. 6 exemplarily shows only the 3-bit load control signals F0 to F2.

When adjusting the capacitive load of the variable dummy load 7 in the wafer test process of the device, the register 3
Generating load control signals F0 to F2 based on the signal from
The timing of the output signal generated at the output terminal Dout when the DLL circuit locks on is compared with the timing of the external clock CLK. That is, external input signals A0 to A2 such as address signals are supplied to the register 32. At this time, when a positive pulse signal is input as the first test signal TEST1, the transfer gates 321 to
323 is turned on, and the external input signals A0 to A2
It is supplied to the switching circuit 33 through 4-326. Thereafter, the transfer gates 331 to 331 in the switching circuit
By setting the second test signal TEST2 input to 36 to the H level, the signal latched in the register 32 is selected, and the load control signals F0 to F2 are supplied to the variable resistor Rp of the variable dummy load. .

By setting any of the external input signals A0 to A2 to the H level, any of the load control signals F0 to F2 is set to the L level, and any of the switches of the variable resistor Rp shown in FIG. S0 to Sn can be made conductive. as a result,
The variable resistance Rp can be set to an arbitrary resistance value.

By using this program circuit, in the test mode, the resistance value of the variable resistor Rp of the variable dummy load 7 is variably set from an external input signal via the register circuit 32, and the optimum value corresponding to the manufacturing variation is obtained. Capacitive load can be detected.

Then, the set value for obtaining the optimum capacitance load detected in this way is recorded in the programmable memory 30 composed of the fuse element. As a result, in the normal operation mode, by setting the second test signal TEST2 to L level, one of the load control signals F0 to F2 is set to L level according to the signal recorded in the programmable memory 30, and the optimum load The capacity is set in the variable dummy load 7.

FIG. 6 is a diagram showing a configuration example (2) of the program circuit 11. Program circuit 11 of this configuration example
As in the case of FIG. 5, a signal set by the register 32 or the fuse 30 is selected by the switching circuit 33 and supplied to the variable resistor Rp as load control signals F0 to F2. However, in the configuration example of FIG.
Inverters 338-340 and a plurality of decode lines 345
And a decode circuit including NAND gates 341 to 343 to which a combination of the decode lines 345 is input.

The decode circuit decodes a 3-bit input signal from the register 32 or the programmable memory circuit 30, and generates 8-bit load control signals F0 to F7. As in the case of FIG. 5, the 8-bit load control signals F0 to
Only one of the F7s is set to the L level and supplied to the variable resistor Rp in the variable dummy load 7. By changing the external input signals A0 to A2 input to the register as binary numbers, the load control signals F0 to F7 can be sequentially changed to L level, and the capacity load of the variable dummy load 7 can be adjusted. .

FIG. 7 is a flowchart for setting the optimum capacity load of the variable dummy load 7 by using the above-mentioned program circuit 11. First test signal TEST
1 is set to the H level (S10), and the external input signals A0 to A2 are latched by the latch circuits 324 to 326 in the register circuit 32 (S12). Then, the first test signal TEST1 is set to L
Level, the switches 321 to 323 are turned off, the second test signal TEST2 is set to the H level, and the switches 332, 334, 3 in the switching circuit 33 are set.
36 are turned on (S14). as a result,
The signals set in the register circuit 32 are load control signals F0 to F0.
As F7, it is supplied to the variable resistor Rp in the variable dummy load 7, and the variable resistor Rp is set to a predetermined resistance value.

Therefore, the self-timing control circuit is operated in the test mode (S16). In this test mode operation, output data DATA is alternately changed to H level and L level. In that case, the reference clock c-cl
k and the phase of the variable clock di-clk almost coincide, and the DLL
In a state where the circuit is locked on, when the switching timing of the data output waveform coincides with the rising edge of the external clock signal CLK, the capacitance load of the variable dummy load 7 becomes an optimum value. Therefore, it is checked whether the output waveform generated at the output terminal Dout is output at the correct timing (S18). If they do not match, the variable resistor R
Change the set value of p and repeat the same test.

The above steps S10 to S18 are repeated until the switching timing of the output waveform generated at the output terminal coincides with the rising edge of the external clock CLK. Then, when it is detected that they match, the corresponding fuses FS0 to FS2 are cut off based on the signal levels of the external input signals A0 to A2 set in the register circuit 32 at that time (S20).

Thereafter, by setting the second test signal TEST2 to L level, the input signal from the fuse is selected, and the capacitance load of the variable dummy load is fixed to the optimum value.

[Configuration Example of Variable Dummy Load (2)] FIG.
FIG. 4 is a diagram showing a configuration example (2) of a variable dummy load. The variable dummy load 7 includes a resistor Rp connected in series between the dummy output buffer 6 and the dummy input buffer 8, and a variable capacitor Cp connected between the output side of the resistor Rp and the ground electrode. The capacitance value of the variable capacitor Cp is controlled by the program circuit 11 via a load control signal φp, as described later. As for the resistance Rp, the parasitic resistance of the existing wiring can be used.

FIG. 9 is a diagram showing a configuration example of the variable capacitor Cp. As shown in FIG.
p denotes a plurality of switches S0 to Sm and a plurality of capacitors C0
To Cm are connected in parallel and configured. The capacitance values of the capacitors C0 to Cm are C0: C1: C2 ... =
It is set to a value weighted sequentially like 1: 2: 4.
The switches S0 to Sn are configured by CMOS transfer switches as in the case of FIG. 4, and are turned on / off by load control signals E0 to Em supplied from a program circuit, respectively. As in the case of FIG. 4, the switch corresponding to the load control signal set to the L level is turned on.

In this variable capacitor, by changing the combination of the load control signals E0 to Em set to the L level, the capacitance value of the variable capacitor Cp can be finely adjusted and set to the optimum value. For example, the load control signal E0
When only the switch is set to the L level, only the switch S0 conducts, and the capacitance value of the variable capacitor Cp becomes C0. When only the load control signal E1 is set to the L level, only the switch S1 is turned on, and the capacitance value of the variable capacitor Cp becomes C1 = 2C0.
When both the load control signals E0 and E1 are set to L level,
Both the switches S0 and S1 conduct, and the capacitance value of the variable capacitor Cp becomes C0 + C1 = 3C0. In this way, by connecting the weighted capacitors in an appropriate combination, it is possible to set an arbitrary capacitance value.

Also in the case of the variable dummy load described above, the program circuit 11 can detect and set the optimum value of the capacitive load by the same circuit as that shown in FIGS. However, since the capacitors are weighted, the number of necessary load control signals can be reduced as compared with the case of the variable dummy load shown in FIGS.

The variable dummy load 7 has a configuration example shown in FIGS.
The variable resistor in (1) and the variable capacitor in the configuration example (2) in FIGS. 8 and 9 can be combined. The basic configuration and operation are the same as the configuration example (1) and the configuration example (2). In this case, each resistance value and capacitance value can be set so that, for example, the variable resistor is used for coarse adjustment and the variable capacitor is used for fine adjustment. In that case, it is possible to set the capacity load of the variable dummy load 7 with higher accuracy.

[Components of DLL Circuit] A specific configuration example of the DLL circuit having the feedback loop shown in FIG. 2 will be described below.

[Variable Delay Circuit] FIG. 10 is a diagram showing an example of the variable delay circuits 2 and 5. This variable delay circuit delays the input clocks CLK1 and c-clk by the number of gate stages controlled by the control signal φE, and outputs output clocks CLK2 and CLK3. The variable delay circuits 2 and 5 include a plurality of inverters 98-1.
12 and NAND gates 113 to 128 are configured as shown. A clock obtained by delaying the input clocks CLK1 and c-clk is supplied to one input of the NAND gates 113 to 120, and the delay control signal φE-
1 to φE-32 are supplied. Delay control signals φE-1 to φE-32
, One of the signals becomes H level and the remaining signals become L level.

If the delay control signal φE-1 is at the H level, the outputs of the NAND gates 113 to 119 are all at the H level due to the L level of the other delay control signals. As a result, all NAND gates 121 to 127 are at L level,
All inverters 102 to 108 are at H level. Therefore, the input clock is supplied to the four inverters 98 to 101.
And a delay amount of a total of ten stages of NAND gates 120 and 128 and four inverters 109 to 112 are output as an output clock CLK2. This state is a state where the delay amount is the minimum. Usually, when the power is turned on, the delay amount is reset to a minimum state by a power-on reset signal.

The H-level delay control signals φE-1 to φE-1
Each time φE-32 shifts to the right in the figure, the delay amount of the two-stage gate by the NAND gate 127 and the inverter 108 is added. When the delay control signal φE-32 becomes H level, the delay amount becomes the maximum. That is, when the H-level delay control signal of the delay control signals φE-1 to φE-32 is shifted to the right by one, the delay amount for the two stages of the NAND gate and the inverter is increased and is shifted to the left by one. , The delay amount for the same two stages is reduced.

[Output Buffer and Dummy Output Buffer]
FIG. 11 is a circuit diagram of the output buffer and the dummy output buffer. The output buffer 3 is supplied with data DATA from the inside, and latches the latch circuits 10 and 12 via CMOS switches composed of transistors N2, P2 and N3, P3 which become conductive at the rising edge of the timing clock CLK2.
Latched. Then, in response to the latched data signals, one of the PMOS transistor P1 and the NMOS transistor N1 in the output stage becomes conductive, and outputs an output signal to the output terminal Dout. Output stage transistor P
1 and N1 are designed as large transistors to drive an external capacitive load Co. The output stage transistors are connected to power supplies VccQ and VssQ for an output buffer.

On the other hand, the dummy output buffer 6 has the same circuit configuration as the output buffer 3. That is, the CMOS transistor N1 which becomes conductive at the rising edge of the clock CLK3
2, P12, N13, P13, and the latch circuit 2
Predetermined data is latched at 0,22. Then, the load capacitance of the dummy load 7 is driven by the transistors P11 and N11 in the output stage.

The output stage transistors P11 and N11 of the dummy output buffer 6 are designed to be much smaller than the output stage transistors P1 and N1 of the output buffer 3. In the integrated circuit device,
This is to prevent a large area from being occupied. Therefore, the capacity load of the dummy load 7 is set to, for example, about 1/10, that is, about 5 pF as compared with the external capacity load Co connected to the output terminal Dout. Accordingly, the output stage transistors P11 and N11 are also designed to be one-tenth the size of the output transistors in the output buffer 3. Further, the delay time of the dummy output buffer 6 is
, Capacitors C1 and C2 are connected to the gate electrodes of the transistors P11 and N11 in the output stage. The capacitances C1 and C2 are designed to be equal to the gate capacitances of the output stage transistors P1 and N1 in the output buffer 3 when combined with the gate capacitances of the output stage transistors P11 and N11.

As described above, the size of the transistors P11 and N11 in the dummy output buffer 6 is reduced, and the capacity load of the dummy load 7 is correspondingly reduced, so that the occupied area in the integrated circuit device is reduced. In addition, power consumption by the dummy output buffer 6 can be reduced.

As described above, the capacity load of the dummy load 7 is designed to be smaller by a predetermined ratio than the actual external capacity load Co. Therefore, a slight variation in the capacitance load in the dummy load 6 due to a manufacturing variation has a great effect on the delay characteristics. The dummy load 7 is affected by manufacturing variations, but the external capacitance load Co is not affected by manufacturing variations. Therefore, it is important to be able to variably set the dummy load 6 as in the present embodiment, in order to generate the timing clock CLK2 having the optimal timing.

[Phase Comparison Circuit] FIG. 12 is a circuit diagram of a phase comparison unit in the phase comparison circuit 9. FIG. 13 is a waveform chart showing the operation of the phase comparison unit. This phase comparison unit includes NAND gates 199 to 203 and inverter 21
5, a phase relationship between the first clock c-clk and the second clock di-clk is detected, and the detection result is generated at nodes n1 to n4. As shown in FIG. 13A, the phase relationship between the two clocks is lower than that of the first clock c-clk.
A state in which the phase of i-clk is advanced, a state in which the phases of both clocks are almost the same as shown in FIG. 13B, and a state in which the first clock c is shown in FIG.
The state is classified as a state in which the phase of the second clock di-clk is delayed as compared with -clk.

In the state of FIG. 13A, when both clocks are at the L level, the nodes n1 to n4 are all at the H level, and then the second clock di-clk is at the H level first. And n1 = L, n2 = H, n3 = L, n4 = H. Then, the first clock c-clk is delayed by H
The state of the above-mentioned nodes n1 to n4 does not change even if the level is reached. The output of the NAND gate 198 becomes L level when both clocks become H level, and an H level pulse having a predetermined width is output from the NOR gate 216 from the falling edge thereof. This H level pulse is supplied as a sampling pulse to NAND gates 204 to 207, and the state of nodes n1 to n4 is changed to NAND gate 2
08, 209 and a NAND gate 2
10 and 211, respectively. Therefore, the signals φb, φc, φd, and φe are as shown in FIG.
As shown in the table, φb = H, φc = L, φd = H, and φe = L.

FIG. 13B shows the state of the first clock c.
This is a case where the phase of the second clock di-clk lags behind −clk within a delay time of the NAND gate 201 and the inverter 215. The delay time of the NAND gate and the inverter is the same as the delay amount of one stage of the delay control of the variable delay circuit described above. In that case, the first clock c-clk goes high first, n1 = H, n2 = L, and the output of the inverter 215 goes high after the second clock di-clk. And n3 = L and n4 = H.

Therefore, the signals are latched at the timing when both clocks become H level, and the signals φb, φc, φd, φe are
As shown in the table of FIG. 12, φb = L, φc = H, φd = H, and φe = L. In this case, it means that the phases match, so that the lock-on signal JST output from the lock-on detection circuit 418 also outputs the H level.

In the state shown in FIG. 13C, the first clock c-clk goes high first, and n1 = H, n2 = L, n3 = H, and n4 = L. Thereafter, even if the second clock di-clk goes high with a delay, the states of the nodes n1 to n4 do not change. This state is latched at the timing when both clocks become H level, and signals φb, φc, φd, φ
e becomes φb = L, φc = H, φd = L, and φe = H as shown in the table of FIG.

FIG. 14 is a circuit diagram of the phase comparison output unit of the phase comparison circuit 9. FIG. 15 is a waveform chart showing the operation of the phase comparison output unit. (A) of the waveform diagram,
(B) and (C) show (A) and (B) of FIGS.
(B) and (C) respectively.

The phase comparison output section includes a frequency dividing circuit 21A that divides the frequency of the timing signal φa generated at the timing of the phase comparison between the two clocks by half, and the timing of the output from the frequency dividing circuit 21A. , The signals φb, φc, φd, generated in accordance with the phase relationship between the two clocks.
An output circuit 21B for outputting phase comparison result signals φSO to φRE based on φe.

The 1/2 frequency dividing circuit 21A has a JK flip-flop configuration and includes both clocks c-clk, di-
The timing when both the clks become H level is determined by the NAND gate 198.
(FIG. 12), the detected pulse .phi.a is divided by half to generate pulse signals n11 and n12 having opposite phases. A detection pulse φa is supplied to gates 226 and 227, and an inverted detection pulse / φa is supplied to gates 222 and 223, and a latch circuit comprising gates 228 and 229;
An inverted signal is transferred between the latch circuits including the gates 224 and 225. As a result, antiphase pulse signals n11 and n12 that are divided by half are generated.

The output circuit 21B decodes the sampled and latched signals φb, φc, φd, φe, and
Of the clock c-clk of the second clock di-i-
When the delay is behind clk (state (A)), the output of the diode 236 is set to the H level, and when the phases of both clocks match (state (B)), the diodes 236 and 23
7 are both at L level, and the first clock c
When the phase of -clk is ahead of the second clock di-clk (state (C)), the output of the diode 237 is set to the H level.

Accordingly, in the output circuit 21B, in the above state (A), the NAND gates 232 and 233 respond to the timing signals n11 and n12 by the decode function of the NAND gates 232 to 235 to output the second signal. The phase comparison result signals φSO and φ for increasing the delay amount of the variable delay circuits 2 and 5 so as to delay the phase of the clock di-clk.
SE is alternately set to the H level. That is, it is as shown in FIG. In the above state (B), the output circuit 21B does not generate the phase comparison result signals φSO to φRE as shown in FIG. Further, in the above state (C), as shown in FIG.
In response to the timing signals n11 and n12, the phase comparison result signals φRO and φRE for reducing the delay amount of the variable delay circuits 2 and 5 are advanced so that the phase of the second clock di-clk is advanced. Alternately to H level.

[Delay Control Circuit] FIG. 16 is a circuit diagram showing a partial configuration of delay control circuit 10. Referring to FIG. Delay control circuit 1
0 is NOR in response to the phase comparison result signals φSO to φRE.
The delay control signal φE-1 is output from the gates 431-1 to 431-3.
~ ΦE-3 is output. As shown in FIG. 10, the delay control signals φE-1 to φE-32 are composed of 32 bits.

The delay control circuit 10 outputs the phase comparison result signal φ
SO, φSE shifts the H-level delay control signal φE to the right, increases the delay amount of the variable delay circuit, and shifts the H-level delay control signal φE to the left by the phase comparison result signals φRO, φRE, thereby changing the variable delay circuit. Reduce the amount of delay.

In each stage of the delay control circuit 10, for example, in the first stage, a NAND gate 432-1 and an inverter 433-
1 each having a latch circuit. Also, the latch circuits 432-1 and 43-1 are controlled by the phase comparison result signals φSO to φRE.
Transistor 43 forcibly inverting the state of 33-1
4-1 and 436-1. Transistor 438-
1,439-1 is provided to prevent the latch circuit from being inverted by the transistors 434-1 and 436-1 when the latch circuit is not the target of inversion. The circuits in the second to third stages have the same configuration. These transistors are all N
Channel type.

Now, if a reset signal φR of an L level pulse is applied with a power-on reset, the NAND
The outputs of the gates 431-1 to 431-3 are all at H level, and the outputs of the inverters 433-1 to 343-3 are all at L level.
Therefore, the node 5a-2 goes low, and the delay control signal φE-1 output from the NOR gate 431-1 goes high. Since both nodes 5a-1 and 5a-3 are at H level, all the other delay control signals φE-2 and φE-3 are at L level. That is, the delay control signal φE-1 goes high in response to the reset signal φR, and the variable delay circuits 2 and 5 are controlled to the minimum delay time.

Next, when the phase comparison is executed, one of the phase comparison result signals φSO to φRE becomes H level according to the phase relationship between the two clocks. If the phase comparison result signal φSE goes high, the transistor 434-1 conducts, forcibly pulling down the node 5a-1 to the low level, and forcibly pulling the node 5a-2 of the output of the inverter 433-1. To H level. As a result, the output φE-1 of the NOR gate 431-1 becomes L level. Also, since both nodes 5a-1 and 5a-4 are at L level, NO
The output .phi.E-2 of the R gate 431-2 becomes H level. Then, the first-stage and second-stage latch circuits hold the state. Further, when the phase comparison result signal φSO becomes H level by the subsequent phase comparison, the node 5
Both a-3 and 5a-6 go low, and the delay control signal φE-3 goes high. Thus, the delay control signal φE is shifted rightward by the phase comparison result signals φSE and φSO so that the delay time becomes longer.

On the contrary, the delay control signal φE is shifted to the left by the operation opposite to the above by the phase comparison result signals φRE and φRO so as to shorten the delay time. As is apparent from the operation of the output section of the phase comparison circuit, the phase comparison result signals φSE and φSO are alternately generated for each phase comparison when the second clock di-clk is advanced. , The phase comparison result signals φRE and φRO are the second clocks di-i-
Generated alternately for each phase comparison when clk is late.

Further, in response to the phase comparison result signals φSE and φSO, the delay control signal φE sequentially moves to the right, and finally the delay control signal φE-32 goes to the H level. In this state,
The output of inverter 433-32 is latched at L level, and the output of NAND gate 432-32 is latched at H level. Therefore, the comparison result signal φSO for further extending the delay time
Is supplied, the output of the NAND gate 432-43 is lowered to the L level, and the output of the inverter 433-32 is raised to the H level.

In the above-described embodiment, an example in which a fuse element is used as a programmable memory has been described. However, it is also possible to use another programmable memory element.

[0069]

As described above, according to the present invention, it is possible to prevent the timing of the timing clock generated by the self-timing control circuit from deviating from the optimum value due to manufacturing variations.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration example of a conventional self-timing control circuit using a DLL circuit;

FIG. 2 is a diagram showing an embodiment of the present invention.

FIG. 3 is a diagram illustrating a configuration example (1) of a first variable dummy load;

FIG. 4 is a diagram illustrating a configuration example of a variable resistor Rp.

FIG. 5 is a diagram showing a configuration example (1) of a program circuit 11;

FIG. 6 is a diagram illustrating a configuration example (2) of a program circuit 11;

FIG. 7 is a flowchart for setting an optimum capacity load of the variable dummy load 7 using the program circuit 11;

FIG. 8 is a diagram illustrating a configuration example (2) of a first variable dummy load;

FIG. 9 is a diagram illustrating a configuration example of a variable capacitor Cp.

FIG. 10 is a diagram illustrating an example of variable delay circuits 2 and 5;

FIG. 11 is a circuit diagram of an output buffer and a dummy output buffer.

FIG. 12 is a circuit diagram of a phase comparison unit in the phase comparison circuit 9.

FIG. 13 is a waveform chart showing an operation of a phase comparison unit in the phase comparison circuit 9;

FIG. 14 is a circuit diagram of a phase comparison output unit of the phase comparison circuit 9.

FIG. 15 is a waveform chart showing the operation of the phase comparison output section of the phase comparison circuit 9.

FIG. 16 is a circuit diagram of the delay control circuit 10.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Clock input buffer 2 2nd variable delay circuit 3 Output buffer 5 1st variable delay circuit 6 Dummy output buffer 7 Variable dummy load 8 Dummy input buffer 9,10 Phase comparison / delay control circuit Rp Variable resistance Cp Variable capacitor

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (reference) // H03K 5/135 G11C 11/34 354C 362S F term (reference) 5B024 AA03 BA21 BA23 CA07 CA11 EA01 5B079 AA07 CC02 CC08 CC14 CC17 DD03 DD06 DD17 5J001 AA11 BB10 BB11 BB12 BB14 BB24 CC03 DD01 DD04 5J106 AA03 CC21 CC52 CC58 DD24 GG04 HH02 KK32 KK37 LL02 5L106 AA01 AA02 DD12 DD32 DD37 EE03 FF05 GG03 GG07

Claims (8)

[Claims] 1. A self-timing control circuit for delaying a supplied clock signal to generate a timing clock having a predetermined phase relationship with the supplied clock signal, wherein the supplied clock signal is inputted, and the frequency of the supplied clock signal is changed. A first variable delay circuit for delaying the supply clock by a controlled delay amount, the supply clock being connected to the first variable delay circuit and having a predetermined delay amount set regardless of the frequency of the supply clock; An additional delay circuit that delays the variable delay load, the additional delay circuit has a variable dummy load in which the delay amount is variably set, and the delay amount of the variable dummy load is variable by a programmable memory that sets the delay amount. A self-timing control circuit characterized by being set. 2. The circuit according to claim 1, further comprising: a clock input buffer for receiving the supply clock; and a delay controlled by inputting the supply clock captured by the clock input buffer, similarly to the first variable delay circuit. A second variable delay circuit that delays by an amount and generates the timing clock; and an output buffer that outputs an output signal in synchronization with the timing clock. The additional delay circuit further includes: a clock input buffer. And a dummy input buffer and a dummy output buffer having the same delay amount as the output buffer. The self-timing control circuit is further delayed by the supply clock, the first variable delay circuit, and the additional delay circuit. The variable clock is compared with the First and second
A self-timing control circuit having a phase comparison / delay control circuit for controlling a delay amount of the variable delay circuit. 3. The self-timing control circuit according to claim 1, further comprising an external setting circuit for setting a delay amount of said variable dummy load by an external signal. 4. The switching circuit according to claim 3, further comprising a switching circuit for switching between setting of the delay amount of the variable dummy load by the external setting circuit and setting of the delay amount of the variable dummy load by the programmable memory. Characteristic self-timing control circuit. 5. The switching circuit according to claim 4, wherein the switching circuit activates the setting of the delay amount by the external setting circuit in a test mode, and activates the setting of the delay amount by the programmable memory in a normal operation mode. And a self-timing control circuit. 6. The output buffer according to claim 1, wherein the output buffer has an output terminal connected to an external capacitance load having a predetermined capacitance, and the capacitance load of the variable dummy load is more predetermined than the external capacitance load. Wherein the driving capability of the dummy output buffer is smaller than the driving capability of the output buffer according to the predetermined ratio. 7. The self-timing control circuit according to claim 1, wherein said programmable memory comprises a memory cell having a fuse element. 8. The self-timing control circuit according to claim 1, wherein said variable dummy load is constituted by a variable resistor or a variable capacitor.