JP2006351834A - Ceramic circuit board and semiconductor module using it - Google Patents

Ceramic circuit board and semiconductor module using it Download PDF

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JP2006351834A
JP2006351834A JP2005176161A JP2005176161A JP2006351834A JP 2006351834 A JP2006351834 A JP 2006351834A JP 2005176161 A JP2005176161 A JP 2005176161A JP 2005176161 A JP2005176161 A JP 2005176161A JP 2006351834 A JP2006351834 A JP 2006351834A
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circuit board
metal plate
ceramic
plate
ceramic circuit
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JP5019148B2 (en
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Toshiyuki Imamura
寿之 今村
Hiroyuki Tejima
博幸 手島
Junichi Watanabe
渡辺　　純一
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Proterial Ltd
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Hitachi Metals Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a ceramic circuit board having an excellent heat-dissipating property and being not peeled, by using a technique determining the thermal behavior of the ceramic circuit board having a laminated structure composed of materials of a different kind, and to provide a semiconductor module. <P>SOLUTION: The ceramic circuit board 10 has a ceramic plate board 11 functioning as an insulating layer such as a silicon nitride board (the Si<SB>3</SB>N<SB>4</SB>board) 11a, a metal plate 12 for forming a circuit pattern joined on one surface of the ceramic plate board 11 through a solder material, and the metal plate 13 for dissipating a heat joined on the other surface of the ceramic plate board 11 through the solder material. The metal plate for forming the circuit pattern and the metal plate for dissipating the heat are formed of Al or an Al alloy. The ceramic circuit board 11 having such a constitution is controlled so that an apparent coefficient of thermal expansion is kept within a range from 10 ppm/k to 17 ppm/k. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明はセラミックス回路基板等の技術に関し、特に冷熱サイクルに対する高信頼性が求められるパワー半導体モジュールに有効に適用することができる技術である。   The present invention relates to a technique for a ceramic circuit board and the like, and is a technique that can be effectively applied to a power semiconductor module that is particularly required to have high reliability with respect to a cooling cycle.

以下に説明する技術は、本発明を完成するに際し、本発明者によって検討されたものであり、その概要は次のとおりである。
従来のパワー半導体モジュールは、半導体素子を搭載したセラミックス回路基板を放熱ベースにはんだを介して接合した構成を有している。パワー半導体モジュールに搭載される半導体素子からの発熱量が大きく、動作安定性を確保するため高い放熱特性が求められている。かかる放熱特性を保証する構成として、上記の如くセラミックス回路基板をはんだを介して放熱ベースに接合する構成が採用されている。 The technology described below has been studied by the present inventors in completing the present invention, and the outline thereof is as follows.
A conventional power semiconductor module has a configuration in which a ceramic circuit board on which a semiconductor element is mounted is joined to a heat dissipation base via solder. A large amount of heat is generated from the semiconductor element mounted on the power semiconductor module, and high heat dissipation characteristics are required to ensure operational stability. As a configuration for guaranteeing such heat dissipation characteristics, a configuration is adopted in which the ceramic circuit board is joined to the heat dissipation base via solder as described above.

かかる半導体モジュールで使用されるセラミックス回路基板としては、例えば、窒化アルミニウム基板(AlN基板)の一方の面に、回路パターン形成用金属板としてAlあるいはCuが設けられ、他方の面の放熱用金属板としてAlあるいはCuが設けられる。また、当該セラミックス回路基板の放熱ベースとして、Cu-MoあるいはAl-SiC等の低熱膨張材が取り付けられた半導体モジュールの構成が知られている。   As a ceramic circuit board used in such a semiconductor module, for example, Al or Cu is provided as a circuit pattern forming metal plate on one surface of an aluminum nitride substrate (AlN substrate), and the heat radiating metal plate on the other surface. Al or Cu is provided. Further, a configuration of a semiconductor module is known in which a low thermal expansion material such as Cu—Mo or Al—SiC is attached as a heat dissipation base of the ceramic circuit board.

さらに、特許文献１には、セラミックス基板の表面に回路、裏面に放熱板が形成されてなる回路基板を、熱膨張係数が１０ｐｐｍ以上である金属を主成分とするベースに、Sn-Sb系半田を用いて接合し、セラミックス基板が窒化アルミニウムまたは窒化ケイ素で、回路及び放熱板がAl又はAl合金である構成が提案されている。   Further, in Patent Document 1, a circuit board having a circuit on the front surface of a ceramic substrate and a heat sink on the back surface, a Sn-Sb solder based on a base mainly composed of a metal having a thermal expansion coefficient of 10 ppm or more. A structure is proposed in which the ceramic substrate is made of aluminum nitride or silicon nitride, and the circuit and the heat sink are made of Al or an Al alloy.

放熱特性は、実際には、-４０℃から１２５℃までの冷熱サイクル試験を所定回数経た上でも保証されることが要求されている。使用分野に応じて、例えば、２００回以上、１０００回以上、さらには３０００回以上の冷熱サイクル試験にパスすることが求められる。特に、ハイブリッド車、電気自動車、電車および航空機等に搭載される場合には、高い耐冷熱サイクル性を有した高信頼性が要求されている。   In fact, the heat dissipation characteristics are required to be guaranteed even after a predetermined number of cooling cycle tests from −40 ° C. to 125 ° C. Depending on the field of use, for example, it is required to pass a thermal cycle test of 200 times or more, 1000 times or more, and 3000 times or more. In particular, when it is mounted on a hybrid vehicle, an electric vehicle, a train, an aircraft, and the like, high reliability having high cold-heat cycle resistance is required.

かかる冷熱サイクルに対しての信頼性の向上を図るセラミックス回路基板の技術としては、例えば、特許文献２には、セラミックス基板の一方の側に接合した放熱側金属板の厚さを、セラミックス基板の他方の側に接合した素子搭載側金属板の１／２以下に規定することが提案されている。   As a technology of a ceramic circuit board for improving the reliability with respect to the cooling / heating cycle, for example, in Patent Document 2, the thickness of the heat-dissipation-side metal plate bonded to one side of the ceramic substrate is set as follows. It has been proposed to define it to be 1/2 or less of the element mounting side metal plate bonded to the other side.

また、放熱特性を確保するためには、素子搭載側の金属板、放熱側の金属板等とセラミックス基板との接合部の剥離が発生しないようにすることが当然に求められるが、かかる点に着目した技術として、例えば、特許文献３には、放熱側金属板の体積／素子搭載側の金属板の体積との体積比を１．０未満に規定することが提案されている。   Moreover, in order to ensure the heat dissipation characteristics, it is naturally required to prevent peeling of the joint portion between the element mounting side metal plate, the heat dissipation side metal plate, etc., and the ceramic substrate. As a focused technique, for example, Patent Document 3 proposes that the volume ratio of the volume of the metal plate on the heat dissipation side / the volume of the metal plate on the element mounting side be defined to be less than 1.0.

さらに、特許文献４では、セラミックス基板として窒化珪素基板を用いた場合に、窒化珪素基板の厚みを、素子搭載側の金属回路板の厚みの２倍以下に規定することが提案されている。   Further, Patent Document 4 proposes that when a silicon nitride substrate is used as the ceramic substrate, the thickness of the silicon nitride substrate is regulated to be twice or less the thickness of the metal circuit board on the element mounting side.

また、窒化珪素基板の厚みに着目した技術としては、例えば、特許文献５に、熱伝導率が９０Ｗ／ｍ・Ｋ以上、３点曲げ強度が７００ＭＰａ以上の窒化珪素基板の厚さをｔｃとした場合に、かかる窒化珪素基板に接合した金属層（金属板）の厚さをｔｍとすると、２ｔｍ≦ｔｃ≦２０ｔｍ等と規定することが提案されている。   Further, as a technique focusing on the thickness of the silicon nitride substrate, for example, in Patent Document 5, the thickness of the silicon nitride substrate having a thermal conductivity of 90 W / m · K or more and a three-point bending strength of 700 MPa or more is defined as tc. In this case, it has been proposed that the thickness of the metal layer (metal plate) bonded to the silicon nitride substrate is defined as 2 tm ≦ tc ≦ 20 tm.

特開２００２-５０８４１号公報JP 2002-50841 A 特開平８-１０２５７０号公報JP-A-8-102570 特開平７-８６７０３号公報JP-A-7-86703 特開平９-６９６７２号公報JP-A-9-69672 特開２０００-１２８６５４号公報JP 2000-128654 A

ところが、上記セラミックス回路基板、あるいはそれを用いた半導体モジュールの技術では、以下の課題があることを本発明者は見出した。
Al配線基板を用いた場合では、前述の如く、Cu-Mo、あるいはAl-SiC等の低熱膨張材を放熱ベースとして用いる構成が必須となっている。しかし、かかる構成はコスト高となり、低コスト化の要請に十分に応えることができない。また、近年パワー半導体モジュールに搭載される半導体素子のパワー密度の増大により、半導体素子動作時に発生する熱量が大きくなり、上記の従来構造では、素子に発生する熱を速やかに、冷却システムへ伝えることができず、放熱性の点で難点がある。 However, the present inventors have found that the above-described ceramic circuit board or a semiconductor module technology using the ceramic circuit board has the following problems.
In the case of using an Al wiring substrate, as described above, a configuration using a low thermal expansion material such as Cu—Mo or Al—SiC as a heat dissipation base is essential. However, this configuration is costly and cannot fully meet the demand for cost reduction. In recent years, due to the increase in power density of semiconductor elements mounted on power semiconductor modules, the amount of heat generated during operation of the semiconductor elements has increased. With the conventional structure described above, the heat generated in the elements can be quickly transferred to the cooling system. However, there is a drawback in terms of heat dissipation.

かかる低コスト化および高放熱性付与の方策として、Al板ベースを放熱ベースとして使用する構成が検討されている。すなわち、セラミックス回路基板をはんだを介してAl板に構成した放熱ベースに接合する構成が検討されている。しかし、かかる構成では、Al配線基板と放熱ベースのAl板との熱膨張係数の差が非常に大きく、はんだを介して接合する構造では、前述の如き冷熱サイクルにおいてはんだ接合部の剥離が生じ、放熱特性を保証することができない。   As a measure for reducing the cost and imparting high heat dissipation, a configuration using an Al plate base as a heat dissipation base has been studied. That is, the structure which joins the ceramic circuit board to the thermal radiation base comprised to the Al board via solder is examined. However, in such a configuration, the difference in the thermal expansion coefficient between the Al wiring board and the heat-dissipating base Al plate is very large, and in the structure that is joined via solder, the solder joint is peeled off in the cooling and heating cycle as described above. The heat dissipation characteristics cannot be guaranteed.

かかる半導体モジュールの放熱特性に関しては、Alベース直下にAlフィンを設けることにより、極めて放熱性の良いパワーモジュールを構成することが可能となる。かかるセラミックス回路基板において、回路パターン形成用金属板、及び放熱用金属板をAlに変えることは比較的に簡単に行えるが、本発明者は、Al材を回路パターン形成用金属板、放熱用金属板に使用する場合のセラミックス回路基板の開発が必要と考えた。   With regard to the heat dissipation characteristics of such a semiconductor module, it is possible to configure a power module with extremely good heat dissipation by providing an Al fin immediately below the Al base. In such a ceramic circuit board, the circuit pattern forming metal plate and the heat radiating metal plate can be changed to Al relatively easily. However, the present inventor has made the Al material a circuit pattern forming metal plate and a heat radiating metal. We thought it necessary to develop a ceramic circuit board for use in boards.

セラミックス回路基板としては、どのような素材が適しているかの素材選択の検討が必要である。かかる素材選択は、セラミックス回路基板における耐冷熱サイクル性を有した放熱特性の確保を選択基準として行なう必要がある。すなわち、セラミックス回路基板としての熱的挙動の把握が求められる。   For ceramic circuit boards, it is necessary to examine the selection of materials that are suitable. Such material selection needs to be performed based on selection of ensuring heat radiation characteristics having heat and cold resistance in a ceramic circuit board. That is, it is required to grasp the thermal behavior as a ceramic circuit board.

しかし、現行の技術では、異種材料の接合構造を有したセラミックス回路基板の冷熱サイクル時の熱的挙動まで把握することはできない。全ての組み合わせに対して、実際に冷熱サイクル試験を行い、その適否を判断するしか無い状況である。ある意味では、最適組み合わせを見つけるには、闇雲に膨大な実験を行なわなければならない場合も十分に想定される。   However, with the current technology, it is impossible to grasp the thermal behavior of a ceramic circuit board having a joint structure of different materials during a cooling / heating cycle. It is a situation where all combinations are actually subjected to a cooling / heating cycle test to determine their suitability. In a sense, it is quite possible that a huge amount of experimentation must be done in the dark clouds to find the optimal combination.

本発明者は、異種材料の接合構造であるセラミックス回路基板としての熱的挙動は、セラミックス回路基板全体としての熱膨張係数からある程度予見できるのではないかと考えた。しかし、現実には、異種材料の接合構造であるセラミックス回路基板の熱膨張係数の実測は行えない。   The inventor considered that the thermal behavior of a ceramic circuit board having a bonded structure of different materials can be predicted to some extent from the thermal expansion coefficient of the entire ceramic circuit board. However, in actuality, it is not possible to actually measure the thermal expansion coefficient of a ceramic circuit board that is a bonded structure of different materials.

そこで、本発明者は、実測は行えないものの、セラミックス回路基板を構成する異種材料のそれぞれの熱的挙動が、全体としてのセラミックス回路基板の熱的挙動に大きな影響を与えるのではないかと着想した。すなわち、本発明者は、セラミックス回路基板の熱的挙動を、かかるセラミックス回路基板を構成する異種材料の熱的挙動の総和として把握することができるのではないかと、着想した。   Therefore, although the present inventor cannot perform actual measurement, the inventors have conceived that the thermal behavior of different materials constituting the ceramic circuit board may greatly affect the thermal behavior of the ceramic circuit board as a whole. . That is, the present inventor has conceived that the thermal behavior of the ceramic circuit board can be grasped as the sum of the thermal behaviors of different materials constituting the ceramic circuit board.

また、冷熱サイクル時の問題となる現象は、放熱ベースとセラミックス回路基板との剥離であり、かかる剥離は、両者の熱膨張係数の差に起因して発生する現象である。そこで、本発明者は、セラミックス回路基板の熱的挙動の把握は、セラミックス回路基板を構成する異種材料の個々の構成要素を考慮した熱膨張係数として把握することが好ましいと発想した。かかる異種材料の接合構造であるセラミックス回路基板の熱膨張係数は実測することはできないが、個々の異種材料の構成要件は十分に前もって知ることができる筈で、かかる構成要件から、セラミックス回路基板全体としての計算上の、すなわち見掛けの熱膨張係数を算出することができるのではないかと発想した。   Also, a phenomenon that becomes a problem during the cooling / heating cycle is peeling between the heat dissipation base and the ceramic circuit board, and this peeling is a phenomenon caused by a difference in thermal expansion coefficient between the two. Therefore, the present inventor has thought that it is preferable to grasp the thermal behavior of the ceramic circuit board as a thermal expansion coefficient considering individual components of different materials constituting the ceramic circuit board. Although the thermal expansion coefficient of a ceramic circuit board that is a bonded structure of such different materials cannot be actually measured, the component requirements of each different material should be known in advance. As a result, it was thought that an apparent thermal expansion coefficient could be calculated.

かかる異種材料の接合構造を有するセラミックス回路基板の見掛けの熱膨張係数を算出できれば、逆に、例えば、放熱ベースのAl材の熱膨張係数に近づけるように異種材料の構成条件を制御することで、冷熱サイクルに対しての高い耐性を有し、且つ放熱特性の優れたセラミックス回路基板を提供できる筈であるとも考えた。   If the apparent thermal expansion coefficient of the ceramic circuit board having such a heterogeneous material bonding structure can be calculated, on the contrary, for example, by controlling the configuration conditions of the heterogeneous material so as to approach the thermal expansion coefficient of the Al material of the heat dissipation base, The present inventors also considered that it should be possible to provide a ceramic circuit board having high resistance to a cooling and heating cycle and excellent heat dissipation characteristics.

さらに、セラミックス回路基板には、厚いAlを回路パターン形成用金属板、及び放熱用金属板に用いることを想定した場合、冷熱繰り返しに伴う、セラミックス基板への負荷応力が増大するため、基板自身の機械強度ならびに破壊靱性に優れた適切な素材選択が必要となる。   Furthermore, assuming that thick Al is used for the circuit pattern forming metal plate and the heat radiating metal plate for the ceramic circuit board, the load stress on the ceramic substrate increases due to repeated cooling and heating. Appropriate material selection with excellent mechanical strength and fracture toughness is required.

本発明の目的は、回路パターン形成用金属板、放熱用金属板としてAl材を用いたセラミックス回路基板ならびにこれらを用いた半導体モジュールの技術を提供することにある。   An object of the present invention is to provide a circuit pattern forming metal plate, a ceramic circuit substrate using an Al material as a heat radiating metal plate, and a semiconductor module using these.

本発明の目的は、異種材料の接合構造を有するセラミックス回路基板の熱的挙動を把握する技術を提供することにある。
本発明の前記ならびにその他の目的と新規な特徴は、本明細書の記述および添付図面から明らかになるであろう。 An object of the present invention is to provide a technique for grasping the thermal behavior of a ceramic circuit board having a joining structure of different materials.
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、次のとおりである。
すなわち、本発明はセラミックス基板の一方の面に回路パターン形成用金属板が設けられ、前記セラミックス基板の他方の面に放熱用金属板が設けられたセラミックス回路基板であって、前記回路パターン形成用金属板は、AlまたはAｌ合金で形成され、前記放熱用金属板は、AlまたはAｌ合金で形成され、前記セラミックス基板、前記回路パターン形成用金属板、前記放熱用金属板の各々のヤング率、線膨張率、板厚に基づき算出される前記セラミックス回路基板の見掛けの熱膨張係数が、１０ｐｐｍ／ｋ以上、１７ｐｐｍ／ｋ以下であることを特徴とする。 Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.
That is, the present invention is a ceramic circuit board in which a circuit pattern forming metal plate is provided on one surface of a ceramic substrate, and a heat radiating metal plate is provided on the other surface of the ceramic substrate. The metal plate is formed of Al or Al alloy, the heat dissipation metal plate is formed of Al or Al alloy, and the Young's modulus of each of the ceramic substrate, the circuit pattern forming metal plate, and the heat dissipation metal plate, The apparent thermal expansion coefficient of the ceramic circuit board calculated based on the linear expansion coefficient and the plate thickness is 10 ppm / k or more and 17 ppm / k or less.

セラミックス回路基板の見掛けの熱膨張係数を、セラミックス回路基板を構成するセラミックス基板、回路パターン形成用金属板、放熱用金属板のそれぞれのヤング率、線膨張率、板厚ヤング率から算出し、かかる見掛けの熱膨張係数を１０ｐｐｍ／ｋ以上、１７ｐｐｍ／ｋ以下に規定することで、放熱ベースにAlあるいはAl合金を用いた場合の冷熱サイクルに対しての高信頼性を有したセラミックス回路基板を提供することができる。   The apparent thermal expansion coefficient of the ceramic circuit board is calculated from the Young's modulus, linear expansion coefficient, and plate thickness Young's modulus of the ceramic substrate, circuit pattern forming metal plate, and heat dissipation metal plate constituting the ceramic circuit substrate. By providing an apparent thermal expansion coefficient of 10 ppm / k or more and 17 ppm / k or less, a ceramic circuit board having high reliability against a cooling cycle when Al or an Al alloy is used for a heat dissipation base is provided. can do.

見掛けの熱膨張係数が１０ｐｐｍ／ｋ未満では、AlまたはAl合金で形成される放熱ベースとの熱膨張係数の差が大きくなり、冷熱サイクル時のセラミックス回路基板と放熱ベース間に接合部材として用いた半田に剥離現象が発生し易くなる。一方、１７ｐｐｍ／ｋを超える場合には、回路パターン形成用金属板および放熱用金属板の厚みが大きく、接合後にセラミックス基板に与える負荷応力が大きくなり、冷熱サイクル試験下では、低サイクルで回路パターン形成用金属板とセラミックス基板との界面で剥離が生じ、所望の信頼性を求めることが困難となる。すなわち、１０ｐｐｍ／ｋ以上、１７ｐｐｍ／ｋ以下の範囲であれば、かかる不具合現象を有効に抑制して、高い耐冷熱サイクル性を有した放熱特性の高いセラミックス回路基板を提供することができる。さらに望ましい範囲は、１２ｐｐｍ／ｋ以上、１５ｐｐｍ／ｋ以下である。   When the apparent thermal expansion coefficient was less than 10 ppm / k, the difference in thermal expansion coefficient from the heat dissipation base formed of Al or Al alloy was large, and it was used as a joining member between the ceramic circuit board and the heat dissipation base during the cooling / heating cycle. Peeling phenomenon is likely to occur in the solder. On the other hand, when it exceeds 17 ppm / k, the thickness of the metal plate for circuit pattern formation and the metal plate for heat dissipation is large, and the load stress applied to the ceramic substrate after bonding becomes large. Peeling occurs at the interface between the forming metal plate and the ceramic substrate, making it difficult to obtain desired reliability. That is, if it is the range of 10 ppm / k or more and 17 ppm / k or less, such a malfunction phenomenon can be suppressed effectively and the ceramic circuit board with the high heat dissipation characteristic which has high cold-heat cycle property can be provided. A more desirable range is 12 ppm / k or more and 15 ppm / k or less.

かかる構成において、前記セラミックス基板は板厚ｔ１が０．２ｍｍ以上、０．４ｍｍ以下であり、前記回路パターン形成用金属板は板厚ｔ２が０．４ｍｍ以上、１．２ｍｍ以下であり、前記放熱用金属板は板厚ｔ３が０．３ｍｍ以上、１．２ｍｍ以下であり、（前記回路パターン形成用金属板と前記放熱用金属板との総和板厚）／前記セラミックス基板の板厚とで示される板厚比（ｔ２＋ｔ３）／ｔ１が２以上、１２未満であることが望ましい。   In this configuration, the ceramic substrate has a plate thickness t1 of 0.2 mm to 0.4 mm, the circuit pattern forming metal plate has a plate thickness t2 of 0.4 mm to 1.2 mm, and the heat dissipation. The metal plate for use has a plate thickness t3 of 0.3 mm or more and 1.2 mm or less, indicated by (total plate thickness of the circuit pattern forming metal plate and the heat radiating metal plate) / plate thickness of the ceramic substrate. The plate thickness ratio (t2 + t3) / t1 is preferably 2 or more and less than 12.

かかる構成を採用することで、実際に使用するセラミックス回路基板を想定した回路パターン形成用金属板、放熱用金属板、セラミックス回路基板の実用的な板厚の範囲内で、板厚を指標として、セラミックス回路基板の接合構造におけるセラミックス回路基板の割合を少なくして、すなわち、AlあるいはAl合金からなる回路パターン形成用金属板と放熱用金属板の割合を多くして、セラミックス回路基板の全体としての見掛けの熱膨張係数を、AlあるいはAl合金からなる放熱ベースの熱膨張係数により近づけることができる。そのため、冷熱サイクル時のセラミックス回路基板と放熱ベースとの剥離障害ならびにセラミックス回路基板において、回路パターン形成用金属板とセラミックス基板との界面での剥離障害を抑制することができる。   By adopting such a configuration, within the range of the practical thickness of the circuit pattern forming metal plate, the heat radiating metal plate, the ceramic circuit board assuming the ceramic circuit board actually used, the thickness is used as an index, Decreasing the ratio of ceramic circuit boards in the ceramic circuit board bonding structure, that is, increasing the ratio of metal plates for circuit pattern formation and heat dissipation made of Al or Al alloy, The apparent thermal expansion coefficient can be made closer to the thermal expansion coefficient of the heat dissipation base made of Al or Al alloy. Therefore, it is possible to suppress the separation failure between the ceramic circuit board and the heat dissipation base during the cooling cycle and the separation failure at the interface between the circuit pattern forming metal plate and the ceramic substrate in the ceramic circuit board.

（前記回路パターン形成用金属板と前記放熱用金属板との総和板厚）／前記セラミックス基板の板厚とで示される板厚比が、２未満ではセラミックス回路基板の積層構造に占めるセラミックス基板の割合が大きくなり、見掛けの熱膨張係数を十分に放熱ベースの熱膨張係数に近づけることができず、場合によっては冷熱サイクル時に前記剥離障害が発生する問題がある。また、１２を越えるとセラミックス基板の接合構造に占める割合が少な過ぎて、セラミックス回路基板の破損障害が発生する問題がある。望ましい範囲は２以上〜９以下、更に望ましい範囲は２以上〜６以下である。   The total thickness of the circuit pattern forming metal plate and the heat radiating metal plate / the thickness of the ceramic substrate is less than 2, and the ceramic substrate occupies the laminated structure of the ceramic circuit substrate. The ratio increases, the apparent thermal expansion coefficient cannot be sufficiently brought close to the thermal expansion coefficient of the heat dissipation base, and there is a problem that the above-mentioned peeling failure occurs in some cases. On the other hand, when the number exceeds 12, the ratio of the ceramic substrate to the bonding structure is too small, and there is a problem that the ceramic circuit board is damaged. A desirable range is from 2 to 9, and a more desirable range is from 2 to 6.

上記いずれかの構成で、前記セラミックス基板は、窒化珪素板であることを特徴とする。セラミックス基板に窒化珪素板を使用すれば、接合構造におけるセラミックス基板の割合を、セラミックス回路基板の強度を確保しつつ少なくすることができる。そのため、セラミックス回路基板の見掛けの熱膨張係数をより放熱ベースの熱膨張係数に近づけることができる。   In any one of the above configurations, the ceramic substrate is a silicon nitride plate. If a silicon nitride plate is used for the ceramic substrate, the ratio of the ceramic substrate in the bonded structure can be reduced while ensuring the strength of the ceramic circuit substrate. Therefore, the apparent thermal expansion coefficient of the ceramic circuit board can be made closer to the thermal expansion coefficient of the heat dissipation base.

特に、前述の如く、セラミックス回路基板に厚いAlを、回路パターン形成用金属板、及び放熱用金属板に用いることを想定した場合、冷熱繰り返しに伴う、セラミックス基板への負荷応力が増大するが、かかる窒化珪素基板を採用すれば、基板自身の機械強度ならびに破壊靱性が優れているため、上記負荷応力にも十分な対応が取れることとなる。   In particular, as described above, when it is assumed that thick Al is used for a circuit pattern forming metal plate and a heat dissipating metal plate as described above, the load stress on the ceramic substrate increases due to repeated cooling and heating. If such a silicon nitride substrate is employed, the mechanical strength and fracture toughness of the substrate itself are excellent, so that it is possible to sufficiently cope with the load stress.

本発明の半導体モジュールは、上記いずれかの構成を有するセラミックス回路基板と、前記セラミックス回路基板の前記回路パターン形成用金属板の素子搭載部に搭載された半導体素子と、前記セラミックス回路基板が、はんだを介して接合されるAlまたはAl合金で形成される放熱ベースとを有することを特徴とする。かかる構成を採用することで、半導体モジュールの冷熱サイクルの耐性を向上させて、放熱効果を確保することができる。   The semiconductor module of the present invention includes a ceramic circuit board having any one of the above configurations, a semiconductor element mounted on an element mounting portion of the circuit pattern forming metal plate of the ceramic circuit board, and the ceramic circuit board having a solder And a heat dissipating base formed of Al or an Al alloy joined together. By adopting such a configuration, it is possible to improve the heat cycle resistance of the semiconductor module and ensure the heat dissipation effect.

さらに、かかる構成で、前記はんだは、Sn-Pb系はんだ、あるいはSn-Ag-Cu系またはSn-Sb系のPbフリーはんだであり、前記はんだには、粒径が２０μｍ以上、３００μｍ以下のNi、Cu、Mo、Wの粉末が１質量％以上、３０質量％以下の範囲で含まれているものを使用することが好ましい。かかる構成を採用すると、回路パターン形成用金属板および放熱用金属板として厚みの大きなAlあるいはAl合金を用いたセラミックス回路基板においても上記粉末がスペーシング材として機能する。   Furthermore, in such a configuration, the solder is Sn—Pb solder, or Sn—Ag—Cu or Sn—Sb Pb free solder, and the solder includes Ni having a particle size of 20 μm or more and 300 μm or less. It is preferable to use a powder containing Cu, Mo, W powder in the range of 1% by mass to 30% by mass. When such a configuration is adopted, the powder functions as a spacing material even in a ceramic circuit board using a thick Al or Al alloy as a circuit pattern forming metal plate and a heat radiating metal plate.

見掛けの熱膨張係数を放熱ベースのAlに近づけるために、上記の如くセラミックス基板に比してAl材を用いた回路パターン形成用金属板、放熱用金属板の割合を多くすることがその対策の一つとして有効ではあるが、しかし、セラミックス回路基板の全体重量は増大する。そのため、セラミックス回路基板と放熱ベースとを接合するために使用するはんだにスペーシング材として機能する上記粉末を混ぜておかないと、セラミックス回路基板の重量により放熱ベースとの間における上記はんだが周囲に押し出される現象が発生する場合がある。   In order to bring the apparent thermal expansion coefficient closer to the heat dissipation base Al, it is necessary to increase the ratio of the circuit pattern forming metal plate and the heat dissipation metal plate using Al material compared to the ceramic substrate as described above. Although effective as one, the overall weight of the ceramic circuit board increases. Therefore, if the above-mentioned powder that functions as a spacing material is not mixed with the solder used to join the ceramic circuit board and the heat dissipation base, the solder between the heat dissipation base and the ceramic circuit board will be surrounded by the weight of the ceramic circuit board. An extruding phenomenon may occur.

厚みがあって重量もあるセラミックス回路基板と放熱ベースとの間に介在させるはんだが、上記の如く、必要以上に周囲に押し出されると、はんだ接合部分に引け巣が発生し、かかる引け巣に基づく気泡がはんだ接合部分に残留し、結果として熱伝導を妨げることとなる。すなわち、スペーシング材として機能する上記粉末をはんだ材料に含有させておくことで、上記引け巣に基づく気泡の残留を抑制し、結果として、セラミックス回路基板から放熱ベースへの良好な熱伝導が確保されることとなる。   As described above, when the solder interposed between the thick and heavy ceramic circuit board and the heat dissipation base is pushed out to the surroundings more than necessary, a shrinkage nest is generated in the solder joint portion, and based on the shrinkage nest. Air bubbles remain in the solder joints, resulting in impeding heat conduction. In other words, by containing the above powder that functions as a spacing material in the solder material, it is possible to suppress residual bubbles due to the shrinkage nest, and as a result, ensure good heat conduction from the ceramic circuit board to the heat dissipation base. Will be.

粒径が２０μｍ未満ではスペーシング材としての効果がなく、一方３００μｍを越えるとはんだ層の厚みが大きくなり、放熱性の低下を招聘する。また、粉末が１質量％未満ではこの場合もスペーシング材としての効果がなく、３０質量％を越える場合にはセラミックス回路基板と放熱ベースの接合に必要なはんだ層の割合が低減するため、接合不良を招聘する。望ましくは、粒径が５０μｍ以上、２００μｍ以下のNi、Cu、Mo、Wの粉末が２質量％以上、１５質量％以下の範囲で含まれていることである。   When the particle size is less than 20 μm, there is no effect as a spacing material. On the other hand, when the particle size exceeds 300 μm, the thickness of the solder layer increases and the heat dissipation is reduced. In addition, if the powder is less than 1% by mass, there is no effect as a spacing material in this case, and if it exceeds 30% by mass, the proportion of the solder layer necessary for joining the ceramic circuit board and the heat dissipation base is reduced. Invite a defect. Desirably, Ni, Cu, Mo, and W powder having a particle size of 50 μm or more and 200 μm or less are contained in a range of 2% by mass or more and 15% by mass or less.

本願において開示される発明のうち、代表的なものによって得られる効果を簡単に説明すれば以下のとおりである。
セラミックス回路基板の見掛けの熱膨張係数を放熱ベースに近づけることができるため、セラミックス回路基板の冷熱サイクルの耐性を向上させることができる。その結果、かかるセラミックス回路基板を用いたパワー半導体モジュール等の半導体モジュールの熱破壊を抑制することができる。 Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.
Since the apparent thermal expansion coefficient of the ceramic circuit board can be made closer to the heat dissipation base, the resistance to the thermal cycle of the ceramic circuit board can be improved. As a result, thermal destruction of a semiconductor module such as a power semiconductor module using such a ceramic circuit board can be suppressed.

セラミックス回路基板の構成材としてAlあるいはAl合金を多く使用することで、セラミックス回路基板の生産コストの低減かつ熱抵抗の低減を図ることができる。その結果、かかるセラミックス回路基板を用いた、安価で高放熱性に優れるパワー半導体モジュール等の半導体モジュールを提供することができる。   By using a large amount of Al or Al alloy as the constituent material of the ceramic circuit board, the production cost of the ceramic circuit board can be reduced and the thermal resistance can be reduced. As a result, it is possible to provide a semiconductor module such as a power semiconductor module that uses such a ceramic circuit board and is inexpensive and excellent in heat dissipation.

以下、本発明の実施の形態を図面に基づいて詳細に説明する。なお、実施の形態を説明するための全図において、同一の部材には原則として同一の符号を付し、その繰り返しの説明は省略する場合がある。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof may be omitted.

本実施の形態では、本発明に係るセラミックス回路基板、及びそれを使用した半導体モジュールについて説明する。
図１は、本発明に係るセラミックス回路基板の全体構成を示す断面説明図である。図２は、図１に示すセラミックス回路基板を用いて本発明に係る半導体モジュールを構成した場合の全体構成を示す断面説明図である。 In the present embodiment, a ceramic circuit board according to the present invention and a semiconductor module using the ceramic circuit board will be described.
FIG. 1 is a cross-sectional explanatory view showing the overall configuration of a ceramic circuit board according to the present invention. FIG. 2 is an explanatory cross-sectional view showing the overall configuration when the semiconductor module according to the present invention is configured using the ceramic circuit board shown in FIG.

本発明に係るセラミックス回路基板１０は、図１に示すように、絶縁層として機能するセラミックス基板１１と、セラミックス基板１１の一方の面にろう材を介して接合された回路パターン形成用金属板１２と、セラミックス基板１１の他方の面にろう材を介して接合された放熱用金属板１３とを有している。
セラミックス基板１１は、例えば、窒化珪素板（Si3N4板）１１ａに構成されている。セラミックス基板１１の板厚は、例えば、実用的範囲として、０．２ｍ以上、０．４ｍｍ以下に設定しておけばよい。 As shown in FIG. 1, a ceramic circuit board 10 according to the present invention includes a ceramic substrate 11 functioning as an insulating layer, and a circuit pattern forming metal plate 12 bonded to one surface of the ceramic substrate 11 via a brazing material. And a heat radiating metal plate 13 joined to the other surface of the ceramic substrate 11 via a brazing material.
The ceramic substrate 11 is constituted by, for example, a silicon nitride plate (Si 3 N 4 plate) 11a. The plate | board thickness of the ceramic substrate 11 should just be set to 0.2 to 0.4 mm as a practical range, for example.

回路パターン形成用金属板１２は、例えば、Al板１２ａに構成されている。回路パターン形成用金属板の板厚は、例えば、実用的範囲としては、０．４ｍｍ以上、１．２ｍｍ以下に設定しておけばよい。尚、図１に示す場合には、回路パターン形成用金属板１２は、エッチング処理により、回路パターンＰが形成されている場合を示している。   The circuit pattern forming metal plate 12 is formed of, for example, an Al plate 12a. The plate thickness of the circuit pattern forming metal plate may be set to 0.4 mm or more and 1.2 mm or less as a practical range, for example. In the case shown in FIG. 1, the circuit pattern forming metal plate 12 has a circuit pattern P formed by an etching process.

放熱用金属板１３は、例えば、Al板１３ａに構成されている。放熱用金属板１３の板厚は、例えば、実用的範囲としては、０．３ｍｍ以上、１．２ｍｍ以下に設定されている。   The metal plate 13 for heat dissipation is comprised by the Al plate 13a, for example. The plate | board thickness of the metal plate 13 for thermal radiation is set to 0.3 mm or more and 1.2 mm or less as a practical range, for example.

セラミックス基板１１と回路パターン形成用金属板１２、放熱用金属板１３をそれぞれ接合するろう材には、例えば、Al-Si系の活性ろう材が使用されている。   For example, an Al—Si based active brazing material is used as the brazing material for joining the ceramic substrate 11 to the circuit pattern forming metal plate 12 and the heat radiating metal plate 13.

また、セラミックス回路基板１０を構成するセラミックス基板１１の板厚ｔ１、回路パターン形成用金属板１２の板厚ｔ２、放熱用金属板１３の板厚ｔ３との間には、（回路パターン形成用金属板１２と放熱用金属板１３との総和板厚）／セラミックス基板１１の板厚とで示される板厚比：（ｔ２＋ｔ３）／ｔ１が、２以上、１２未満であるように設定されている。
尚、図１に示す場合には、セラミックス基板１１、回路パターン形成用金属板１２、放熱用金属板１３の各々の板厚は、図面の分かり易さを優先させるために、正確な板厚比を再現するものではない。 Further, between the plate thickness t1 of the ceramic substrate 11 constituting the ceramic circuit substrate 10, the plate thickness t2 of the metal plate 12 for circuit pattern formation, and the plate thickness t3 of the metal plate 13 for heat dissipation (the metal for circuit pattern formation) The plate thickness ratio: (t2 + t3) / t1 expressed by the total plate thickness of the plate 12 and the heat radiating metal plate 13) / the plate thickness of the ceramic substrate 11 is set to be 2 or more and less than 12.
In the case shown in FIG. 1, the thickness of each of the ceramic substrate 11, the circuit pattern forming metal plate 12, and the heat radiating metal plate 13 is an accurate plate thickness ratio in order to prioritize easy understanding of the drawing. Is not reproduced.

表１はセラミックス回路基板における見掛けの熱膨張係数の算出結果を示す。
かかる構成のセラミックス回路基板１０では、その見掛けの熱膨張係数が放熱ベース（図２参照）として使用されるAl板の熱膨張係数に近い値に設定されていることとなる。すなわち、見掛けの熱膨張係数は、１０ｐｐｍ／ｋ以上、１５ｐｐｍ／ｋ以下に設定されている。 Table 1 shows the calculation result of the apparent thermal expansion coefficient in the ceramic circuit board.
In the ceramic circuit board 10 having such a configuration, the apparent thermal expansion coefficient is set to a value close to the thermal expansion coefficient of the Al plate used as the heat dissipation base (see FIG. 2). That is, the apparent thermal expansion coefficient is set to 10 ppm / k or more and 15 ppm / k or less.

Figure 2006351834
Figure 2006351834

表１の右欄には、図１に示すセラミックス回路基板１０において、セラミックス基板１１の板厚ｔ１＝０．３ｍｍ、回路パターン形成用金属板１２の板厚ｔ２＝０．６ｍｍ、放熱用金属板１３の板厚ｔ３＝０．５ｍｍに設定した場合の見掛けの熱膨張係数を示した。ここで、見掛けの熱膨張係数は、セラミックス基板（図中、基板と表示）１１、回路パターン形成用金属板（図中、回路板と表示）１２、放熱用金属板（図中、放熱板と表示）１３の各々のヤング率（Ｅ）、熱膨張係数（σ）、板厚（ｔ）を基に算出される。すなわち、回路板、基板、放熱板の各々の部材のＥ・σ・ｔの積の総和を一体化セラミックス回路基板と見なし、Σ（Ｅ×σ×ｔ）／Σ（Ｅ×ｔ）の値を求めて見掛けの熱膨張係数（平均熱膨張係数）を算出している。かかる算出結果から分かるように、図１に示すセラミックス回路基板の見掛けの熱膨張係数は１２．６３ｐｐｍ／ｋに設定されている。   In the right column of Table 1, in the ceramic circuit board 10 shown in FIG. 1, the thickness t1 of the ceramic substrate 11 = 0.3 mm, the thickness t2 of the circuit pattern forming metal plate 12 = 0.6 mm, the metal plate for heat dissipation The apparent thermal expansion coefficient when the plate thickness t3 of 13 is set to 0.5 mm is shown. Here, the apparent thermal expansion coefficient is as follows: ceramic substrate (indicated as substrate in the figure) 11, metal plate for circuit pattern formation (indicated as circuit board in the figure) 12, metal plate for heat dissipation (in the figure, heat sink and (Indication) Calculation is performed based on each Young's modulus (E), thermal expansion coefficient (σ), and plate thickness (t). That is, the sum of the products of E · σ · t of each member of the circuit board, the substrate, and the heat sink is regarded as an integrated ceramic circuit substrate, and the value of Σ (E × σ × t) / Σ (E × t) is The apparent thermal expansion coefficient (average thermal expansion coefficient) is calculated. As can be seen from the calculation result, the apparent thermal expansion coefficient of the ceramic circuit board shown in FIG. 1 is set to 12.63 ppm / k.

表１に例示するように、本発明に係るセラミックス回路基板１０では、その見掛けの熱膨張係数が、Alの熱膨張係数に近い値をとるように制御されているため、例えば、図２に示す半導体モジュール１００に構成した際の放熱ベース２０にAl板２０ａを用いた場合には、はんだを介して接合したセラミックス回路基板１０と放熱ベース２０とは、冷熱サイクル試験では、略似た熱的挙動を示すこととなり、両者の熱膨張係数の差に起因する大きな残留応力に基づく剥離現象が発生しない。   As illustrated in Table 1, in the ceramic circuit board 10 according to the present invention, the apparent thermal expansion coefficient is controlled to take a value close to the thermal expansion coefficient of Al. When the Al plate 20a is used for the heat dissipation base 20 when the semiconductor module 100 is configured, the ceramic circuit board 10 and the heat dissipation base 20 joined via solder have substantially similar thermal behavior in the thermal cycle test. Therefore, the peeling phenomenon based on the large residual stress due to the difference between the thermal expansion coefficients of the two does not occur.

尚、冷熱サイクル試験は、例えば、冷熱サイクル試験機（エスペック社製ＴＡＳ-201S）に、セラミックス回路基板と放熱ベースからなる半導体モジュールを挿入し、-４０℃×３０分保持、室温×１０分保持、１２５℃×３０分保持の低温域から高温域までの試験条件に試験体を置いて、どの程度のサイクル数で剥離破壊が発生するかを、超音波画像診断装置（日立建機製マイスコープ）を用いて観察する。冷熱サイクル試験の規格では、例えば、一般産業用半導体モジュールとしては、１０００サイクル以上、ハイブリッド車、電車用半導体モジュールとしては３０００サイクル以上の高信頼性が要求されている。   In the thermal cycle test, for example, a semiconductor module composed of a ceramic circuit board and a heat dissipation base is inserted into a thermal cycle tester (TASPE 201S manufactured by Espec Corp.) and held at −40 ° C. for 30 minutes and at room temperature for 10 minutes. Ultrasonic diagnostic imaging equipment (Hitachi Construction Machinery Myscope) shows the number of cycles at which a specimen is placed under test conditions from low to high temperatures at 125 ° C x 30 minutes. Observe with. In the standard of the thermal cycle test, for example, high reliability of 1000 cycles or more is required for a general industrial semiconductor module, and 3000 cycles or more is required for a hybrid vehicle or a train semiconductor module.

上記説明では、回路パターン形成用金属板１２としてAl板１２ａ、放熱用金属板１３としてAl板１３ａをそれぞれ用いた場合を示したが、Al合金板を用いても一向に構わない。Al合金板としては、例えば、Al-Si合金およびAl/Ni/Alのクラッド材も一例として挙げることができる。
すなわち、回路パターン形成用金属板１２と放熱用金属板１３の双方にAi-Si合金板を使用しても、あるいは、回路パターン形成用金属板１２と放熱用金属板１３のいずれか一方にAl-Si合金板あるいはAl/Ni/Alを使用し、他方にAl板を用いても構わない。ただし、回路パターン形成用金属板としては、通電側であるため、高い導電性ならびに回路パターン形成が必要なため、易エッチング性が求められる。したがって、Al-Si合金板およびAl/Ni/Alクラッド材は、放熱用金属板として用いる方が望ましい。 In the above description, an Al plate 12a is used as the circuit pattern forming metal plate 12 and an Al plate 13a is used as the heat radiating metal plate 13, but an Al alloy plate may be used. Examples of the Al alloy plate include an Al—Si alloy and an Al / Ni / Al clad material.
That is, even if an Ai-Si alloy plate is used for both the circuit pattern forming metal plate 12 and the heat radiating metal plate 13, or either one of the circuit pattern forming metal plate 12 and the heat radiating metal plate 13 is made of Al. -Si alloy plate or Al / Ni / Al may be used, and Al plate may be used for the other. However, since the metal plate for circuit pattern formation is on the energization side, high conductivity and circuit pattern formation are required, and thus easy etching is required. Therefore, it is desirable to use the Al—Si alloy plate and the Al / Ni / Al clad material as a heat radiating metal plate.

かかる構成のセラミックス回路基板１０を用いて構成した半導体モジュール１００は、図２に示すように、セラミックス回路基板１０を構成する回路パターン形成用金属板１２の素子搭載部に半導体素子３０が１番はんだ４１を介して接合されている。半導体素子３０は、回路パターン形成用金属板１２に、金線３１ａ等のワイヤー３１でワイヤーボンディングされて電気的接続が形成されている。
このように半導体素子３０が搭載された回路パターン形成用金属板１２を有するセラミックス回路基板１０は、その放熱用金属板１３が２番はんだ４２を介して、放熱ベース２０に接合されている。尚、放熱ベース２０には、ねじ止め用のねじ孔２１が設けられている。 As shown in FIG. 2, the semiconductor module 100 configured using the ceramic circuit board 10 having such a configuration has the semiconductor element 30 as the first solder on the element mounting portion of the circuit pattern forming metal plate 12 constituting the ceramic circuit board 10. 41 is joined. The semiconductor element 30 is wire-bonded to the circuit pattern forming metal plate 12 with a wire 31 such as a gold wire 31a to form an electrical connection.
In this way, the ceramic circuit board 10 having the circuit pattern forming metal plate 12 on which the semiconductor element 30 is mounted has the heat radiating metal plate 13 joined to the heat radiating base 20 via the second solder 42. The heat dissipation base 20 is provided with screw holes 21 for screwing.

２番はんだ４２は、例えば、リフロー処理で行われる。リフロー処理で使用する２番はんだとしては、例えば、Sn-Pb系はんだ、あるいはSn-Ag-Cu系またはSn-Sb系のPbフリーはんだが使用されている。勿論、それ以外の組成のはんだを使用しても構わないが、かかる構成のはんだを用いると、よりセラミックス回路基板１０と放熱ベース２０との接合剥離を発生させない構成とすることができる。   The second solder 42 is performed by, for example, a reflow process. As the second solder used in the reflow process, for example, Sn-Pb solder, Sn-Ag-Cu solder, or Sn-Sb solder free Pb is used. Of course, a solder having a composition other than that may be used. However, when the solder having such a configuration is used, the ceramic circuit board 10 and the heat dissipation base 20 can be further prevented from being peeled off.

かかるはんだには、図示はしないが、粒径が２０μｍ以上、３００μｍ以下のNi、Cu、Mo、Wの粉末が１質量％以上、３０質量％以下の範囲で含まれている。セラミックス回路基板１０における見掛けの熱膨張係数を放熱ベース２０のAl板２０ａの熱膨張係数に近づけるために、回路パターン形成用金属板１２のAl板１２ａの板厚を大きく設定しているが、粒径２０〜３００μｍのNi、Cu、Mo、Wの粉末が１質量％以上、３０質量％以下の範囲で含まれているため、前述の如く、回路パターン形成用金属板１２のセラミックス基板１１に対しての相対厚みを大きくしたことに基づくセラミックス回路基板１０の重量化による２番はんだ４２の押しつぶしが発生しない。   Although not shown, such solder contains Ni, Cu, Mo, W powder having a particle size of 20 μm or more and 300 μm or less in a range of 1% by mass or more and 30% by mass or less. In order to make the apparent thermal expansion coefficient of the ceramic circuit board 10 close to the thermal expansion coefficient of the Al plate 20a of the heat dissipation base 20, the plate thickness of the Al plate 12a of the circuit pattern forming metal plate 12 is set large. Since Ni, Cu, Mo, and W powder having a diameter of 20 to 300 μm are included in the range of 1% by mass to 30% by mass, as described above, the ceramic substrate 11 of the circuit pattern forming metal plate 12 is used. The second solder 42 is not crushed due to the weight of the ceramic circuit board 10 based on the increased relative thickness.

かかる所定粒径の粉末が含まれていない場合には、２番はんだ４２が押しつぶされて、２番はんだ４２がセラミックス回路基板１０の放熱用金属板１３と放熱ベース２０との間から押し出され、放熱用金属板１３と放熱ベース２０との間に気泡が残るような状態で接合されることとなる。かかる放熱用金属板１３と放熱ベース２０とは、半導体素子３０の熱を逃がす放熱ルートとして機能するため、両者の接合部に気泡が残留することは、前述の如く、その半導体モジュールの放熱性を低下させることとなり好ましくない。   When the powder having the predetermined particle diameter is not included, the second solder 42 is crushed and the second solder 42 is pushed out between the heat radiation metal plate 13 and the heat radiation base 20 of the ceramic circuit board 10, It joins in the state which a bubble remains between the metal plate 13 for thermal radiation, and the thermal radiation base 20. FIG. Since the heat radiating metal plate 13 and the heat radiating base 20 function as a heat radiating route for releasing the heat of the semiconductor element 30, air bubbles remain at the joint between the two, as described above, to improve the heat radiating property of the semiconductor module. It is not preferable because it lowers.

本発明の半導体モジュール１００は、上記のように、２番はんだ４２にスペーシング機能を発揮する所定粒径の粉末を所定量だけ含有させることで、見掛けの熱膨張係数を放熱ベース２０の熱膨張係数に近づけるために回路パターン形成用金属板１２の板厚を厚くしても、２番はんだ４２を押しつぶすことなく、半導体素子３０の放熱パスを確保した構成を有している。   As described above, the semiconductor module 100 according to the present invention includes the second solder 42 with a predetermined amount of powder having a predetermined particle diameter that exhibits a spacing function, so that the apparent thermal expansion coefficient can be increased. Even if the thickness of the circuit pattern forming metal plate 12 is increased in order to approach the coefficient, the heat radiation path of the semiconductor element 30 is secured without crushing the second solder 42.

図３には、本発明に係るセラミックス回路基板１０、半導体モジュール１００とその効果を従来構成と比較するために、比較例として、セラミックス基板１１として窒化アルミニウム板１１ｂを用い、回路パターン形成用金属板１２、放熱用金属板１３にそれぞれAlを用いた構成のセラミックス回路基板１０ａ、半導体モジュール１００ａを示した。
図３に示す構成では、例えば、セラミックス基板１１は、板厚ｔ１＝０．６３５ｍｍの窒化アルミニウム板１１ｂに構成されている。回路パターン形成用金属板１２は板厚ｔ２＝０．４ｍｍのAl板１２ａに、放熱用金属板１３は板厚ｔ３＝０．３ｍｍのAl板１３ａにそれぞれ構成されている。窒化アルミニウム板１１ｂに構成したセラミックス基板１１と、回路パターン形成用金属板１２、放熱用金属板１３は、それぞれ図示はしないがろう材により接合されている。かかる接合に使用するろう材は、例えば、Al-Si活性ろう材を使用した。 In FIG. 3, in order to compare the ceramic circuit board 10 and the semiconductor module 100 according to the present invention and the effects thereof with the conventional configuration, as a comparative example, an aluminum nitride plate 11b is used as the ceramic substrate 11, and a circuit pattern forming metal plate is used. 12 shows a ceramic circuit board 10a and a semiconductor module 100a each having a structure in which Al is used for the metal plate 13 for heat dissipation.
In the configuration shown in FIG. 3, for example, the ceramic substrate 11 is configured as an aluminum nitride plate 11b having a plate thickness t1 = 0.635 mm. The circuit pattern forming metal plate 12 is constituted by an Al plate 12a having a plate thickness t2 = 0.4 mm, and the heat radiating metal plate 13 is constituted by an Al plate 13a having a plate thickness t3 = 0.3 mm. The ceramic substrate 11 formed on the aluminum nitride plate 11b, the circuit pattern forming metal plate 12, and the heat radiating metal plate 13 are joined by a brazing material (not shown). As the brazing material used for such joining, for example, an Al—Si active brazing material was used.

かかる構成のセラミックス回路基板１０ａの回路パターン形成用金属板１２上には、図３に示すように、素子搭載部に半導体素子３０が１番はんだ４１を介して搭載されている。併せて、セラミックス回路基板１０ａの放熱用金属板１３側は、２番はんだ４２を介して、Al板２０ａに構成した放熱ベース２０に接合されている。   As shown in FIG. 3, the semiconductor element 30 is mounted on the element mounting portion via the first solder 41 on the circuit pattern forming metal plate 12 of the ceramic circuit board 10 a having such a configuration. In addition, the heat dissipation metal plate 13 side of the ceramic circuit board 10a is joined to the heat dissipation base 20 formed on the Al plate 20a via a second solder 42.

かかる構成の半導体モジュール１００ａで使用されているセラミックス回路基板１０ａについて、表１の左欄に示すように、見掛けの熱膨張係数を算出した。見掛けの熱膨張係数は、図１の例と同様に回路板、基板、放熱板の各々の部材のＥ・σ・ｔを基に算出し８．４８と、図１に示す本発明に係るセラミックス回路基板１０の１２．６３に比べて低い値となった。すなわち、セラミックス基板１１に窒化アルミニウム板１１ｂを用いた場合には、放熱ベース２０としてAl板２０ａを使用すると、両者の熱膨張係数の差が大きく、冷熱サイクルにおいて放熱用金属板１３と放熱ベース２０との接合剥離障害が発生する可能性が大きいことを示唆している。   As shown in the left column of Table 1, an apparent thermal expansion coefficient was calculated for the ceramic circuit board 10a used in the semiconductor module 100a having such a configuration. The apparent thermal expansion coefficient is 8.48 calculated based on E · σ · t of each member of the circuit board, the substrate and the heat radiating plate as in the example of FIG. 1, and the ceramic according to the present invention shown in FIG. The value was lower than 12.63 of the circuit board 10. That is, when the aluminum nitride plate 11b is used for the ceramic substrate 11, if the Al plate 20a is used as the heat radiating base 20, the difference in thermal expansion coefficient between the two is large, and the heat radiating metal plate 13 and the heat radiating base 20 are used in a cooling cycle. This suggests that there is a high possibility that a bond peeling failure will occur.

また、図２に示すように、熱抵抗値も、図３に示す本発明に係るセラミックス回路基板１０の方（熱抵抗値：０．２０℃／Ｗ）が、図３に示す上記構成の場合（熱抵抗値：０．２５℃／Ｗ）に比べて８０％に低減されていることが確認される。図３に示す上記構成では、図２に示す構成で使用した窒化珪素板１１ａの熱伝導率９０W/m.Kよりも大きな熱伝導率１７０W/m.Kの窒化アルミニウム板１１ｂを使用したにもかかわらず、熱抵抗値は低くなっている。   Further, as shown in FIG. 2, the thermal resistance value of the ceramic circuit board 10 according to the present invention shown in FIG. 3 (thermal resistance value: 0.20 ° C./W) is the above-described configuration shown in FIG. It is confirmed that it is reduced to 80% compared to (thermal resistance value: 0.25 ° C./W). In the above configuration shown in FIG. 3, although the aluminum nitride plate 11b having a thermal conductivity of 170 W / mK larger than the thermal conductivity of 90 W / mK of the silicon nitride plate 11a used in the configuration shown in FIG. The resistance value is low.

これは、本発明に係る構成の方が熱放散性に優れるAlを用いた回路板を厚く構成しているので、Ｓｉチップの動作中に生じる熱を速やかに回路内で面内方向へ拡散することができ、当構成での熱抵抗が低減されている。
なお、表１に示す熱抵抗値は、図２および図３の構成のモジュールを試作し、熱抵抗評価システム（キャッツ電子製モデルDV２４０）用いて評価したものである。評価に供したＳｉチップは、ダイオードチップで、これを３枚、回路基板上に実装したものである。 This is because the circuit board using Al, which is superior in heat dissipation in the configuration according to the present invention, is thickened, so that heat generated during the operation of the Si chip is quickly diffused in the in-plane direction in the circuit. And the thermal resistance in this configuration is reduced.
Note that the thermal resistance values shown in Table 1 were evaluated using a thermal resistance evaluation system (Cats Electronics Model DV240) manufactured by making a module having the configuration shown in FIGS. The Si chip used for the evaluation was a diode chip, and three of these were mounted on a circuit board.

使用するセラミックス基板１１を、窒化珪素板１１ａから窒化アルミニウム板１１ｂに変えるだけで、表１に示すように、見掛けの熱膨張係数が大きく異なり、その結果が放熱ベース２０との冷熱サイクル時の熱的挙動の差異を広げ、剥離障害に発展するものと考えられる。
窒化珪素板１１ａが窒化アルミニウム板１１ｂよりも有効である理由の一つには、窒化珪素板１１ａの方が窒化アルミニウム板１１ｂよりも機械的強度、破壊靱性が大きく、その分回路パターン形成用金属板１２として板厚を厚くしたAl板１２ａを載せても、薄い板厚で済ませることができ、結果としてセラミックス回路基板１０の異種材の接合構造における窒化珪素板１１ａの割合を減じて、セラミックス回路基板１０の見掛けの熱膨張係数を放熱ベース２０のAl板２０ａに近づけることができるのである。 By simply changing the ceramic substrate 11 to be used from the silicon nitride plate 11a to the aluminum nitride plate 11b, as shown in Table 1, the apparent thermal expansion coefficient is greatly different, and the result is the heat during the cooling cycle with the heat radiating base 20. It is thought that the difference in the mechanical behavior is widened and develops into a peeling failure.
One of the reasons why the silicon nitride plate 11a is more effective than the aluminum nitride plate 11b is that the silicon nitride plate 11a has higher mechanical strength and fracture toughness than the aluminum nitride plate 11b. Even if an Al plate 12a having a large thickness is placed as the plate 12, a thin plate thickness can be achieved. As a result, the ratio of the silicon nitride plate 11a in the joining structure of different materials of the ceramic circuit substrate 10 is reduced, and the ceramic circuit is reduced. The apparent thermal expansion coefficient of the substrate 10 can be brought close to the Al plate 20 a of the heat dissipation base 20.

本発明に係るセラミックス回路基板１０における見掛けの熱膨張係数は、上記比較からも分かるように、使用する素材を変更することで所定範囲に制御することができるが、使用する素材を変更することなく、板厚を種々変更することでもその制御が容易に行える。
表２はセラミックス回路基板の見掛けの熱膨張係数が、回路パターン形成用金属板、放熱用金属板の板厚で制御可能なことを示している。 The apparent thermal expansion coefficient of the ceramic circuit board 10 according to the present invention can be controlled within a predetermined range by changing the material to be used, as can be seen from the above comparison, but without changing the material to be used. The control can be easily performed by variously changing the plate thickness.
Table 2 shows that the apparent thermal expansion coefficient of the ceramic circuit board can be controlled by the thickness of the circuit pattern forming metal plate and the heat radiating metal plate.

Figure 2006351834
Figure 2006351834

表２に示す場合には、図１に示すセラミックス回路基板１０の構成で、セラミックス基板（Si3N4板基板）１１の板厚ｔ１を０．３ｍｍに固定した状態で、回路パターン形成用金属板（Cu回路板）１２、放熱用金属板（Cu放熱板）１３の板厚ｔ２、ｔ３をそれぞれ変化させた場合の見掛けの熱膨張係数の変化を示している。板厚を変えることで、見掛けの熱膨張係数は、約９．６３から約１６．０６まで大きく変化していることが分かる。
９．６３の見掛けの熱膨張係数を示す回路基板では、耐冷熱サイクル試験では１０００回未満で剥離が発生する場合が見られる等好ましくない結果が発生した。一方、見掛けの熱膨張係数が１０．３６の回路基板では、板厚比が限度ギリギリではあるが、耐冷熱サイクル試験では、少なくとも１０００回までは剥離現象等が発生しておらず、本発明における見掛けの熱膨張係数を１０ｐｐｍ／ｋ以上、１７ｐｐｍ／ｋ以下と設定したことの有効性を示す一例となる。 In the case shown in Table 2, with the configuration of the ceramic circuit board 10 shown in FIG. 1, the circuit pattern forming metal with the thickness t1 of the ceramic substrate (Si 3 N 4 plate substrate) 11 fixed to 0.3 mm. The change of the apparent thermal expansion coefficient at the time of changing plate | board thickness t2, t3 of the board (Cu circuit board) 12 and the metal plate for heat radiation (Cu heat sink) 13 is shown. It can be seen that the apparent thermal expansion coefficient is greatly changed from about 9.63 to about 16.06 by changing the plate thickness.
In the circuit board showing an apparent thermal expansion coefficient of 9.63, an unfavorable result occurred, such as a case where peeling occurred in less than 1000 times in the cold-heat cycle test. On the other hand, in the circuit board having an apparent thermal expansion coefficient of 10.36, the plate thickness ratio is at the limit, but in the thermal cycle test, the peeling phenomenon or the like has not occurred until at least 1000 times. This is an example showing the effectiveness of setting the apparent thermal expansion coefficient to 10 ppm / k or more and 17 ppm / k or less.

表３には、見掛けの熱膨張係数と板厚比との関係を示している。セラミックス基板（Si3N4板基板）１１の板厚ｔ１を０．２ｍｍ、０．３ｍｍおよび０．４ｍｍにそれぞれ固定しておき、回路パターン形成用金属板（Al回路板）１２の板厚ｔ２と放熱用金属板（Al放熱板）１３の板厚ｔ３との両者の総和板厚を変化させた場合の見掛けの熱膨張係数と板厚比（ｔ２＋ｔ３）／ｔ１を示し、さらに図２に示す半導体モジュールを構成して上述の冷熱サイクル試験を行って評価した。表３には剥離サイクル数と外観検査の結果を同時に示す。
尚、本発明の開発においては、発明品の耐冷熱サイクル性は、表３に示すように、前記冷熱サイクル試験においては１０００回以上の結果となるものを有効と評価した。 Table 3 shows the relationship between the apparent thermal expansion coefficient and the plate thickness ratio. The plate thickness t1 of the ceramic substrate (Si 3 N 4 plate substrate) 11 is fixed to 0.2 mm, 0.3 mm and 0.4 mm, respectively, and the plate thickness t2 of the circuit pattern forming metal plate (Al circuit board) 12 is set. FIG. 2 shows the apparent thermal expansion coefficient and the plate thickness ratio (t2 + t3) / t1 when the total thickness of the plate and the thickness t3 of the heat radiating metal plate (Al heat radiating plate) 13 is changed. The semiconductor module was configured and evaluated by performing the above-described cooling cycle test. Table 3 shows the number of peeling cycles and the results of visual inspection at the same time.
In the development of the present invention, as shown in Table 3, the thermal cycle resistance of the inventive product was evaluated as effective if it resulted in 1000 times or more in the thermal cycle test.

Figure 2006351834
Figure 2006351834

表３の結果から、セラミックス回路基板１０の見掛けの熱膨張係数が、前記の如く、１０ｐｐｍ／ｋ以上、１７ｐｐｍ／ｋ以下の範囲になるように制御すると、耐冷熱サイクル性が向上することが確認された。また、見掛けの熱膨張係数を満足し、さらに板厚比が２以上、６以下の範囲にあるとさらに望ましいことが分かる。
かかる結果は、セラミックス回路基板１０を構成するセラミックス基板１１、回路パターン形成用金属板１２、放熱用金属板１３の素材が同じである場合には、見掛けの熱膨張係数を所定範囲に制御するためには、一々見掛けの熱膨張係数を算出するまでもなく、簡便には、板厚比を確認することで大まかにその有効性の評価が容易に行えることが分かる。
しかし、板厚比での判定は、その上限値、下限値の近辺ではその判定性を一義的に判断することができない場合も存在するため、厳密には、前述の算出式を用いて個々に見掛けの熱膨張係数を試算してみることが必要である。すなわち、板厚比は、その上下の限界値近辺では熱膨張係数の算出結果と併せて使用すべきもので、あくまで、大まかな有効性の評価を行う簡便な判定基準であると、その精度の限界性を認識した上で使用すべきものと考えるのが好ましい。 From the results of Table 3, it is confirmed that when the apparent thermal expansion coefficient of the ceramic circuit board 10 is controlled to be in the range of 10 ppm / k or more and 17 ppm / k or less as described above, the thermal cycle resistance is improved. It was. It can also be seen that it is more desirable if the apparent thermal expansion coefficient is satisfied and the plate thickness ratio is in the range of 2 to 6.
As a result, when the ceramic substrate 11, the circuit pattern forming metal plate 12, and the heat radiating metal plate 13 constituting the ceramic circuit substrate 10 are made of the same material, the apparent thermal expansion coefficient is controlled within a predetermined range. Therefore, it is understood that the effectiveness can be roughly evaluated easily by simply checking the thickness ratio, without calculating the apparent thermal expansion coefficient.
However, since there are cases where the determination by the plate thickness ratio cannot be determined unambiguously in the vicinity of the upper limit value and the lower limit value, strictly speaking, using the above calculation formula, It is necessary to estimate the apparent thermal expansion coefficient. In other words, the plate thickness ratio should be used in conjunction with the calculation result of the thermal expansion coefficient in the vicinity of the upper and lower limit values, and it is only a simple judgment criterion for roughly evaluating the effectiveness. It is preferable that it should be used after recognizing sex.

以上に説明の本発明に係るセラミックス回路基板１０の製造は、図４に模式的に示す手順で行う。すなわち、セラミックス回路基板１０の構成原料をステップＳ１００でボールミル混合する。混合した原料スラリーを脱泡・増粘した後、ステップＳ２００で、ドクターブレードで所定板厚でシート成形して成形体を得る。ステップＳ３００で成形したシートを焼結炉内で１８００℃〜１９００℃×５時間保持の０．９２ＭＰａの窒素雰囲気で焼結し、更に１７００℃〜１８００℃×５時間保持にて焼結時の反り矯正を行い、更にサンドブラストにより表面を整えセラミックス基板１１として使用する焼結体の窒化珪素板１１ａを得る。   The ceramic circuit board 10 according to the present invention described above is manufactured according to the procedure schematically shown in FIG. That is, the constituent materials of the ceramic circuit board 10 are ball mill mixed in step S100. After defoaming and thickening the mixed raw material slurry, in step S200, a sheet is formed with a doctor blade at a predetermined plate thickness to obtain a formed body. The sheet formed in step S300 is sintered in a sintering furnace in a nitrogen atmosphere of 0.92 MPa held at 1800 ° C. to 1900 ° C. for 5 hours, and further warped during sintering by holding at 1700 ° C. to 1800 ° C. for 5 hours. Correction is performed, and the surface is further prepared by sandblasting to obtain a sintered silicon nitride plate 11 a used as the ceramic substrate 11.

その後、ステップＳ４００で、セラミックス基板１１の一方の面にAl-Si系の活性ろう材を介して回路パターン形成用金属板１２としてのAl板１２ａを、他方の面に同様のろう材を介して放熱用金属板１３としてのAl板１３ａをそれぞれ接合する。その後、ステップＳ５００で、セラミックス基板１１上の回路パターン形成用金属板１２をエッチング処理して回路パターンを形成する。ステップＳ６００で回路パターン形成後の回路パターン形成用金属板１２上にメッキを施し、セラミックス回路基板１０が製造される。   Thereafter, in step S400, an Al plate 12a serving as a circuit pattern forming metal plate 12 is placed on one surface of the ceramic substrate 11 via an Al—Si-based active brazing material, and a similar brazing material is placed on the other surface. The Al plates 13a as the heat radiating metal plates 13 are respectively joined. Thereafter, in step S500, the circuit pattern forming metal plate 12 on the ceramic substrate 11 is etched to form a circuit pattern. In step S600, the circuit pattern forming metal plate 12 after the circuit pattern is formed is plated, and the ceramic circuit board 10 is manufactured.

以上、本発明者によってなされた発明を実施の形態に基づき具体的に説明したが、本発明は前記実施の形態に限定されるものではなく、Alベースの合金を用いた場合も同様の効果が得られることは勿論のこと、その要旨を逸脱しない範囲で種々変更可能であることはいうまでもない。   As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and the same effect can be obtained when an Al-based alloy is used. Needless to say, various changes can be made without departing from the scope of the invention.

本発明はセラミックス回路基板、及びそれを使用した半導体モジュールの分野で、冷熱サイクルの耐性を向上させるのに有効に利用することができる。   INDUSTRIAL APPLICABILITY The present invention can be effectively used in the field of ceramic circuit boards and semiconductor modules using the ceramic circuit boards to improve the heat cycle resistance.

本発明の一実施の形態であるセラミックス回路基板の全体構成を示す断面説明図である。It is a section explanatory view showing the whole ceramic circuit board composition which is one embodiment of the present invention. 本発明の一実施の形態であるセラミックス回路基板を用いた半導体モジュールの全体構成を示す断面説明図である。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an explanatory cross-sectional view showing an overall configuration of a semiconductor module using a ceramic circuit board according to an embodiment of the present invention. 窒化アルミニウムをセラミックス基板に構成したセラミックス回路基板を用いた半導体モジュールの全体構成を示す断面説明図である。It is sectional explanatory drawing which shows the whole structure of the semiconductor module using the ceramic circuit board which comprised the aluminum nitride in the ceramic substrate. 本発明に係るセラミックス回路基板の製造手順を模式的に示すフロー図である。It is a flowchart which shows typically the manufacture procedure of the ceramic circuit board which concerns on this invention.

符号の説明Explanation of symbols

１０ セラミックス回路基板
１０ａ セラミックス回路基板
１１ セラミックス基板
１１ａ 窒化珪素板
１１ｂ 窒化アルミニウム板
１２ 回路パターン形成用金属板
１２ａ Al板
１３ 放熱用金属板
１３ａ Al板
２０ 放熱ベース
２０ａ Al板
２１ ねじ孔
３０ 半導体素子
３１ ワイヤー
３１ａ 金線
４１ １番はんだ
４２ ２番はんだ
１００ 半導体モジュール
１００ａ 半導体モジュール
Ｐ 回路パターン
Ｓ１００、Ｓ２００、Ｓ３００、Ｓ４００、Ｓ５００、Ｓ６００ ステップ
ｔ１ 板厚
ｔ２ 板厚
ｔ３ 板厚 DESCRIPTION OF SYMBOLS 10 Ceramic circuit board 10a Ceramic circuit board 11 Ceramic board 11a Silicon nitride board 11b Aluminum nitride board 12 Metal plate for circuit pattern formation 12a Al board 13 Metal plate for heat radiation 13a Al board 20 Heat radiation base 20a Al board 21 Screw hole 30 Semiconductor element 31 Wire 31a Gold wire 41 First solder 42 Second solder 100 Semiconductor module 100a Semiconductor module P Circuit patterns S100, S200, S300, S400, S500, S600 Step t1 Plate thickness t2 Plate thickness t3 Plate thickness

Claims (4)

セラミックス基板の一方の面に回路パターン形成用金属板が設けられ、前記セラミックス基板の他方の面に放熱用金属板が設けられたセラミックス回路基板であって、前記回路パターン形成用金属板は、AlまたはAl合金で形成され、前記放熱用金属板は、AlまたはAl合金で形成され、前記セラミックス基板、前記回路パターン形成用金属板、前記放熱用金属板の各々のヤング率、線膨張率、板厚に基づき算出される前記セラミックス回路基板の見掛けの熱膨張係数が、１０ｐｐｍ／ｋ以上、１７ｐｐｍ／ｋ以下であることを特徴とするセラミックス回路基板。 A ceramic circuit board provided with a metal plate for circuit pattern formation on one surface of a ceramic substrate and a metal plate for heat dissipation provided on the other surface of the ceramic substrate, wherein the metal plate for circuit pattern formation is made of Al Alternatively, the metal plate for heat dissipation is formed of Al or Al alloy, and the Young's modulus, linear expansion coefficient, plate of each of the ceramic substrate, the metal plate for circuit pattern formation, and the metal plate for heat dissipation An apparent thermal expansion coefficient of the ceramic circuit board calculated based on the thickness is 10 ppm / k or more and 17 ppm / k or less. 請求項１記載のセラミックス回路基板において、前記セラミックス基板は、板厚ｔ１が０．２ｍｍ以上、０．４ｍｍ以下であり、前記回路パターン形成用金属板は、板厚ｔ２が０．４ｍｍ以上、１．２ｍｍ以下であり、前記放熱用金属板は、板厚ｔ３が０．３ｍｍ以上、１．２ｍｍ以下であり、（前記回路パターン形成用金属板と前記放熱用金属板との総和板厚）／前記セラミックス基板の板厚とで示される板厚比（ｔ２＋ｔ３）／ｔ１が、２以上、１２未満であることを特徴とするセラミックス回路基板。 2. The ceramic circuit board according to claim 1, wherein the ceramic substrate has a plate thickness t1 of 0.2 mm or more and 0.4 mm or less, and the circuit pattern forming metal plate has a plate thickness t2 of 0.4 mm or more, 1 .2 mm or less, and the metal plate for heat dissipation has a plate thickness t3 of 0.3 mm or more and 1.2 mm or less (total thickness of the circuit pattern forming metal plate and the metal plate for heat dissipation) / A ceramic circuit board, wherein a thickness ratio (t2 + t3) / t1 indicated by a thickness of the ceramic substrate is 2 or more and less than 12. 請求項１または２記載のセラミックス回路基板において、前記セラミックス基板は、窒化珪素板であることを特徴とするセラミックス回路基板。 3. The ceramic circuit board according to claim 1, wherein the ceramic board is a silicon nitride plate. 請求項１〜３のいずれか１項に記載のセラミックス回路基板と、前記セラミックス回路基板の前記回路パターン形成用金属板の素子搭載部に搭載された半導体素子と、前記セラミックス回路基板が、はんだを介して接合されるAlまたはAl合金で形成される放熱ベースと、を有することを特徴とする半導体モジュール。 A ceramic circuit board according to any one of claims 1 to 3, a semiconductor element mounted on an element mounting portion of the circuit pattern forming metal plate of the ceramic circuit board, and the ceramic circuit board comprising solder And a heat dissipating base formed of Al or an Al alloy joined through the semiconductor module.
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008093808A1 (en) * 2007-01-31 2008-08-07 Ngk Insulators, Ltd. Heat spreader module, method for manufacturing the heat spreader module, and heat sink
JP2009212367A (en) * 2008-03-05 2009-09-17 Stanley Electric Co Ltd Semiconductor light-emitting device
US8415801B2 (en) 2009-06-04 2013-04-09 Honda Motor Co., Ltd. Semiconductor device having thermal endurance and method of manufacturing the same
JP2014030053A (en) * 2013-10-11 2014-02-13 Honda Motor Co Ltd Method for setting plate thickness of insulating substrate and metal plate of semiconductor device
JP2015170736A (en) * 2014-03-07 2015-09-28 国立研究開発法人物質・材料研究機構 Detachable current supply member for superconducting equipment and superconducting equipment using the same
US11439039B2 (en) 2020-12-07 2022-09-06 Hamilton Sundstrand Corporation Thermal management of electronic devices on a cold plate

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001144234A (en) * 1999-11-16 2001-05-25 Mitsubishi Materials Corp Semiconductor mounting insulation circuit substrate
JP2004158659A (en) * 2002-11-07 2004-06-03 Denki Kagaku Kogyo Kk Module structure and module employing same
JP2004356625A (en) * 2003-05-06 2004-12-16 Fuji Electric Device Technology Co Ltd Semiconductor device and method for manufacturing the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001144234A (en) * 1999-11-16 2001-05-25 Mitsubishi Materials Corp Semiconductor mounting insulation circuit substrate
JP2004158659A (en) * 2002-11-07 2004-06-03 Denki Kagaku Kogyo Kk Module structure and module employing same
JP2004356625A (en) * 2003-05-06 2004-12-16 Fuji Electric Device Technology Co Ltd Semiconductor device and method for manufacturing the same

Cited By (6)

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Publication number Priority date Publication date Assignee Title
WO2008093808A1 (en) * 2007-01-31 2008-08-07 Ngk Insulators, Ltd. Heat spreader module, method for manufacturing the heat spreader module, and heat sink
JP2009212367A (en) * 2008-03-05 2009-09-17 Stanley Electric Co Ltd Semiconductor light-emitting device
US8415801B2 (en) 2009-06-04 2013-04-09 Honda Motor Co., Ltd. Semiconductor device having thermal endurance and method of manufacturing the same
JP2014030053A (en) * 2013-10-11 2014-02-13 Honda Motor Co Ltd Method for setting plate thickness of insulating substrate and metal plate of semiconductor device
JP2015170736A (en) * 2014-03-07 2015-09-28 国立研究開発法人物質・材料研究機構 Detachable current supply member for superconducting equipment and superconducting equipment using the same
US11439039B2 (en) 2020-12-07 2022-09-06 Hamilton Sundstrand Corporation Thermal management of electronic devices on a cold plate

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