JP2006351794A - Field effect transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a field effect transistor having a structure capable of utilizing a field plate effect. <P>SOLUTION: A conductive gallium nitride substrate 13 comprises a first region 13c having first dislocation density, and a second region 13d having second dislocation density smaller than the first dislocation density. A gate electrode 17 is provided on a second part 15d of a gallium nitride base semiconductor region 15. A drain electrode 19 is provided on the second part 15d of the semiconductor region 15. A source electrode 21 is provided on the semiconductor region 15, and connected to the second part 15d of the semiconductor region 15. The dislocation density of the first part 15c of the semiconductor region 15 is larger than that of the second part 15d of the gallium nitride base semiconductor region 15. The conductivity of the first part 15c of the semiconductor region 15 is larger than that of the second part 15d of the semiconductor region 15. The source electrode 21 is connected to the first part 15c of the semiconductor region 15. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a field effect transistor.

  Non-Patent Document 1 describes a GaN-HEMT device that achieves higher breakdown voltage of a power device. This GaN-HEMT device is formed on an n-type conductive SiC substrate. The SiC substrate is electrically connected to the source electrode, whereby the SiC substrate also serves as a field plate electrode.

  Non-Patent Document 2 describes an AlGaN / GaN power HFET (Heterostructure Field Effect Transistor: HFET). The AlGaN / GaN HFET is formed on a conductive silicon substrate. The source electrode is connected to the silicon substrate through the surface via hole. As a result, the conductive silicon substrate acts as a field plate electrode.

  Patent Document 1 (Japanese Patent Laid-Open No. 2001-102307) describes a wafer plate manufacturing technique for forming a low dislocation region by concentrating dislocations using a facet structure. With this technique, a high-quality gallium nitride wafer is produced. A semiconductor laser device is manufactured using this gallium nitride wafer.

In Patent Document 2 (Japanese Patent Laid-Open No. 2003-124115) and Patent Document 3 (Japanese Patent Laid-Open No. 2003-273470), when manufacturing a semiconductor laser element or a gallium nitride electronic device using these substrates, The device structure is formed so as to avoid the core region where dislocations are concentrated.
IEICE technical report ED2003-202 MW2003-230, (2004-01) IEICE technical report ED2004-212, MW2004-219, (2005-01) JP 2001-102307 A JP 2003-124115 A JP 2003-273470 A

  In order to increase the breakdown voltage of a gallium nitride based semiconductor device, a back surface field plate structure is formed by grounding a conductive substrate with a source electrode as described in the prior art (Non-Patent Documents 1 and 2). This requires a complicated process.

  For example, in Non-Patent Document 2, a source via structure is adopted to provide a source electrode pad on the back surface of a substrate, and a via hole is formed using an inductively coupled plasma dry etching apparatus in order to form this structure. Although Non-Patent Document 1 does not describe in detail, in order to make the source electrode and the substrate have the same potential, a via hole structure similar to Non-Patent Document 2 or a structure in which the source electrode is connected to the substrate is required. is there. To that end, complicated process steps are still necessary. What is needed is a field effect transistor that can achieve the field plate effect with a simpler structure.

  Therefore, the present invention has been made in view of the above circumstances, and an object thereof is to provide a field effect transistor having a structure capable of using the field plate effect.

  According to one aspect of the present invention, a field effect transistor includes (a) a first surface having a front surface and a back surface, extending in a first direction from the back surface toward the surface, and having a first dislocation density. And a conductive gallium nitride substrate including a second region having a second dislocation density lower than the first dislocation density; and (b) provided on the first region of the conductive gallium nitride substrate. A gallium nitride based semiconductor region including a first portion formed and a second portion provided on the second region of the conductive gallium nitride substrate; and (c) the first portion of the gallium nitride based semiconductor region. A gate electrode provided on the second portion; (d) a drain electrode provided on the second portion of the gallium nitride based semiconductor region; and (e) provided on the gallium nitride based semiconductor region. The gallium nitride semiconductor A source electrode connected to the first portion of the region, and the dislocation density of the first portion of the gallium nitride based semiconductor region is greater than the dislocation density of the second portion of the gallium nitride based semiconductor region The conductivity of the first portion of the gallium nitride based semiconductor region is greater than the conductivity of the second portion of the gallium nitride based semiconductor region.

  According to this field effect transistor, the source electrode is connected to the conductive gallium nitride substrate through the first portion of the gallium nitride based semiconductor region. The potential of the source electrode is applied to the first portion having a large dislocation density, and the potential of the source electrode is transmitted to the conductive gallium nitride substrate.

  The field effect transistor according to the present invention may further include a source pad electrode provided on the back surface of the conductive gallium nitride substrate. According to this field effect transistor, since the source pad electrode is located on the back surface of the substrate of the field effect transistor, an area for providing the source pad electrode on the surface of the field effect transistor becomes unnecessary, and the gallium nitride based semiconductor Electrically connected to the source electrode through the first portion of the region and the conductive gallium nitride substrate.

In the field effect transistor according to the present invention, the second dislocation density in the second region of the conductive gallium nitride substrate may be 1 × 10 ⁶ cm ⁻² or less. According to this field effect transistor, the crystallinity of the second portion of the gallium nitride based semiconductor region is improved.

  In the field effect transistor according to the present invention, the gallium nitride based semiconductor region includes (b1) a first portion provided on the first region of the conductive gallium nitride substrate and the conductive gallium nitride substrate. A channel layer made of a first gallium nitride semiconductor and including a second portion provided on the second region, and (b2) provided on the first region of the conductive gallium nitride substrate. A first portion and a second portion provided on the second region of the conductive gallium nitride substrate, and an electron barrier layer made of a second gallium nitride semiconductor, One of the electron barrier layer and the channel layer is provided on the other, and the channel layer and the electron barrier layer form a heterojunction. According to this field effect transistor, a heterojunction transistor capable of using the field plate effect is provided.

  In the field effect transistor according to the present invention, the conductive gallium nitride substrate further includes a third region having a third dislocation density larger than the second dislocation density and extending in the first direction, The gallium nitride based semiconductor region includes a third portion provided on the third region of the conductive gallium nitride substrate, and the conductivity of the third portion of the gallium nitride based semiconductor region is The conductivity of the second portion of the gallium nitride based semiconductor region is larger than the conductivity of the second portion, and the gallium nitride based semiconductor region has an isolation region for separating the third portion of the gallium nitride based semiconductor region from the drain electrode. And the depth of the isolation region is deeper than the position of the heterojunction.

  According to this field effect transistor, dislocations can be collected in the first and third regions of the conductive gallium nitride substrate, and the dislocation density in the second region can be reduced. The gallium nitride based semiconductor region can include a third portion that is not connected to the source electrode, and the third portion is electrically isolated from the drain by the isolation region.

  In the field effect transistor according to the present invention, the first region of the conductive gallium nitride substrate extends along a second direction intersecting the first direction. According to this field effect transistor, dislocations can be collected in the first region of the conductive gallium nitride substrate, and the dislocation density in the second region can be reduced. In the second region, a high-quality semiconductor crystal for a field effect transistor can be produced.

  In the field effect transistor according to the present invention, the conductive gallium nitride substrate has a third dislocation density larger than the second dislocation density, and further includes a plurality of third regions extending in the first direction. The gallium nitride based semiconductor region includes a third portion provided on the third region of the conductive gallium nitride substrate, and the conductivity of the third portion of the gallium nitride based semiconductor region is The second region of the gallium nitride based semiconductor region is larger than the conductivity of the second portion, and the first region and the third region of the conductive gallium nitride substrate intersect the first direction. They are arranged in an array in the third direction. According to this field effect transistor, dislocations can be collected in the first and third regions of the conductive gallium nitride substrate, and the dislocation density in the second region can be reduced. In the second region, a high-quality semiconductor crystal for a field effect transistor can be produced.

  The above and other objects, features, and advantages of the present invention will become more readily apparent from the following detailed description of preferred embodiments of the present invention, which proceeds with reference to the accompanying drawings.

  As described above, according to the present invention, a field effect transistor having a structure capable of using the field plate effect is provided.

  The knowledge of the present invention can be easily understood by considering the following detailed description with reference to the accompanying drawings shown as examples. Subsequently, embodiments of the field effect transistor of the present invention will be described with reference to the accompanying drawings. Where possible, the same parts are denoted by the same reference numerals.

(First embodiment)
FIG. 1A is a plan view showing the field effect transistor according to the first embodiment. FIG. 1B is a cross-sectional view taken along the I-I cross section shown in FIG. The field effect transistor 11 includes a conductive gallium nitride substrate 13, a gallium nitride based semiconductor region 15, a gate electrode 17, a drain electrode 19, and a source electrode 21. The conductive gallium nitride substrate 13 has a front surface 13a and a back surface 13b, and includes a first region 13c having a first dislocation density and a second region 13d having a second dislocation density. The first region 13c extends in the Z direction from the back surface 13b toward the front surface 13a. The second region 13d is adjacent to the first region 13c. The first region 13c is located between the two second regions 13d. The second dislocation density in the second region 13d is smaller than the first dislocation density in the first region 13c. The gallium nitride based semiconductor region 15 includes a first portion 15c and a second portion 15d. The first portion 15 c is provided on the first region 13 c of the conductive gallium nitride substrate 13. The second portion 15 d is provided on the first region 13 c of the conductive gallium nitride substrate 13. The gate electrode 17 is provided on the second portion 15 d of the gallium nitride based semiconductor region 15. The drain electrode 19 is provided on the second portion 15 d of the gallium nitride based semiconductor region 15. The source electrode 21 is provided on the gallium nitride based semiconductor region 15 and is connected to the first portion 15 c of the gallium nitride based semiconductor region 15. The dislocation density of the first portion 15 c of the gallium nitride based semiconductor region 15 is larger than the dislocation density of the second portion 15 d of the gallium nitride based semiconductor region 15. The conductivity of the first portion 15 c of the gallium nitride based semiconductor region 15 is larger than the conductivity of the second portion 15 d of the gallium nitride based semiconductor region 15.

  According to the field effect transistor 11, the source electrode 21 is connected to the conductive gallium nitride substrate 13 through the first portion 15 c of the gallium nitride based semiconductor region 15. The potential of the source electrode is applied to the first portion 15 c having a large dislocation density, and the potential of the source electrode 21 is transmitted to the conductive gallium nitride substrate 13. A second portion 15d having a low dislocation density is utilized for the drain and channel.

  In the field effect transistor 11, the first region 13c of the conductive gallium nitride substrate 13 and the first portion 15c of the gallium nitride based semiconductor region 15 are provided along a predetermined plane S1. That is, the regions 13c and 15c having a high dislocation density extend in the Z-axis direction, and the first portion 15c of the gallium nitride based semiconductor region 15 is directly connected to the first region 13c of the conductive gallium nitride substrate 13. Yes. At least a part of the source electrode 21 is located on the first portion 15 c of the gallium nitride based semiconductor region 15, and thereby the conductive gallium nitride substrate via the first portion 15 c of the gallium nitride based semiconductor region 15. Thirteen first regions 13c are electrically connected.

In this embodiment, the first region 13c of the conductive gallium nitride substrate 13 extends along the Y direction that intersects the Z direction. According to the field effect transistor 11, dislocations can be collected in the first region 13c of the conductive gallium nitride substrate 13 and the dislocation density in the second region 13d can be reduced. A high-quality semiconductor crystal for the field effect transistor 11 can be formed on the second region 13d using the MOVPE method or the MBE method. For example, the second dislocation density of the second region 13 of the conductive gallium nitride substrate 13 can be about 1 × 10 ⁶ cm ⁻² or less. According to this field effect transistor 11, the crystallinity of the second portion 15d of the gallium nitride based semiconductor region 15 is improved.

  Further, in the conductive gallium nitride substrate 13 of one embodiment, the crystal axis of the first region 13c is opposite to the crystal axis of the second region 13d. For example, the first region 13c that appears on the back surface 13b of the conductive gallium nitride substrate 13 is one of the N and Ga surfaces of gallium nitride, and the second region 13d that appears on the back surface 13b is made of gallium nitride. The other of the N plane and the Ga plane.

  Subsequently, a high electron mobility transistor will be described as an example of the field effect transistor 11. The gallium nitride based semiconductor region 15 can include a channel layer 23 made of a first gallium nitride based semiconductor and an electron barrier layer 25 made of a second gallium nitride based semiconductor. The first gallium nitride based semiconductor is different from the second gallium nitride based semiconductor. On the conductive gallium nitride substrate 13, one of the channel layer 23 and the electron barrier layer 25 is provided on the other, and the channel layer 23 and the electron barrier layer 25 form a heterojunction 27.

  In this embodiment, the electron barrier layer 25 is formed on the channel layer 23. The channel layer 23 includes a first portion 23c and a second portion 25c. The first portion 23 c is provided on the first region 13 c of the conductive gallium nitride substrate 13. The second portion 23 d is provided on the second region 23 d of the conductive gallium nitride substrate 23. The electron barrier layer 25 includes a first portion 25c and a second portion 25d. The first portion 25 c is provided on the first portion 23 c of the channel layer 23. The second portion 25 d is provided on the second portion 23 d of the channel layer 23. The first region 13c is located between the two second regions 13d. Since the second dislocation density of the second region 13d is smaller than the first dislocation density of the first region 13c, the second dislocation density of the second portion 23d is the first dislocation of the first portion 23c. The second dislocation density of the second portion 25d is smaller than the first dislocation density of the first portion 25c.

  According to the field effect transistor 11, the source electrode of the heterojunction transistor is electrically connected to the conductive gallium nitride substrate 13 through the first portion 23 c of the channel layer 23 and the first portion 25 c of the electron barrier layer 25. Connected. Therefore, a heterojunction transistor capable of utilizing the field plate effect is provided.

  The band gap of the gallium nitride semiconductor of the electron barrier layer 25 is larger than the band gap of the gallium nitride semiconductor of the channel layer 23. Therefore, a two-dimensional electron gas 29 is formed along the heterojunction 27 in the channel layer 23. Is done. A two-dimensional electron gas 29 flows from the source electrode 21 toward the drain electrode 19, and the density of the two-dimensional electron gas 29 is controlled by the gate electrode 17. In the preferred embodiment, the channel layer 23 comprises an undoped semiconductor and the electron barrier layer 25 comprises an undoped semiconductor.

The field effect transistor 11 can include a protective film 31 provided on the gallium nitride based semiconductor region 15. The protective film 31 is made of an insulator such as a silicon oxide such as SiO ₂ , a silicon nitride film such as SiN, or an aluminum oxide such as Al ₂ O _{3, and is} formed on the semiconductor region 15 between the source electrode 21 and the gate electrode 17. And located on the semiconductor region 15 between the drain electrode 19 and the gate electrode 17.

  In the field effect transistor 11, the gallium nitride based semiconductor region 15 may further include one or more third regions 13e. The third region 13e extends in the Z direction and has a third dislocation density higher than that of the second region 13d. The third dislocation density is substantially equal to the first dislocation density. The gallium nitride based semiconductor region 15 includes a third portion 15 e, and the third portion 15 e is provided on the third region 13 e of the conductive gallium nitride substrate 13. The third portion 15e and the third region 13e are provided along the predetermined surface S2. That is, the regions 13e and 15e having a high dislocation density extend in the Z-axis direction, and the third portion 15e of the gallium nitride based semiconductor region 15 is directly connected to the third region 13e of the conductive gallium nitride substrate 13. Yes. A distance D1 between the predetermined surface S2 and the predetermined surface S1 is, for example, about 100 micrometers, and further high dislocation regions can be arranged at a predetermined pitch. When the gallium nitride based semiconductor region 15 includes the channel layer 23 and the electron barrier layer 25, the third portion 15 e includes the third portion 23 e of the channel layer 23 and the third portion 25 e of the electron barrier layer 25.

  The conductivity of the third portion 15 e of the gallium nitride based semiconductor region 15 is larger than the conductivity of the second portion 15 d of the gallium nitride based semiconductor region 15, and the conductivity of the first portion 15 c of the gallium nitride based semiconductor region 15. Is substantially the same as the rate. Since the third portion 15e is connected to the first portion 15c of the gallium nitride based semiconductor region 15 through the conductive gallium nitride substrate 13, the potential of the third portion 15e is the same as that of the first portion 15c. become. The gallium nitride based semiconductor region 15 includes an isolation region 33 for separating the third portion 15 e of the gallium nitride based semiconductor region 15 from the drain electrode 19. The isolation region 33 can prevent the third portion 15e of the gallium nitride based semiconductor region 15 from being electrically connected to the drain electrode 19 with a low resistance.

  When the gallium nitride based semiconductor region 15 includes the channel layer 23 and the electron barrier layer 25, the isolation region 33 is deeper than the heterojunction 27. As a result, the two-dimensional electron gas 29 is separated from each other by the isolation region 33.

  As the isolation region 33, a groove can be formed in the gallium nitride based semiconductor region 15 for electrical isolation. Alternatively, as the isolation region 33, a region having a high resistivity for electrical separation can be formed in the gallium nitride based semiconductor region 15.

  Further, in the field effect transistor 11, the gallium nitride based semiconductor region 15 can include an isolation region 35 extending along the first portion 15 c located below the source electrode 21.

  FIG. 2 is a diagram illustrating a modification of the field effect transistor according to the first embodiment. The field effect transistor 11 a of the modification can further include a source pad electrode 37 provided on the back surface 13 b of the conductive gallium nitride substrate 13. Since the source pad electrode 37 is located on the back surface 13b of the substrate 13 of the field effect transistor 11a, an area for providing the source pad electrode on the surface of the field effect transistor 11a becomes unnecessary.

  As described above, the present embodiment can employ the back surface field plate structure without requiring a complicated process. Further, since the gallium nitride substrate having the first and second regions is used, the crystallinity of the epitaxial film formed on the substrate is improved. Therefore, the breakdown voltage of the gallium nitride power device can be improved.

(Example 1)
A GaN substrate having a low dislocation region of 2 × 10 ⁵ cm ⁻² , a thickness of 350 μm, and a carrier concentration of 2 × 10 ¹⁸ cm ⁻³ is prepared. As this kind of GaN substrate, a substrate having stripe-shaped high dislocation regions (hereinafter referred to as a core region in this embodiment) at intervals of 10 μm to 1 mm is obtained. On this GaN substrate, using a metal organic chemical vapor deposition method (MOCVD method), an undoped GaN layer of 1.5 μm, and then an undoped Al _X Ga _1-X N barrier layer (for example, X = 0.25) of 30 nm. Form. This produces an epitaxial substrate for the heterostructure field effect transistor (HFET). As in the above embodiment, the gate electrode and the drain electrode are formed on the low dislocation region. A Ni / Au structure is used for the gate electrode, and a Ti / Al structure is used for the drain electrode. The gate length Lg is 1.5 μm, and the gate width Wg is 200 μm. The source electrode is formed so that a part thereof is in contact with the core region. The source electrode has the same Ti / Al structure as the drain electrode, and the source electrode is formed simultaneously with the formation of the drain electrode. The gate electrode, the drain electrode, and the pad electrode of the source electrode are provided on the surface of the transistor. In addition, the GaN layer and the Al _X Ga _1-X N barrier layer were etched by RIE for element isolation. Further, SiO ₂ is used as a protective film. An H-FET 11b schematically shown in FIG. The prototyped heterostructure field effect transistor had a maximum transconductance (gm) of 180 mS / mm and a maximum drain current of 800 mA / mm. The off breakdown voltage is a high value of 960 volts. The on-resistance is 2.3 mΩcm ² , which is a good low value for a power switching device.

  Note that a cap layer can be formed to reduce ohmic resistance. Furthermore, at least one of the gate electrode, the drain electrode, and the source electrode may have a recess structure. Even in these cases, the advantages according to the present embodiment are exhibited without change.

(Example 2)
In the same manner as in Example 1, an epitaxial substrate for an AlGaN / GaN-HFET structure was formed on a GaN substrate having a core region and a low dislocation region. The source pad electrode is formed on the back surface of the substrate as shown in the modification. The material of the source pad electrode uses a Ti / Al structure. An H-FET 11c schematically shown in FIG. As a result, the off breakdown voltage is slightly improved up to 1000 volts. Furthermore, since the source wiring resistance can be reduced, the on-resistance is as low as 1.8 mΩcm ² .

(Example 3)
A GaN substrate having a low dislocation region of 2 × 10 ⁵ cm ⁻² , a thickness of 350 μm, and a carrier concentration of 2 × 10 ¹⁸ cm ⁻³ is prepared. This type of GaN substrate has a striped core region at intervals of 10 μm to 1 mm. A 1.49 μm undoped GaN layer, a 0.01 μm undoped Ga _X In _1-X N layer (for example, X = 0.05), a 30 nm undoped Al _Y Ga ₁ film on the GaN substrate by MOCVD. _{-YN A} barrier layer (for example, Y = 0.2) is formed. This produces an epitaxial substrate for the HFET. In the same manner as in Example 1, an HFET 11d schematically shown in FIG. As a result, the off breakdown voltage is 820 volts, and the on resistance is 0.9 mΩcm ² .

  As described above, in the above embodiment, a gallium nitride field effect transistor is formed on a gallium nitride semiconductor substrate having a core region and a low dislocation region excluding the core region. A number of high-density dislocations in the core region are inherited from the gallium nitride substrate to the upper surface and reach the surface. For this reason, a core region and a low dislocation region excluding the region are also formed on the surface of the gallium nitride field effect transistor. A gate electrode and a drain electrode are provided on the surface of the low dislocation region, and a source electrode is provided in contact with the core region. Since the core region does not exist between the gate electrode, the source electrode, and the drain electrode, the operation region such as the channel layer is formed in the low dislocation region, and good transistor characteristics can be obtained. On the other hand, the source electrode is electrically connected to the gallium nitride substrate through the inherited core region. Therefore, the gallium nitride substrate can be kept at the same potential as the source electrode without adopting a complicated structure such as a source via structure, and the breakdown voltage of the transistor can be increased by the back surface field plate action. Further, since the gallium nitride substrate is used, the operation region has excellent crystallinity, and good characteristics that cannot be achieved by the prior art can be obtained. Further, when the source pad electrode is provided on the back surface of the substrate, the on-resistance and the parasitic source inductance are reduced in addition to the reduction of the chip size. When the high dislocation regions are regularly arranged, the electrode formation position can be easily designed. For this reason, the power switching device can be mass-produced with a high yield.

(Second Embodiment)
FIG. 4A is a plan view showing a field effect transistor according to the second embodiment. FIG. 4B is a cross-sectional view taken along the II-II cross section shown in FIG. FIG. 5 is a cross-sectional view taken along the III-III cross section shown in FIG. The field effect transistor 11 e includes a conductive gallium nitride substrate 43, a gallium nitride based semiconductor region 45, a gate electrode 17, a drain electrode 19, and a source electrode 21. The conductive gallium nitride substrate 43 has a front surface 43a and a back surface 43b, and includes a plurality of first regions 43c having a first dislocation density and a second region 43d having a second dislocation density. The first region 13c extends in the Z direction from the back surface 43b toward the front surface 43a. Each first region 43c is surrounded by a second region 43d. The second dislocation density in the second region 43d is smaller than the first dislocation density in the first region 43c. The gallium nitride based semiconductor region 45 includes a first portion 45c and a second portion 45d. The first portion 45 c is provided on the first region 43 c of the conductive gallium nitride substrate 43. The second portion 45 d is provided on the second region 43 d of the conductive gallium nitride substrate 43. The gate electrode 17 is provided on the second portion 45 d of the gallium nitride based semiconductor region 45. The drain electrode 19 is provided on the second portion 45 d of the gallium nitride based semiconductor region 45. The source electrode 21 is provided on the gallium nitride based semiconductor region 45 and is connected to the first portion 45 c of the gallium nitride based semiconductor region 45. The dislocation density of the first portion 45 c of the gallium nitride based semiconductor region 45 is larger than the dislocation density of the second portion 45 d of the gallium nitride based semiconductor region 45. The conductivity of the first portion 45 c of the gallium nitride based semiconductor region 45 is greater than the conductivity of the second portion 45 d of the gallium nitride based semiconductor region 45.

  According to the field effect transistor 11 e, the source electrode 21 is connected to the conductive gallium nitride substrate 43 through the first portion 45 c of the gallium nitride based semiconductor region 45. The potential of the source electrode is applied to the first portion 45c having a large dislocation density, and the potential of the source electrode is transmitted to the conductive gallium nitride substrate. A second portion 45d having a low dislocation density is utilized for the drain and channel.

  In the field effect transistor 11e, the first regions 43c of the conductive gallium nitride substrate 43 and the first portions 45c of the gallium nitride based semiconductor region 45 are arranged along a predetermined plane S3. That is, the regions 43c and 45c having a high dislocation density extend in the Z-axis direction, and the first portion 45c of the gallium nitride based semiconductor region 45 is directly connected to the first region 43c of the conductive gallium nitride substrate 43. Yes. A part of the source electrode 21 is located on the first portion 45 c of the gallium nitride based semiconductor region 45, whereby the conductive gallium nitride substrate 43 is interposed via the first portion 45 c of the gallium nitride based semiconductor region 45. Electrically connected to the first region 43c.

In this embodiment, as shown in FIG. 5, the first regions 43c of the conductive gallium nitride substrate 43 are arranged in the Y direction intersecting the Z direction to form a row. According to this field effect transistor 11e, dislocations can be collected in the first region 43c of the conductive gallium nitride substrate 43, and the dislocation density in the second region 43d can be reduced. For example, the second dislocation density of the second region 43d of the conductive gallium nitride substrate 43 can be about 1 × 10 ⁶ cm ⁻² or less. According to this field effect transistor 11e, the crystallinity of the second portion 45d of the gallium nitride based semiconductor region 45 is improved.

  In the field effect transistor 11e, as shown in FIG. 4, the gallium nitride based semiconductor substrate 43 may further include one or a plurality of third regions 43e. The third region 43e extends in the Z direction and has a third dislocation density higher than that of the second region 43d. Further, the third dislocation density is substantially equal to the first dislocation density. The gallium nitride based semiconductor region 45 includes a third portion 45 e, and the third portion 45 e is provided on the third region 43 e of the conductive gallium nitride substrate 43. The third portion 45e and the third region 43e are provided along a predetermined surface S4. That is, the regions 43e and 45e having a high dislocation density extend in the Z-axis direction, and the third portion 45e of the gallium nitride based semiconductor region 45 is directly connected to the third region 43e of the conductive gallium nitride substrate 43. Yes. A distance D2 between the predetermined surface S3 and the predetermined surface S4 is, for example, about 100 micrometers, and rows of further high dislocation regions can be arranged at a predetermined pitch.

  The conductivity of the third portion 45e of the gallium nitride based semiconductor region 45 is larger than the conductivity of the second portion 45d of the gallium nitride based semiconductor region 45, and the conductivity of the first portion 45c of the gallium nitride based semiconductor region 45. About the same rate. Since the third portion 45e is connected to the first portion 45c through the conductive gallium nitride substrate 43, the third portion 45e has the same potential as the first portion 45c. The gallium nitride based semiconductor region 45 includes an isolation region 63 for separating the third portion 45 e of the gallium nitride based semiconductor region 45 from the drain electrode 19. The isolation region 63 can prevent the third portion 45 e of the gallium nitride based semiconductor region 45 from being electrically connected to the drain electrode 19.

  Subsequently, a high electron mobility transistor will be described as an example of the field effect transistor 11e. The gallium nitride based semiconductor region 45 can include a channel layer 53 made of a first gallium nitride based semiconductor and an electron barrier layer 55 made of a second gallium nitride based semiconductor. On the conductive gallium nitride substrate 43, one of the channel layer 53 and the electron barrier layer 55 is provided on the other, and the channel layer 53 and the electron barrier layer 55 form a heterojunction 57.

  In this embodiment, the electron barrier layer 55 is formed on the channel layer 53. The channel layer 53 includes a first portion 53c and a second portion 55c. The first portion 53 c is provided on the first region 43 c of the conductive gallium nitride substrate 43. The second portion 53 d is provided on the second region 53 d of the conductive gallium nitride substrate 53. The electron barrier layer 55 includes a first portion 55c and a second portion 55d. The first portion 55 c is provided on the first portion 53 c of the channel layer 23. The second portion 55 d is provided on the second portion 53 d of the channel layer 53. The first region 43c is located between the two second regions 43d. Since the second dislocation density in the second region 43d is smaller than the first dislocation density in the first region 43c, the second dislocation density in the second portion 53d is the first dislocation in the first portion 53c. The second dislocation density of the second portion 55d is smaller than the first dislocation density of the first portion 55c. When the gallium nitride based semiconductor region 45 includes the channel layer 53 and the electron barrier layer 55, the third portion 45 e includes the third portion 53 e of the channel layer 53 and the third portion 55 e of the electron barrier layer 55.

  According to the field effect transistor 11e, a heterojunction transistor capable of using the field plate effect is provided. The source electrode of the heterojunction transistor is electrically connected to the conductive gallium nitride substrate 43 through the first portion 53 c of the channel layer 53 and the first portion 55 c of the electron barrier layer 55.

  When the gallium nitride based semiconductor region 45 includes the channel layer 53 and the electron barrier layer 55, the isolation region 63 is deeper than the heterojunction 57. As a result, the two-dimensional electron gas 59 is separated into the isolation region 63.

  Further, in the field effect transistor 11e, the gallium nitride based semiconductor region 45 can include an isolation region 65 extending along the first portion 45c located under the source electrode 21.

  Similar to the field effect transistor modification 11 a, the source pad electrode can be provided on the back surface 43 b of the conductive gallium nitride substrate 43.

(Third embodiment)
FIG. 6 is a plan view showing a field effect transistor according to the third embodiment. FIG. 7 is a cross-sectional view taken along the IV-IV cross section shown in FIG. The field effect transistor 11 f includes a conductive gallium nitride substrate 13 and a gallium nitride based semiconductor region 15. On the gallium nitride based semiconductor region 15, a source electrode 21a, a gate electrode 17a, a drain electrode 19a, a gate electrode 17b, and a source electrode 21b are arranged in this order in the X direction. The gate electrodes 17 a and 17 b are provided on the second portion 15 d of the gallium nitride based semiconductor region 15. The drain electrode 19 a is provided on the second portion 15 d of the gallium nitride based semiconductor region 15. The source electrode 21 a is provided on the gallium nitride based semiconductor region 15 and is connected to the first portion 15 c of the gallium nitride based semiconductor region 15. The source electrode 21 b is provided on the gallium nitride based semiconductor region 15 and is connected to the third portion 15 e of the gallium nitride based semiconductor region 15.

  According to the field effect transistor 11f, the source electrodes 21a and 21b are connected to the conductive gallium nitride substrate 13 via the first portion 15c and the third portion 15e of the gallium nitride based semiconductor region 15, respectively. The potentials of the source electrodes 21 a and 21 b are applied to the first portion 15 c and the third portion 15 e having a large dislocation density, and the potentials of the source electrodes 21 a and 21 b are transmitted to the conductive gallium nitride substrate 13. A second portion 15d having a low dislocation density is utilized for the drain and channel. A source electrode 21a, a gate electrode 17a, a drain electrode 19a, a gate electrode 17b, and a source electrode 21b are placed between the two drain electrodes 19b.

  In the field effect transistor 11f, the gallium nitride based semiconductor region 15 can include isolation regions 35a extending along the first portions 15c and 15e located under the source electrodes 21a and 21b, respectively.

(Example 4)
A plurality of core regions (stripe shapes) of the gallium nitride substrate extend along a plane regularly arranged at intervals of 100 μm, the dislocation density of the low dislocation regions is 1 × 10 ⁵ cm ⁻² , and the thickness is 400 μm. And the carrier concentration is 4 × 10 ¹⁸ cm ⁻³ . Similar to Example 1, an HFET device was fabricated. In this case, the distance between the cores coincides with the distance between the electrodes, and a high-current HFET structure device in which the gallium nitride substrate and the electrode arrangement are combined is designed. The source electrode length Ls is 24 μm, the gate-source Lgs is 1.5 μm, the gate length Lg is 1.5 μm, the gate width is 200 μm (2 × 100 μm), and the gate-drain Lgd is 10 μm. The drain electrode length Ld is 50 μm. In this HFET, the off breakdown voltage is 900 volts, the on resistance is 2.5 mΩcm ² , and the maximum drain current is 120 amperes.

(Fourth embodiment)
FIG. 8 is a plan view showing a field effect transistor according to the fourth embodiment. FIG. 9 is a cross-sectional view taken along the VV cross section shown in FIG. The field effect transistor 11 g includes a conductive gallium nitride substrate 43 and a gallium nitride based semiconductor region 45. On the gallium nitride semiconductor region 45, a source electrode 21a, a gate electrode 17a, a drain electrode 19a, a gate electrode 17b, and a source electrode 21b are arranged in this order in the X direction. The gate electrodes 17 a and 17 b are provided on the second portion 45 d of the gallium nitride based semiconductor region 45. The drain electrode 19 a is provided on the second portion 45 d of the gallium nitride based semiconductor region 45. The source electrode 21 a is provided on the gallium nitride based semiconductor region 45 and is connected to the first portion 45 c of the gallium nitride based semiconductor region 45. The source electrode 21 b is provided on the gallium nitride based semiconductor region 45 and is connected to the third portion 45 e of the gallium nitride based semiconductor region 45.

  According to the field effect transistor 11g, the source electrodes 21a and 21b are connected to the conductive gallium nitride substrate 43 through the first portion 45c and the third portion 45e of the gallium nitride based semiconductor region 45, respectively. The potentials of the source electrodes 21 a and 21 b are applied to the first portion 45 c and the third portion 45 e having a large dislocation density, and the potentials of the source electrodes 21 a and 21 b are transmitted to the conductive gallium nitride substrate 43. A second portion 45d having a low dislocation density is utilized for the drain and channel. A source electrode 21a, a gate electrode 17a, a drain electrode 19a, a gate electrode 17b, and a source electrode 21b are placed between the two drain electrodes 19b.

  In the field effect transistor 11g, the gallium nitride based semiconductor region 45 can include isolation regions 65a extending along the first portions 15c and 15e located under the source electrodes 21a and 21b, respectively.

(Example 5)
The core region (island shape) of the gallium nitride substrate extends along a plane regularly arranged at intervals of 100 μm. The dislocation density in the low dislocation region of the gallium nitride substrate is 1 × 10 ⁵ cm ⁻² , the thickness is 400 μm, and the carrier concentration is 4 × 10 ¹⁸ cm ⁻³ . A device having an HFET structure was fabricated in the same manner as in Example 4. In this case, the distance between the cores coincides with the distance between the electrodes, and a device for high current combining the gallium nitride substrate and the electrode arrangement is designed. When the total gate width is 200 μm, the off breakdown voltage is 940 volts, the on resistance is 2.0 mΩcm ² , and the maximum drain current is 140 amperes.

  Since the lattice constant and thermal expansion coefficient of the gallium nitride semiconductor constituting the gallium nitride power device are different from those of SiC and Si, the nitride formed as a substrate made of a different material from the gallium nitride semiconductor. Gallium-based epitaxial crystals do not show good crystallinity. Since the high breakdown voltage of a device depends on the quality of crystallinity, when using a gallium nitride substrate, the field effect of the characteristics superior to the device characteristics achieved using the SiC substrate and the Si substrate used in the prior art A transistor is provided.

In the field effect transistors according to some of the embodiments described above, at least the first (Al _X In _1-X ) _Y Ga _1-Y N layer (0 ≦ X <1, 0 ≦ Y ≦ 1) is used as the channel layer. )including. In addition, the field effect transistor has a second (Al _U In _1-U ) _V having a larger band gap energy than the first (Al _X In _1-X ) _Y Ga _1-Y N layer as an electron barrier layer. Ga _1-V N (0 ≦ U ≦ 1, 0 ≦ V <1) may be included. Therefore, a good heterostructure field effect transistor (HFET) is provided by using a two-dimensional electron gas. As described above, according to the embodiment of the present invention, a gallium nitride power switching device having a high breakdown voltage and a low on-resistance can be provided.

  While the principles of the invention have been illustrated and described in the preferred embodiments, it will be appreciated by those skilled in the art that the invention can be modified in arrangement and detail without departing from such principles. We therefore claim all modifications and changes that come within the scope and spirit of the following claims.

FIG. 1A is a plan view showing the field effect transistor according to the first embodiment. FIG. 1B is a cross-sectional view taken along the I-I cross section shown in FIG. FIG. 2 is a diagram illustrating a modification of the field effect transistor according to the first embodiment. FIG. 3A, FIG. 3B, and FIG. 3C are drawings showing examples according to the first embodiment. FIG. 4A is a plan view showing a field effect transistor according to the second embodiment. FIG. 4B is a cross-sectional view taken along the II-II cross section shown in FIG. FIG. 5 is a cross-sectional view taken along the III-III cross section shown in FIG. FIG. 6 is a plan view showing a field effect transistor according to the third embodiment. FIG. 7 is a cross-sectional view taken along the IV-IV cross section shown in FIG. FIG. 8 is a plan view showing a field effect transistor according to the fourth embodiment. FIG. 9 is a cross-sectional view taken along the VV cross section shown in FIG.

Explanation of symbols

11, 11 a, 11 b, 11 c, 11 d, 11 e, 11 f, 11 g ... field effect transistor, 13 ... conductive gallium nitride substrate, 13a ... conductive gallium nitride substrate surface, 13b ... back surface of conductive gallium nitride substrate, 13c ... 1 region (high dislocation region), 13d ... second region (low dislocation region), 13e ... third region (high dislocation region), 15 ... gallium nitride based semiconductor region, 15c ... first portion, 15d ... Second part, 15e ... third part, 17 ... gate electrode, 17a ... gate electrode, 17b ... gate electrode, 19 ... drain electrode, 19a ... drain electrode, 19b ... drain electrode, 21 ... source electrode, 21a ... source Electrode, 21b ... Source electrode, 23 ... Channel layer, 23c ... First part, 23d ... Second part, 23e ... Third part, 25 ... Electron barrier layer, 25c ... 1 part, 25d ... 2nd part, 25e ... 3rd part, 27 ... heterojunction, 29 ... two-dimensional electron gas, 31 ... protective film, 33, 35, 35a ... isolation region, 37 ... source pad electrode 43 ... conductive gallium nitride substrate, 43a ... conductive gallium nitride substrate surface, 43b ... conductive gallium nitride substrate back surface, 43c ... first region, 43d ... second region, 43e ... third region, 45 ... Gallium nitride semiconductor region, 45c ... first portion, 45d ... second portion, 45e ... third portion, 53 ... channel layer, 55 ... electron barrier layer, 57 ... heterojunction, 59 ... two-dimensional electron gas, 63, 65, 65a ... isolation region,

Claims (7)

A first region having a front surface and a back surface, extending in a first direction from the back surface toward the front surface and having a first dislocation density, and a second dislocation density smaller than the first dislocation density A conductive gallium nitride substrate including a second region having;
A gallium nitride based semiconductor including a first portion provided on the first region of the conductive gallium nitride substrate and a second portion provided on the second region of the conductive gallium nitride substrate. Area,
A gate electrode provided on the second portion of the gallium nitride based semiconductor region;
A drain electrode provided on the second portion of the gallium nitride based semiconductor region;
A source electrode provided on the gallium nitride based semiconductor region and connected to the first portion of the gallium nitride based semiconductor region;
The dislocation density of the first portion of the gallium nitride based semiconductor region is greater than the dislocation density of the second portion of the gallium nitride based semiconductor region,
The field effect transistor according to claim 1, wherein the conductivity of the first portion of the gallium nitride based semiconductor region is greater than the conductivity of the second portion of the gallium nitride based semiconductor region.   The field effect transistor according to claim 1, further comprising a source pad electrode provided on the back surface of the conductive gallium nitride substrate. 3. The field effect according to claim 1, wherein the second dislocation density in the second region of the conductive gallium nitride substrate is 1 × 10 ⁶ cm ⁻² or less. Transistor. The gallium nitride based semiconductor region is
A first portion provided on the first region of the conductive gallium nitride substrate; and a second portion provided on the second region of the conductive gallium nitride substrate. A channel layer made of a gallium nitride based semiconductor,
A first portion provided on the first region of the conductive gallium nitride substrate and a second portion provided on the second region of the conductive gallium nitride substrate; And an electron barrier layer made of a gallium nitride based semiconductor,
One of the electron barrier layer and the channel layer is provided on the other,
The field effect transistor according to any one of claims 1 to 3, wherein the channel layer and the electron barrier layer form a heterojunction. The conductive gallium nitride substrate further includes a third region having a third dislocation density greater than the second dislocation density and extending in the first direction;
The gallium nitride based semiconductor region includes a third portion provided on the third region of the conductive gallium nitride substrate,
The conductivity of the third portion of the gallium nitride based semiconductor region is greater than the conductivity of the second portion of the gallium nitride based semiconductor region,
The gallium nitride based semiconductor region includes an isolation region for separating the third portion of the gallium nitride based semiconductor region from the drain electrode,
The field effect transistor according to claim 4, wherein a depth of the isolation region is deeper than a position of the heterojunction.   The said 1st area | region of the said electroconductive gallium nitride substrate is extended along the 2nd direction which cross | intersects the said 1st direction, The Claim 1 characterized by the above-mentioned. Field effect transistor. The conductive gallium nitride substrate further includes a plurality of third regions having a third dislocation density greater than the second dislocation density and extending in the first direction;
The gallium nitride based semiconductor region includes a third portion provided on the third region of the conductive gallium nitride substrate,
The conductivity of the third portion of the gallium nitride based semiconductor region is greater than the conductivity of the second portion of the gallium nitride based semiconductor region,
The first region and the third region of the conductive gallium nitride substrate are arranged in an array in second and third directions intersecting the first direction. The field effect transistor according to claim 1.

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