JP2006339416A - Method for manufacturing semiconductor element, semiconductor element, semiconductor device, and display unit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor element capable of decreasing a characteristic defect occurring on the basis of an nonuniformity of an impurity (dopant) concentration in an impurity included region of the semiconductor layer; and to provide the semiconductor element, a semiconductor device, and a display unit. <P>SOLUTION: The method for manufacturing the semiconductor element having a structure in which the semiconductor layer with the impurity included region formed, a gate insulating film, and a gate electrode are laminated comprises the steps of forming the semiconductor layer, the gate insulating film, a lower layer metal film, and an upper layer metal film; etching the upper layer metal film to form the upper layer gate electrode; and forming the impurity included region by implanting the impurity to the semiconductor layer through the lower layer metal film and the gate insulating film. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

The present invention relates to a method for manufacturing a semiconductor element, a semiconductor element, a semiconductor device, and a display device. More specifically, the present invention relates to a method for manufacturing a semiconductor element such as a positive staggered thin film transistor, a semiconductor element manufactured using the manufacturing method, a semiconductor device including the semiconductor element, and a display device.

A semiconductor element is an active element using electrical characteristics of a semiconductor. Among them, a thin film transistor (TFT) which is a three-terminal active element is used as a switching element in a display device or the like. In recent years, by using a polysilicon TFT (p-Si TFT) having a polysilicon (p-Si) layer as a semiconductor layer, a high performance TFT and a built-in drive circuit have been achieved by adopting a self-aligned structure. ing. Furthermore, in order to improve the performance of the p-Si TFT, a semiconductor device including a tungsten (W) layer as a gate electrode is disclosed from the viewpoint of low specific resistance and high heat resistance (see, for example, Patent Document 1). . Furthermore, a semiconductor device including a stacked body in which a tungsten layer and a tantalum nitride layer are stacked in this order toward the semiconductor layer as the gate electrode is also disclosed from the viewpoint of improving the adhesion between the gate electrode and the semiconductor layer. (For example, refer to Patent Document 2).

Below, the manufacturing method of the positive stagger type p-Si TFT according to Patent Document 2 will be described.
First, as shown in FIG. 9A, a base coat film 6, a p-Si layer 5, a gate insulating film 4, a lower metal film 3, an upper metal film 2 and a photoresist layer 1 are formed in this order on a glass substrate 7. To do. Next, as shown in FIG. 9B, the upper metal film 2 is etched using the photoresist layer 1 as a mask to form an upper gate electrode 12 (first gate etching step). At this time, the upper gate electrode 12 is formed in a forward tapered shape in order to improve the step coverage of the interlayer insulating film formed in a later process. Next, as shown in FIG. 9C, the lower layer metal film 3 is etched using the upper layer gate electrode 12 as a mask to form the lower layer gate electrode 13, thereby completing the two-layered gate electrode 10 (first). 2 gate etching step).

Next, as shown in FIG. 9D, after the photoresist layer 1 is peeled off, impurities are implanted into the p-Si layer 5 through the gate insulating film 4 using the gate electrode 10 as a mask, and the impurity-containing region 5a. Is formed (through doping process). Finally, as shown in FIG. 9E, by forming the interlayer insulating film 9, the source electrode 8a, and the drain electrode 8b, a positive staggered p-Si TFT is completed.

However, according to the manufacturing method described in Patent Document 2, since the selection ratio of the lower metal film 3 to the gate insulating film 4 is small and the film thickness variation occurs in the gate insulating film 4 after the second gate etching step, Even if an impurity (dopant) is implanted into the p-Si layer 5 through the gate insulating film 4 in the through doping process, the dopant is not uniformly distributed in a predetermined region of the p-Si layer 5, Characteristic defects such as higher resistance, lower reliability, poor driver operation, and increased contact resistance have occurred.
JP 2001-35808 A JP 2003-209260 A

The present invention has been made in view of the above-described situation, and a method for manufacturing a semiconductor element capable of reducing characteristic defects caused by non-uniformity of impurity (dopant) concentration in an impurity-containing region of a semiconductor layer. An object of the present invention is to provide a semiconductor element, a semiconductor device, and a display device.

The present inventor has made various studies on a method for manufacturing a semiconductor element having a structure in which a semiconductor layer in which an impurity-containing region is formed, a gate insulating film, and a gate electrode are stacked. Attention was paid to the selectivity of the metal film to be formed. Since the selection ratio of the gate metal film to the gate insulating film is small, it has been confirmed that the conventional manufacturing method is difficult to uniformly inject impurities through the gate insulating film.

Therefore, the present inventor has further studied, and the structure of the gate electrode is a laminated structure including the lower gate electrode and the upper gate electrode, and the upper layer with respect to the lower metal film (metal film for forming the lower gate electrode). Attention was paid to the selectivity of the metal film (metal film for forming the upper gate electrode). The selectivity of the upper metal film (for example, tungsten) with respect to the lower metal film (for example, tantalum nitride) is more easily increased than the selection ratio of the gate metal film to the gate insulating film by appropriately setting the etching conditions. I found that I could do it.

The gate insulating film has a thickness distribution by including a step of forming a semiconductor layer, a gate insulating film, a lower metal film, and an upper metal film, and a step of etching the upper metal film to form an upper gate electrode. No influence is exerted on the lower metal film because the influence on the film thickness distribution is smaller than the influence on the gate insulating film in the conventional manufacturing method. Therefore, the lower metal film and the gate are not formed in the semiconductor layer formation region except the upper gate electrode formation region. It has been found that the total thickness of the insulating film can be made uniform. As a result, the semiconductor layer can be uniformly doped in-plane by further including a step of injecting impurities into the semiconductor layer through the lower metal film and the gate insulating film to form an impurity-containing region. And found that it is possible to reduce characteristic defects caused by the non-uniformity of the impurity (dopant) concentration in the impurity-containing region of the semiconductor layer, and that the above problem can be solved brilliantly, The present invention has been achieved.

That is, the present invention is a method for manufacturing a semiconductor element having a structure in which a semiconductor layer having an impurity-containing region formed, a gate insulating film, and a gate electrode are stacked, and the manufacturing method includes a semiconductor layer, a gate insulating film, A step of forming a lower layer metal film and an upper layer metal film (stacked body forming step), a step of etching the upper layer metal film to form an upper layer gate electrode (upper layer gate electrode forming step), a lower layer metal film and a gate insulating film; And a step of implanting impurities into the semiconductor layer to form an impurity-containing region (impurity-containing region forming step). In the semiconductor element, the gate electrode includes a lower layer gate electrode and an upper layer gate electrode, and the present invention is a method for manufacturing such a semiconductor element. Note that the impurity is a material doped in the intrinsic semiconductor in order to reduce the resistance of the intrinsic semiconductor. The impurity-containing region is a region where a part of the base element of the intrinsic semiconductor is replaced with the impurity element by doping the intrinsic semiconductor with the impurity.

According to the method for manufacturing a semiconductor element of the present invention, the lower layer metal film and the upper layer metal film for forming the gate electrode on the gate insulating film formed so as to cover the semiconductor layer by performing the laminated body forming step. Can be formed. Next, by performing the above-mentioned upper layer gate electrode formation step, the upper layer gate electrode constituting the upper part of the gate electrode can be formed by etching the upper layer metal film. At this time, the gate insulating film is not affected by the film thickness distribution, and the lower metal film has a smaller influence on the film thickness distribution than the influence of the gate insulating film in the conventional manufacturing method. The total film thickness of the lower metal film and the gate insulating film can be made uniform in the semiconductor layer forming region excluding the semiconductor layer formation region. As a result, by further including the impurity-containing region forming step, the semiconductor layer can be uniformly doped with impurities in the plane through the lower metal film and the gate insulating film. Therefore, according to the method for manufacturing a semiconductor element of the present invention, it is possible to reduce the characteristic failure caused by the nonuniformity of the impurity (dopant) concentration in the impurity-containing region, and to improve the yield.

The semiconductor device manufacturing method of the present invention does not include other steps as long as it includes the stacked body forming step, the upper gate electrode forming step, and the impurity-containing region forming step as essential steps. There is no particular limitation. Therefore, for example, a photoresist layer functioning as a mask when the upper metal film is etched in the upper gate electrode forming process between the stacked body forming process and the upper gate electrode forming process is used as the upper metal film. A form including the step of forming the semiconductor element is also included in the method for manufacturing a semiconductor element of the present invention.

In addition, by further reducing the etching of the lower layer metal film in the upper layer gate electrode formation step, the uniformity of the total film thickness of the lower layer metal film and the gate insulating film after the upper layer gate electrode formation step is improved. From the viewpoint of more uniformly doping impurities in the impurity-containing region forming step, the upper gate electrode forming step is performed under the condition that the selection ratio of the upper metal film to the lower metal film is larger than the selection ratio of the lower metal film to the gate insulating film. Preferably, the selection ratio of the upper metal film to the lower metal film is more preferably 4 or more. From the same viewpoint, the thickness of the lower metal film is preferably 10 nm or more and 40 nm or less, and the thickness of the gate insulating film is preferably 100 nm or less. Furthermore, the film thickness of the gate insulating film is preferably 30 nm or more so as not to expose the semiconductor layer in the step of etching the lower metal film to form the lower gate electrode, thereby improving the performance of the semiconductor element. Therefore, it is more preferably 70 nm or less. From the viewpoint of preventing channeling when doping impurities, the upper metal film preferably has a thickness of 340 nm to 500 nm.

In addition, the more preferable minimum of the film thickness of the said lower layer metal film is 20 nm, and a more preferable upper limit is 30 nm. A more preferable lower limit of the thickness of the gate insulating film is 50 nm. Furthermore, the more preferable lower limit of the film thickness of the upper metal film is 360 nm, and the more preferable upper limit is 400 nm.

Moreover, as a form of the said lower metal film and an upper metal film, although the form which consists of multiple layers is mentioned about each, the form which consists of a single layer is preferable from a viewpoint on manufacture. In addition, from the viewpoint of suppressing plastic deformation such as hillocks in a plurality of thermal processes and ease of wiring formation by dry etching, the metal constituting the lower gate electrode and the upper gate electrode has a melting point of 2000 ° C. or higher. A refractory metal is preferred. Furthermore, from the viewpoint of effectively obtaining the effects of the present invention, the upper gate electrode formation step is preferably performed using an etching gas. The impurity-containing region forming step is preferably performed using the upper gate electrode as a mask.

As a preferred embodiment of the method for producing a semiconductor element of the present invention, (1) the lower metal film contains tantalum nitride or tantalum, the upper metal film contains a metal compound containing a refractory metal as a main component, and The etching gas is a form containing sulfur hexafluoride gas or carbon tetrafluoride gas, oxygen gas, and chlorine gas. (2) In the form of (1), the etching gas is a flow rate of sulfur hexafluoride gas. (3) In the mode (1) or (2), the etching gas has an oxygen gas flow rate of 5 sccm or more and 200 sccm or less. (4) The above (1) ) To (3), the etching gas has a flow rate ratio of sulfur hexafluoride gas to oxygen gas of 1.0 or more and 3.0 or less, ) In any of the above (1) to (4), the etching gas, the flow rate of the chlorine gas is more than 5 sccm, include form is 200sccm less. In addition, in this specification, sccm represents the unit of the gas flow rate per minute in 1.013 * 10 < ⁵ > Pa and 0 degreeC, and is 1sccm = 10 < ^-6 > m < ³ > / min.

According to the above aspect (1), the selectivity of the upper metal film to the lower metal film can be further increased in the upper gate electrode forming step, and the lower metal film and the gate can be formed before the impurity-containing region forming step. Since the uniformity of the total film thickness of the insulating film can be further improved, the effects of the present invention can be obtained more effectively. The refractory metal is preferably a metal having a melting point of 2000 ° C. or higher, and examples thereof include tungsten and molybdenum. Moreover, it is preferable that the said metal compound contains a refractory metal 50 mass% or more as a main component.

In the form (2), the flow rate of the sulfur hexafluoride gas is preferably 10 sccm or more in order to obtain a sufficient etching rate in the upper gate electrode formation step, and the lower layer in the upper gate electrode formation step. In order to obtain a sufficient selection ratio of the upper metal film to the metal film, it is preferably 500 sccm or less. A more preferable lower limit of the flow rate of sulfur hexafluoride gas is 100 sccm, and a more preferable upper limit is 250 sccm. A more preferable lower limit of the flow rate of the sulfur hexafluoride gas is 150 sccm, and a more preferable upper limit is 200 sccm.

In the form (3), the flow rate of oxygen gas is preferably 5 sccm or more in order to obtain a sufficient selectivity of the upper metal film to the lower metal film in the upper gate electrode formation step. Further, if it exceeds 200 sccm, a large amount of reactive products may be generated in the upper gate electrode formation step, and therefore the flow rate of oxygen gas is preferably 200 sccm or less. A more preferable lower limit of the flow rate of oxygen gas is 50 sccm, and a more preferable upper limit is 100 sccm. Further, a more preferable lower limit of the flow rate of the oxygen gas is 60 sccm, and a more preferable upper limit is 80 sccm.

About the form of said (4), when the flow ratio of sulfur hexafluoride gas with respect to oxygen gas is less than 1.0, there is a possibility that many reactive products may be generated. There is a possibility that the selective ratio of the upper metal film to the film cannot be obtained sufficiently. A more preferable lower limit of the flow ratio of sulfur hexafluoride gas to oxygen gas is 1.5, and a more preferable upper limit is 2.0.

In the form (5), the flow rate of the chlorine gas is preferably 5 sccm or more in order to sufficiently obtain the film thickness uniformity of the lower layer metal film after the upper layer gate electrode formation step. In order to obtain a sufficient selection ratio of the upper metal film to the lower metal film in the forming step, it is preferably 200 sccm or less. A more preferable lower limit of the chlorine gas flow rate is 20 sccm, and a more preferable upper limit is 100 sccm. Further, the more preferable lower limit of the flow rate of chlorine gas is 30 sccm, and the more preferable upper limit is 70 sccm.

The upper gate electrode formation step is preferably performed using an inductively coupled plasma (ICP) etching apparatus. If the ICP etching apparatus is used, the plasma can be easily controlled, so that the effects of the present invention can be obtained more easily. In the ICP etching apparatus, the quartz plate constituting the upper part of the chamber has an antenna coil disposed thereon, and is connected to an RF (Radio frequency) power source via a match box. The lower electrode for disposing the substrate to be etched and the substrate to be etched is connected to another RF power source via a match box. Therefore, by independently adjusting the RF power density (coil power density) applied to the antenna coil and the RF power density (bias power) applied to the lower electrode, the plasma density and the self-bias voltage are independently controlled. Is possible. Further, the frequency of the applied RF power density can be varied depending on the material of the object to be etched.

Preferred forms of the ICP etching apparatus, (A) the coil power density 0.50 W / cm ² or more, 2.00W / cm ² or less is the form, (B) a bias power density of 0.05 W / cm ² or more , A form that is 0.20 W / cm ² or less, (C) a form that the atmospheric pressure in the chamber is 0.65 Pa or more and 4.0 Pa or less, (D) a form that combines (A) and (B) above, (E) A combination of the above (A) and (C), (F) a combination of (B) and (C), and (G) a combination of (A) to (C). A form is mentioned.

In the form (A), the coil power density is preferably 0.50 W / cm ² or more in order to suppress the generation of reactive products in the upper gate electrode formation step. In order to obtain a sufficient selection ratio of the upper metal film to the lower metal film in the gate electrode formation step, it is preferably 2.00 W / cm ² or less. A more preferable lower limit of the coil power density is 0.80 W / cm ² , and a more preferable upper limit is 1.95 W / cm ² .

In the form (B), the bias power density is preferably 0.05 W / cm ² or more in order to suppress the generation of reactive products in the upper gate electrode formation step. In order to obtain a sufficient selection ratio of the upper metal film to the lower metal film in the gate electrode formation step, it is preferably 0.20 W / cm ² or less. A more preferable lower limit of the bias power density is 0.06 W / cm ² , and a more preferable upper limit is 0.16 W / cm ² .

In the form (C), the atmospheric pressure in the chamber is preferably 4.0 Pa or less in order to obtain a sufficient selection ratio of the upper metal film to the lower metal film in the upper gate electrode formation step. In order to prevent an undercut of the upper gate electrode in the upper gate electrode formation step, it is more preferably 3.0 Pa or less. Moreover, in order to sufficiently obtain the film thickness uniformity of the upper gate electrode after the upper gate electrode forming step, it is preferably 0.65 Pa or more. A more preferable lower limit of the atmospheric pressure in the chamber is 0.8 Pa, and a more preferable upper limit is 2.0 Pa. Further, a more preferable lower limit of the atmospheric pressure in the chamber is 0.9 Pa, and a more preferable upper limit is 1.9 Pa.
The same applies to the forms (D) to (G). In the above-described forms (A) to (G), the temperature of the lower electrode constituting the ICP etching apparatus is preferably 20 ° C. or higher and 40 ° C. or lower. The temperature is preferably 80 ° C. or higher from the viewpoint of suppressing product adhesion.

The method for manufacturing a semiconductor element further includes a step of etching a lower metal film to form a lower gate electrode, and the lower gate electrode forming step is preferably performed using the upper gate electrode as a mask. Thereby, the line width shift amount of the lower layer gate electrode can be reduced in the lower layer gate electrode formation step, so that variations in element characteristics can be reduced. In addition, since a photolithography process is not used in the lower layer gate electrode formation step, the manufacturing cost can be reduced.

The method for manufacturing a semiconductor device of the present invention includes (a) leaving the lower metal film in the upper gate electrode forming step, (b) the selectivity of the upper metal film to the lower metal film, or the gate metal to the gate insulating film. (C) When etching the gate metal film, the flow ratio of sulfur hexafluoride gas to oxygen gas is 1.0 or more and 3.0 or more. Use of the following etching gas has technical significance with respect to the prior art in the points (a) to (c). Therefore, the present invention only needs to have any one of the characteristics (a) to (c). That is, in the above-described present invention, the above-mentioned point (a) is indispensable, but a method for manufacturing a semiconductor element in which only the above-mentioned point (b) or (c) is essential is also one aspect of the present invention. is there. By combining these points (a) to (c), a preferable form can be obtained. Further, the above forms (a) to (c) can be made more preferable by combining with the form using the ICP etching apparatus.

The present invention is also a semiconductor device manufactured using the above-described method for manufacturing a semiconductor device. According to the semiconductor element of the present invention, it is possible to reduce the characteristic failure caused by the non-uniformity of the dopant concentration. A preferable form of the semiconductor element includes a form that is a thin film transistor, and a more preferable form is, for example, a first impurity containing region and a second impurity containing region containing the same dopant at the same or substantially the same concentration. The semiconductor layer, the gate insulating film, the lower gate electrode, and the upper gate electrode formed in this order are stacked in this order, the first impurity-containing region is connected to the source electrode, and the second impurity-containing region is connected to the drain electrode From the viewpoint of improving the line width controllability of the lower layer gate electrode and the upper layer gate electrode and reducing in-plane variation of semiconductor element characteristics, the lower layer gate electrode and the upper layer gate electrode are more preferable. The form which is not a taper shape is mentioned.

The present invention is also a semiconductor device including the semiconductor element. According to the semiconductor device of the present invention, it is possible to reduce the defective characteristics of the semiconductor element and further the in-plane variation in the characteristics of the semiconductor element, so that the yield of the semiconductor device can be improved. As a preferable form of the semiconductor device, for example, a form in which a plurality of the semiconductor elements are connected, a form in which a plurality of the semiconductor elements form a circuit via wiring, and the like can be given. Note that the area of the semiconductor device can be easily increased by performing the upper gate electrode formation step using an ICP etching apparatus.

The present invention is also a display device including the semiconductor element. According to the display device of the present invention, it is possible to reduce the defective characteristics of the semiconductor elements and further the in-plane variation in the characteristics of the semiconductor elements, so that the yield of the display device can be improved. A preferable embodiment of the display device includes a liquid crystal display device, and a more preferable embodiment of the display device includes a gate wiring, a source wiring, the semiconductor element, and a pixel electrode. The semiconductor layer, the gate insulating film, the lower gate electrode, and the upper gate electrode in which the first impurity-containing region and the second impurity-containing region containing the same dopant at the same or substantially the same concentration are formed are stacked in this order. The first impurity-containing region is connected to the source electrode, and the second impurity-containing region is connected to the drain electrode. The gate electrode is connected to the gate wiring, and An active matrix substrate having a structure in which a source electrode is connected to the source wiring and the drain electrode is connected to the pixel electrode Comprise constituted form can be mentioned. Note that the area of the display device can be increased easily by performing the upper gate electrode formation step using an ICP etching apparatus.

According to the method for manufacturing a semiconductor element of the present invention, the steps of forming a semiconductor layer, a gate insulating film, a lower layer metal film, and an upper layer metal film, and a step of etching the upper layer metal film to form an upper layer gate electrode are performed. As a result, the total film thickness of the lower metal film and the gate insulating film after the upper gate electrode forming step can be made uniform in-plane, and further, impurities can be introduced into the semiconductor layer via the lower metal film and the gate insulating film. By performing the step of implanting and forming the impurity-containing region, the semiconductor layer can be uniformly doped with impurities in the plane, and therefore, it is generated due to the non-uniformity of the dopant concentration in the impurity-containing region. Characteristic defects can be reduced.

The present invention will be described in more detail below with reference to examples, but the present invention is not limited to these examples.

[Example 1]
FIG. 1 is a schematic cross-sectional view showing a manufacturing process flow of a positive staggered p-Si TFT (semiconductor element) according to Example 1 of the invention.
First, as shown in FIG. 1A, on a glass substrate 7, a base coat film 6, a polysilicon (p-Si) layer (semiconductor layer) 5, a silicon oxide (SiO ₂ ) film (gate insulating film) 4, A tantalum nitride (TaN) film (lower metal film) 3, a tungsten (W) film (upper metal film) 2, and a photoresist layer 1 were formed in this order (stacked body forming step).

In addition, although the precision glass for liquid crystals was used as a material of the glass substrate 7, it is not limited to this. The base coat film 6 employs a two-layer structure in which the lower layer is made of silicon nitride (SiN _x ) and the upper layer is made of silicon oxide, but is not limited to this. For example, the lower layer is made of silicon oxynitride (SiNO), and the upper layer A two-layer structure made of silicon oxide can also be used. The material of the semiconductor layer 5 is not limited to polysilicon, and for example, continuous grain boundary crystal (CG) silicon can be used. In this embodiment, the thickness of the semiconductor layer 5 is 50 nm, but the present invention is not limited to this. The material of the gate insulating film 4 is not limited to silicon oxide. In this embodiment, the thickness of the gate insulating film 4 is set to 70 nm. However, the present invention is not limited to this. According to this embodiment, it is possible to improve the performance of the p-Si TFT by making the thickness of the gate insulating film 4 smaller than, for example, 70 nm. The material of the lower metal film 3 is not limited to tantalum nitride. In this embodiment, the thickness of the lower metal film 3 is set to 30 nm, but is not particularly limited as long as the effects of the present invention can be obtained. The material of the upper metal film 2 is not limited to tungsten. In this embodiment, the upper metal film 2 has a thickness of 360 nm, but is not particularly limited as long as the effects of the present invention can be obtained. In this embodiment, the thickness of the photoresist layer 1 is 1.4 μm, but the present invention is not limited to this.

Next, as shown in FIG. 1B, the tungsten film 2 was etched using the inductively coupled plasma (ICP) etching apparatus with the photoresist layer 1 as a mask (upper gate electrode forming step). As an etching gas, a gas composed of sulfur hexafluoride (SF ₆ ) gas, oxygen (O ₂ ) gas and chlorine (Cl ₂ ) gas is used, and the flow rates of SF ₆ gas, O ₂ gas and Cl ₂ gas are respectively 100 sccm, 80 sccm, and 40 sccm. For the ICP etching apparatus, the coil power density is 1.95 W / cm ² , the bias power density is 0.15 W / cm ² , the atmospheric pressure in the chamber is 1.3 Pa, and the lower electrode constituting the ICP etching apparatus The temperature was 20 ° C. Thereby, as shown in the scanning electron microscope (SEM) photograph of FIG. 2, the upper gate electrode 12 made of tungsten can be formed, and the film thickness uniformity of the tantalum nitride film 3 is ensured at 28.7%. We were able to.

Next, as shown in FIG. 1C, after the photoresist layer 1 is peeled off, phosphorus (P) is formed on the polysilicon layer 5 through the tantalum nitride film 3 and the silicon oxide film 4 using the upper gate electrode 12 as a mask. Was implanted to form an n-type polysilicon region (impurity-containing region) 5a (impurity-containing region forming step). In this embodiment, the N ion implantation method is used as a doping method. However, the present invention is not limited to this. For example, the Loff doping method, the plasma doping (PD) method, the ND doping method, or the like is used. May be performed. Further, phosphorus (P) is implanted as an impurity at a dose of 10 ¹⁵ / cm ³ , but the present invention is not limited to this.

Next, as shown in FIG. 1D, the lower gate electrode 13 was formed by etching the tantalum nitride film 3 using the upper gate electrode 12 as a mask using an ICP etching apparatus (lower gate electrode forming step). . At this time, no resist shift occurred, so that the line width shift of the lower gate electrode 13 could be reduced. Further, as long as the polysilicon layer 5 is not exposed, the upper portion of the silicon oxide film 4 may be etched, and the unnecessary tantalum nitride film 3 can be sufficiently removed. Thereby, the gate electrode 10 having a two-layer structure was completed.
Finally, as shown in FIG. 1E, an interlayer insulating film 9, a source electrode 8a, and a drain electrode 8b are formed to complete a positive staggered p-Si TFT.

[Experimental Example 1]
In this experimental example, (i) a flow rate of sulfur hexafluoride (SF ₆ ) gas, (ii) a flow rate of oxygen (O ₂ ) gas, (iii) a flow rate of chlorine (Cl ₂ ) gas, (iv) coil power Density, (v) bias power density, and (vi) chamber pressure, (a) etch rate of tungsten (W) film, tantalum nitride (TaN) film and silicon oxide (SiO ₂ ) film, (b) The relationship between etching uniformity and (c) selectivity was examined. The results are shown in FIGS.
Note that a tungsten film having a thickness of 32 × 40 cm and a thickness of 400 nm is used, a tantalum nitride film having a thickness of 32 × 40 cm and a thickness of 200 nm is used, and a silicon oxide film is 32 × 40 cm and a thickness of 300 nm. The thing of was used. As an etching apparatus, an ICP etching apparatus manufactured by YAC Corporation was used.

(I) Flow rate of SF ₆ gas (Fig. 3)
As shown in FIG. 3A, the etching rate of the tungsten film and the tantalum nitride film tends to increase monotonically as the flow rate of SF ₆ gas increases, and the tungsten film increases more than the tantalum nitride film. The degree is large. Further, as shown in FIG. 3B, the etching uniformity of the tungsten film and the tantalum nitride film tends to monotonously decrease as the flow rate of SF ₆ gas increases. Further, as shown in FIG. 3C, the selectivity (W / TaN) tends to monotonously decrease as the flow rate of SF ₆ gas increases.

(Ii) O ₂ gas flow rate (FIG. 4)
As shown in FIG. 4A, the etching rate of the tungsten film tends to increase monotonically as the flow rate of O ₂ increases, whereas the etching rate of the tantalum nitride film tends to decrease monotonously. Further, as shown in FIG. 4B, the etching uniformity of the tungsten film tends to decrease monotonically as the flow rate of O ₂ increases, whereas the etching uniformity of the tantalum nitride film has a vertical axis. Further, when the etching uniformity is taken and the flow rate of O ₂ gas is taken on the horizontal axis, an upwardly convex parabola tends to be drawn. Furthermore, as shown in FIG. 4C, the selection ratio (W / TaN) tends to increase monotonically as the flow rate of O ₂ increases.

(Iii) Flow rate of Cl ₂ gas (FIG. 5)
As shown in FIG. 5A, the etching rate of the tungsten film tends to monotonously decrease as the Cl ₂ flow rate increases, whereas the etching rate of the tantalum nitride film does not change much. Further, as shown in FIG. 5B, the etching uniformity of the tungsten film does not change much with respect to the flow rate of Cl ₂ , whereas the etching uniformity of the tantalum nitride film shows the etching uniformity on the vertical axis. When the flow rate of Cl ₂ gas is taken on the horizontal axis, there is a tendency to draw an upwardly convex parabola. Furthermore, as shown in FIG. 5C, the selection ratio (W / TaN) tends to monotonously decrease as the flow rate of Cl ₂ increases.

(Iv) Coil power density (FIG. 6)
As shown in FIG. 6A, the etching rate of the tungsten film and the tantalum nitride film tends to increase monotonically as the coil power density increases. Further, as shown in FIG. 6B, the etching uniformity of the tungsten film tends to decrease monotonically as the coil power density increases, whereas the etching uniformity of the tantalum nitride film increases monotonously. Tend to be. Further, as shown in FIG. 6 (c), the selectivity (W / TaN) tends to draw a substantially parabola that is convex upward when the vertical axis represents the etching uniformity and the horizontal axis represents the coil power density. is there.

(V) Bias power density (FIG. 7)
As shown in FIG. 7A, the etching rate of the tungsten film and the tantalum nitride film tends to increase monotonically as the bias power density increases. Further, as shown in FIG. 7B, the etching uniformity of tungsten does not change much with respect to the bias power density, whereas the etching uniformity of the tantalum nitride film shows the etching uniformity on the vertical axis and the horizontal axis. When the bias power density is taken, there is a tendency to draw a substantially parabola convex downward. Furthermore, as shown in FIG. 7C, the selection ratio (W / TaN) tends to monotonously decrease as the bias power density increases.

(Vi) Pressure inside the chamber (FIG. 8)
As shown in FIG. 8A, the etching rate of the tungsten film tends to decrease monotonically as the atmospheric pressure in the chamber increases, whereas the etching rate of the tantalum nitride film tends to increase monotonously. Further, as shown in FIG. 8B, the etching uniformity of the tungsten film tends to draw a substantially parabola convex upward when the vertical axis represents the etching uniformity and the horizontal axis represents the pressure in the chamber. On the other hand, the etching uniformity of the tantalum nitride film tends to draw a downwardly convex substantially parabola. Furthermore, as shown in FIG. 8 (c), the selectivity (W / TaN) tends to monotonously decrease as the atmospheric pressure in the chamber increases.

(A)-(e) is a cross-sectional schematic diagram which shows the manufacturing-process flow of the positive stagger type p-SiTFT (semiconductor element) which concerns on Example 1 of this invention. It is a scanning electron microscope (SEM) photograph which shows the mode after an upper layer gate electrode formation process (Example 1). (A) is a diagram showing the relationship between the sulfur hexafluoride (SF ₆₎ gas flow rate and the etching rate, (b) is an diagram showing the relationship between the flow rate and etching uniformity of SF ₆ gas , (c) is a diagram showing the relationship between the flow rate and selectivity of the SF ₆ gas (W / TaN) (experiment example 1). (A) oxygen (O ₂₎ is a diagram showing the relationship between gas flow rate and the etching rate, (b) is a diagram showing the relationship between flow rate and etching uniformity of the O ₂ gas, (c ) Is a diagram showing the relationship between the flow rate of O ₂ gas and the selection ratio (W / TaN) (Experimental Example 1). (A) is a diagram showing the relationship between the chlorine (Cl ₂₎ gas flow rate and the etching rate, (b) is a diagram showing the relationship between flow rate and etching uniformity of the Cl ₂ gas, (c ) Is a diagram showing the relationship between the flow rate of Cl ₂ gas and the selection ratio (W / TaN) (Experimental Example 1). (A) is a figure which shows the relationship between coil power density and an etching rate, (b) is a figure which shows the relationship between coil power density and etching uniformity, (c) is a figure showing coil power density and It is a figure which shows the relationship with a selection ratio (W / TaN) (Experimental example 1). (A) is a figure which shows the relationship between bias power density and an etching rate, (b) is a figure which shows the relationship between bias power density and etching uniformity, (c) is a figure showing bias power density and It is a figure which shows the relationship with a selection ratio (W / TaN) (Experimental example 1). (A) is a figure which shows the relationship between the atmospheric pressure in a chamber, and an etching rate, (b) is a figure which shows the relationship between the atmospheric pressure in a chamber, and etching uniformity, (c) is a figure in a chamber. It is a figure which shows the relationship between the atmospheric pressure and selection ratio (W / TaN) (Experimental example 1). (A)-(e) is a cross-sectional schematic diagram which shows the manufacturing process flow of the manufacturing method of the positive stagger type p-SiTFT based on patent document 2. FIG.

Explanation of symbols

1: Photoresist layer 2: Tungsten film (upper metal film)
3: Tantalum nitride film (lower metal film)
4: Silicon oxide film (gate insulating film)
5: Polysilicon layer (semiconductor layer)
5a: n-type polysilicon region (impurity-containing region)
5b: channel region 6: base coat film 7: glass substrate 8a: source electrode 8b: drain electrode 9: interlayer insulating film 10: gate electrode 11: phosphorus (impurities)
12: Tungsten layer (upper gate electrode)
13: Tantalum nitride layer (lower gate electrode)

Claims (20)

A method of manufacturing a semiconductor device having a structure in which a semiconductor layer in which an impurity-containing region is formed, a gate insulating film, and a gate electrode are stacked,
The manufacturing method includes a step of forming a semiconductor layer, a gate insulating film, a lower metal film, and an upper metal film;
Etching the upper metal film to form an upper gate electrode;
And a step of injecting impurities into the semiconductor layer through the lower metal film and the gate insulating film to form an impurity-containing region. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the upper gate electrode forming step etches the upper metal film under a condition that the selection ratio of the upper metal film to the lower metal film is 4 or more. 3. The method of manufacturing a semiconductor element according to claim 1, wherein a film thickness of the lower metal film is 10 nm or more and 40 nm or less. The method of manufacturing a semiconductor element according to claim 1, wherein the gate insulating film has a thickness of 30 nm or more and 100 nm or less. The method for manufacturing a semiconductor device according to claim 1, wherein the upper gate electrode forming step is performed using an etching gas. The lower metal film includes tantalum nitride or tantalum,
The upper metal film includes a metal compound mainly composed of a refractory metal,
6. The method of manufacturing a semiconductor device according to claim 5, wherein the etching gas contains sulfur hexafluoride gas or carbon tetrafluoride gas, oxygen gas, and chlorine gas. The method of manufacturing a semiconductor device according to claim 6, wherein the etching gas has a flow rate of sulfur hexafluoride gas of 10 sccm or more and 500 sccm or less. 8. The method of manufacturing a semiconductor device according to claim 6, wherein the etching gas has an oxygen gas flow rate of 5 sccm or more and 200 sccm or less. 9. The method of manufacturing a semiconductor device according to claim 6, wherein the etching gas has a flow ratio of sulfur hexafluoride gas to oxygen gas of 1.0 or more and 3.0 or less. 10. The method of manufacturing a semiconductor device according to claim 6, wherein the etching gas has a chlorine gas flow rate of 5 sccm or more and 200 sccm or less. The method of manufacturing a semiconductor device according to claim 1, wherein the upper gate electrode forming step is performed using an inductively coupled plasma etching apparatus. The inductively coupled plasma etching apparatus, a coil power density 0.50 W / cm ² or more, The method as claimed in claim 11, wherein the at 2.00W / cm ² or less. The inductively coupled plasma etching apparatus, a bias power density of 0.05 W / cm ² or more, The method as claimed in claim 11 or 12, wherein the at 0.20 W / cm ² or less. The method of manufacturing a semiconductor device according to claim 11, wherein the inductively coupled plasma etching apparatus has an atmospheric pressure of 0.65 Pa or more and 4.0 Pa or less in the chamber. The method for manufacturing a semiconductor element further includes a step of etching a lower metal film to form a lower gate electrode,
15. The method of manufacturing a semiconductor device according to claim 1, wherein the lower gate electrode forming step is performed using the upper gate electrode as a mask. A semiconductor device manufactured using the method for manufacturing a semiconductor device according to claim 1. The semiconductor device according to claim 16, wherein the semiconductor device is a thin film transistor. A semiconductor device comprising the semiconductor element according to claim 16. A display device comprising the semiconductor element according to claim 16. The display device according to claim 19, wherein the display device is a liquid crystal display device.