JP2006338877A - Semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory for reducing noise by encoding data while lowering its effect on chip size and memory cycle time. <P>SOLUTION: The semiconductor memory is configured to set a register RE for data which can perform random access to the inside of chip while all the accesses from the outside of the chip are made through the register for data, and to encode the data when writing the data in parallel into the memory array MCA from the register for data while decoding the data when reading the data to the register for data from the memory cell. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device (memory), and more particularly to a dynamic random access memory (DRAM) that can reduce noise during memory array operation and expand an operation margin when a memory cell is a single intersection cell.

  In DRAM, it is desired to reduce the manufacturing cost by reducing the chip area. In the one-intersection cell array shown in FIG. 9A, memory cells are connected to all the intersections of the word lines WL and the bit lines BL, and the cells are connected to half of the intersections of the currently used word lines and bit lines. The cell area can be reduced by 25% compared to the two intersection cells. In the figure, reference numerals SA0, SA1, SA2,... Are sense amplifiers.

However, compared with the two-intersection cell array, the one-intersection cell array has a problem of increasing array noise at the time of data reading, and is difficult to put into practical use.
Also in the two-intersection cell array, if the difference between the two parasitic capacitances between the complementary bit line and the word line becomes large and the noise cannot be offset, there is a similar problem of increasing array noise.

  FIG. 9B shows the principle of generation of word line noise which is one of array noise. The figure shows a case where the word line WL0 is activated, high (H) data is read to the bit line BL1T, and low (L) data is read to the bit lines BL0T, BL2T and the like.

  Here, it is assumed that the signal amount is exceptionally reduced in the bit line BL1T due to a leak current or the like. Then, the bit lines BL0 and BL2 having a large signal amount are amplified first. This potential change of the bit line causes a potential change of the word line WL0 via the parasitic capacitance CBLWL between the bit line and the word line as shown by a dotted arrow in FIG. Return to bit line BL1 via CBLWL.

  Since the signal amount of the bit line BL1 is small, the amplification is slow, and if the signal amount is reduced due to this noise, there is a risk of inversion by mistake. Similar noise is generated through the plate which is the counter electrode of the cell capacitor and the substrate of the cell transistor. Therefore, it is important to reduce this array noise in order to put the one-intersection array into practical use.

  Focusing on the bit line pair BL1T-BL1B, the worst case in which the array noise is the largest is that all the H data (defined as “1” data) or all the L data (“0”) on the bit lines BL0T, BL2T, etc. on the T side. Is defined as data).

  FIG. 10 shows a conventional example of a semiconductor memory in which this noise is reduced by encoding a data pattern of data written in a memory cell. Such noise reduction is described in detail in, for example, Japanese Patent Application Laid-Open No. 11-110967 and “IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 10, OCTOBER 1999, pp.1391-1394”. .

Japanese Patent Laid-Open No. 11-110967 “I EE Journal of Solid State Circuits, Vol. 34, No. 10, October 1999, p.1391-1394” (IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34 , NO. 10, OCTOBER 1999, pp.1391-1394) In this conventional semiconductor memory, bits input serially from the input / output pin DQ via the input / output buffer IOB are parallelized by the multiplexer MUX and temporarily registered. Simultaneously with writing to the RE, the serial data is counted by the burst counter BC. At this time, if the number of “1” is 25% or less or 75% or more, the flag FLG is set and half the data is inverted by the encoding circuit EN. In this way, the number of one data on one word line WL is always kept within the range of 25% to 75%, as compared with the case where 100% is “1” or 100% is “0”. The array noise can be reduced to 50%. In FIG. 10, MC is a memory cell, SA is a sense amplifier, BL is a bit line, DEC is a decoder, and SEL is a selection signal.

  However, in the semiconductor memory having the above-described conventional encoding circuit, a flag bit is necessary for each serially input data block. Therefore, when the number of serially input bits is small, the flag for the flag in the chip is used. There is a problem that the number of memory cells increases and the chip size increases.

  In addition, since data serially input from the input / output pin DQ is sequentially counted by the burst counter BC and the flag FLG is determined, there is a problem that the determination time becomes long and the memory cycle time is sacrificed.

  In addition, since the flag FLG has a determination criterion that the number of “1” is 25% or less or 75% or more, there is a problem that the circuit scale increases and the chip area increases.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device that can reduce noise by encoding data and reduce the sacrifice of chip size and memory cycle time.

  In order to solve the above problems, a semiconductor memory device according to the present invention includes a plurality of memory cells provided at intersections of a plurality of word lines and a plurality of bit lines, and a 1-bit flag provided for each word line. Memory cells, a plurality of sense amplifiers provided on the plurality of bit lines, a plurality of randomly accessible data registers for holding write data, and “1” and “0” of the write data It has an encoding control circuit for determining the ratio and an encoding circuit for inverting or writing the write data to the sense amplifier as it is based on the determination result of the encoding control circuit.

  The outline of this semiconductor memory device will be briefly described as follows. In other words, a random access data register is provided in the semiconductor memory chip, all accesses from outside the semiconductor memory chip are performed to the data register, and data is written from the data register to the memory cell array in parallel. The encoding circuit and the encoding control circuit are configured to perform the decoding operation by referring to the state of the flag when reading data from the memory cell to the data register. As a result, it is possible to suppress a reduction in operation margin due to array noise during reading, and to suppress an increase in chip size and memory cycle time during encoding.

  By providing a circuit for encoding a data pattern in the one-intersection memory cell array that can reduce the memory cell size and reduce the manufacturing cost, the array noise at the time of reading data peculiar to the one-intersection memory cell array is reduced by 50%. . Since this encoding is performed at the time of data transfer between the data register and the memory cell array, the access time penalty is reduced.

  Further, the encoding used in the semiconductor memory of the present invention is simplified by checking whether or not the number of bits of “1” data in a plurality of bits is a majority. This simplifies and reduces the time and circuit area required for encoding.

  Furthermore, since the encoding control circuit used in the semiconductor memory of the present invention compares data patterns in parallel using an analog circuit, it is possible to determine a data pattern at high speed.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of a semiconductor memory device according to the invention will be described with reference to the accompanying drawings.

<Embodiment 1>
FIG. 1 (a) shows a configuration of a low noise encoding DRAM which is a semiconductor memory device (hereinafter referred to as a semiconductor memory) according to the present invention, and FIG. In the low noise encoding DRAM chip 10 in the present embodiment, when reading (reading) or writing (writing) data, first, an activation command ACT is issued, and the memory cell MC in the memory cell array MCA is issued. Data is read and held in the sense amplifiers SA in the sense amplifier arrays SAB0 and SAB1.

  After the precharge of the sense amplifier SA is turned off, the sub word driver SWD activates the word line WL0, and reads the data in the memory cell MC to the bit lines BL0T, BL1T and the like. The sense amplifier SA differentially amplifies the minute signals generated on these bit lines using the B side bit lines BL0B, BL1B and the like as reference potentials, and holds the result.

  Here, the memory cell block amplified by the left-side sense amplifier array SAB0 for the data on one word line is indicated by a circle as MCB0 and amplified by the right-side sense amplifier array SAB1. A block of memory cells is represented by a square mark as MCB1 and divided into two blocks.

  Subsequently, a prefetch command PFC is issued, and the data in the sense amplifier SA is transferred to the data register RE via the main I / O line MIO. At this time, data of one of the blocks MCB0 and MCB1 divided into a plurality is selected by the block select signal BSL and transferred in parallel to the data register RE. When data is written from the main I / O line to the register RE, a data decoding operation described later is performed in the encoding circuit EN in the encoding circuit array ENB.

  The main I / O line is complementary to MIOT and MIOB for high speed, precharged to high level (H level) during standby, and either main I / O line MIOT or MIOB is used during data transmission Reduced to low level (L level). In the drawings and in the specification, T and B of complementary signal lines, for example, MIOT and MIOB may be written as MIOT / B. There are 256 main I / O lines, MIO0T,..., MIO255T and 256 MIO0B,..., MIO255B, which are represented as MIO0T / B,. Hereinafter, other complementary signals may be similarly expressed.

  As will be described in detail later, prior to data transfer, a flag register is connected from the sense amplifier connected to the flag bit line BLF0T / B via the flag main I / O line MIOFT / B before the data transfer. The flag status is transferred to FRE. The block number “0” or “1” is transferred from one of the block number drivers BND0 and BND1 to the block number register BN via the block number driver main I / O line MIONT / B.

  Data exchange with the outside of the DRAM chip is performed via the data register RE. When a read RED or write WRT command is issued, an address is designated for the register column REB by a column selection line YS from the column decoder YDEC. In the read operation, the data in the data register RE is output to the input / output pin DQ via the global I / O line GIO and the input / output buffer IOB. In the write operation, the data is transferred from the input / output pin DQ through the opposite path. The input data is written to the data register RE.

  After the necessary read / write with respect to the data in the data register RE is completed, the restore command RST is issued to write the data back from the data register RE to the memory cell array MCA. The data in the data register RE is written to the sense amplifier SA via the main I / O line MIO and simultaneously to the memory cell in which the word line is selected via the bit line. Finally, a precharge command PRE is issued to reset the word line and precharge the bit line.

  During the prefetch and restore operations described above, the data in the block is transferred between the sense amplifier SA and the data register RE in parallel. In the above, the case where the memory cell array is divided into two blocks MCB0 and MCB1 is shown. However, it is possible to further divide these to reduce the amount of data transferred between the sense amplifier and the data register at the same time. In this case, the number of main I / O lines can be reduced.

  In the low noise encoding DRAM of the present embodiment, the encoding circuit array ENB is provided between the data register array REB and the sense amplifier array SAB, and the data to be written to the sense amplifier and the memory cell is encoded. Reduce array noise when the cell array operates.

  When data is written from the data register RE to the sense amplifier SA during the restore operation, the number of bits of “0” data is always kept larger than the number of bits of “1” data for the data in the block MCB0. . Therefore, when “1” data becomes a majority, “1” is written to the flag register FRE, and the data is inverted. This encoding operation is realized by inverting the code in the data register RE in the encoding circuit array ENB, outputting it to the main I / O line MIO, and transferring it to the sense amplifier SA. If the data “1” is exactly half, the sign in the data register RE is output without being inverted, and transferred to the sense amplifier SA.

  Conversely, the block MCB1 is kept in a state where the number of bits of “1” data is larger than the number of bits of “0” data. Therefore, when “0” data becomes a majority, “1” is written to the flag register FRE, and the data is inverted. Since this flag FLG is necessary for the decoding operation at the time of prefetch for reading data from the memory cell MC to the data register RE, the flag FLG is provided with flag memory cells MCF0 and MCF1 for each word line, and in the flag register FRE at the time of restoration Is written in the flag memory cells MCF0 and MCF1. Also in this case, if the data “0” is exactly half, the flag register FRE remains “0”, and the data is output as it is without being inverted into the data register RE, to the sense amplifier SA. Forward.

  In FIG. 1 (a), the memory cells on one word line are divided into two blocks, but the present encoding method can be applied in the same way even when divided into two or more blocks. The block is divided into two groups so that the number of bits in the group is almost equal. In the block belonging to one group, the number of bits of “0” data is a majority, and in the block belonging to the other group, “1”. “Encode so that the number of data bits is a majority. In FIG. 1A, ENCNTL is an encoding control circuit, which will be described later.

  FIG. 1B shows the effect of reducing array noise in the coded DRAM which is a semiconductor memory in the present embodiment. When not encoded, the 512-bit data on the word line WL0 can be in a state of all “0” or all “1”, and at this time, the array noise becomes the largest. The array noises in these two states are almost equal in magnitude and opposite in sign, and are defined as array noise 100% and -100%, respectively. However, the bit line BLF of the flag memory cell is excluded.

  On the other hand, when the above-described encoding of the present embodiment is performed, the number of “1” data in the memory cell block MCB0 is 0 bits at the minimum and 128 bits at the maximum, and “1” in the memory cell block MCB1. “The number of data is 128 bits at the minimum and 256 bits at the maximum. Therefore, the total number of“ 1 ”data on the word line WL0 is limited to between 128 bits and 384 bits.

  Here, the potential fluctuation applied to a certain word line from the bit line for amplifying “1” data and the potential fluctuation applied to the word line from the bit line for amplifying “0” data have opposite signs. Negate each other. That is, the noise when the number of “1” is 384 bits and the number of “0” is 128 bits corresponds to the noise of subtracting 256 bits.

  Therefore, the array noise is reduced to almost 50% as compared with the case where all 512 bits are “1” data. Similarly, the array noise when the number of “1” is 128 bits and the number of “0” is 384 bits is reduced to almost 50% of the array noise when all 512 bits are “0”. Therefore, when considering the worst case, the encoding noise described in the present embodiment can reduce array noise via the word line, plate, and substrate by 50% on both the positive side and the negative side.

  3A and 3B show the data register string REB, the data register RE, the encoding circuit string ENB, the encoding circuit EN, the flag register FRE, and the block number register BN during the restore (RST) operation. Indicates the state.

As shown in FIG. 3A, when the data of the memory cell block MCB0 is in the data register row REB, the block number register BN is set to “0”. The encoding control circuit ENCNTL analyzes the data in the data register string REB. When the block number register BN is “0”, the number of bits of “0” data in the data register string is a majority. Sets the flag register FRE to “0” and sets the encoding circuit EN to the non-inverted state “F”. Then, the data in the data register RE is output as it is to the main I / O line MIO.
That is, when BN = “0” and the number of “0” s in RE is larger than the number of “1”, FRE = “0” and EN = “F” (non-inverted).

On the contrary, as shown in FIG. 3B, when the number of bits of one data in the data register string REB is a majority, the flag register FRE is set to “1” and the encoding circuit EN is in an inverted state. “R”. At this time, the data in the data register string REB is inverted and output to the main I / O line MIO. When the data of the memory cell block MCB1 is in the data register RE, the block number register BN is set to “1”, and the number of bits of “0” data in the data register RE is opposite to the above description. When the number is the majority, “1” is set in the flag register FRE, and when the number of bits of the “1” data is the majority, “0” is set in the flag register FRE.
That is, when BN = “0”, if the number of “0” in RE is less than the number of “1”, FRE = “1” and EN = “R” (inverted).

FIGS. 3C and 3D show the data register string REB, data register RE, encoding circuit string ENB, encoding circuit EN, flag register FRE, and block number register BN during prefetch (PFC) operation. Indicates the state.
When prefetching data, first read the flag state and block number from the flag memory cell MCF in the memory cell array MCA to the flag register FRE, and from the block number driver BND to the block number register BN. As a result, after determining the state of the encoding circuit EN, data is read from the memory cell array MCA into the data register RE.

  As shown in FIG. 3C, if the state of the flag register FRE is “0”, the encoding circuit EN is in the non-inverted state “F”, and the data of the main I / O line MIO is used as it is. Read into RE. On the other hand, as shown in FIG. 3D, when the state of the flag register FRE is “1”, the encoding circuit EN is in the inversion state “R”, and the data of the main I / O line MIO is inverted and the data Read into register RE. Therefore, the data encoded and written in the memory cell is decoded into the original data pattern inputted from the outside in the data register RE.

  The encoding in the present embodiment only needs to check one point of whether or not the number of bits of “1” data is a majority, and whether or not the number of bits of “1” data is 25% or more as in the conventional example. And it is simpler than examining two points: 75% or less. Therefore, the time required for the encoding operation can be shortened, access and cycle time are not sacrificed, and the scale of the encoding circuit can be reduced, so that there is an advantage that the circuit area can be reduced.

  FIG. 4 shows the configuration of the encoding circuit used in this embodiment. The encoding circuit EN has NMOS transistors MN1 and MN2 whose gates are connected to the T-side output FRET of the flag register FRE shown on the lower side of the figure, and whose gates are connected to the B-side output FREB of the flag register FRE. NMOS transistors MN3 and MN4. The drain / source path of the NMOS transistor MN1 is between the output RE0B on the B side of the data register RE and the main I / O line MIO0T on the T side, and the drain / source path of the NMOS transistor MN2 is the T side of the data register RE Output REOT and the B side main I / O line MIO0B. The drain / source path of the NMOS transistor MN3 is between the output REOT on the T side of the data register RE and the main I / O line MIO0T on the T side, and the drain / source path of the NMOS transistor MN4 is on the B side of the data register RE Output REOB and the B side main I / O line MIO0B.

  When the status of the flag register FRE is “0”, the T-side output FRET of the flag register is L level, and the B-side output FREB is H level, it is non-inverted, and the T-side outputs REOT and T of the data register Side main I / O line MIOT is connected, and the B side output REOB of the data register and the B side main I / O line MIOB are connected. When the flag register FRE is “1”, FRET is H level and FREB is L level, it is in the inverted state, the data register output terminal REOT and the main I / O line MIOB are connected, and the data register output Terminal REOB and main I / O line MIOT are connected. In FIG. 4, the NMOS transistor and the PMOS transistor are connected in parallel, and an analog switch whose gate is driven by a complementary signal may be used. In this case, the register read / write is performed. Has the advantage of speeding up.

  The data register circuit RE includes a bidirectional switch including inverters IV1 and IV2 whose input / output terminals are connected to each other and clocked inverters CIV1 to CIV4. The clocked inverters CIV1 and CIV3 controlled by the restore signal RS have input terminals connected to internal nodes REI0B and REI0T of the data register, respectively, and output terminals connected to data register output nodes REOT and REOB, respectively. On the other hand, the clocked inverters CIV2 and CIV4 controlled by the prefetch signal PF have their input terminals connected to the data register output nodes REOT and REOB, respectively, and their output terminals connected to the data register internal nodes REI0B and REI0T, respectively. The During the prefetch operation, the prefetch signal PF is activated and the data of the main I / O line MIO is read into the data register RE, and during the restore operation, the restore signal RS is activated and the data in the data register RE is main. Writing to the sense amplifier SA via the I / O line MIO and writing to the memory cell MC in which the word line is selected via the bit line.

  The internal terminal REI0T of the data register RE is connected to the global I / O line GIO via the column selection switch NMOS transistor MN5, and the column selection line YS is connected to the gate of the NMOS transistor MN5. During the read / write operation, the column selection line YS of a desired address is selected, the data register RE is connected to the global I / O line GIO, and data is input / output.

  The flag register FRE has a configuration similar to that of the data register RE, but an input clock PFF is provided independently in order to perform a prefetch operation before the data register. Since the block number register BN performs only reading, only the input switch is provided, and the clocked inverters CIV1 and CIV3 and the column selection switch NMOS transistor are excluded from the flag register FRE. The NMOS transistor MN6 in the flag register FRE is connected to the FREW terminal shown in FIG. 5 by a flag column selection line YSF input to the gate.

  FIG. 5 shows the encoding control circuit ENCNTL of the present embodiment. This circuit is an analog counter circuit that determines whether the number of “1” data or the number of “0” data in the data register RE is larger. The input transistors of the differential amplifier are connected in parallel, and the drains of the transistors MN11, MN12, etc., whose drains are connected in parallel to the output terminal OUTB, the T-side terminals REI0T, REI2T, etc. of the even-numbered data register and the H level The potential VCC is connected. On the other hand, the B-side terminals REI1B, REI3B, etc. of the odd-numbered registers and the L level potential VSS are connected to the gates of the transistors MN21, MN22, etc. whose drains are connected in parallel to the output terminal OUTT.

  When the counter activation signal CNTE is activated and the amplification is started, the output terminal when the number of bits of “1” data in the register is large and the number of T-side terminals is high is high. Since more transistors connected to OUTB are turned on, the B-side output terminal OUTB is amplified to a voltage lower than the T-side output terminal OUTT. Therefore, the output MST1 of the inverter IV5 is H, and the output MST0 of the inverter IV6 is L. At this time, if the block number register BN is “0”, one terminal BN0 of the register BN is H, and the other terminal BN1 is L, H is output to the FREW terminal of the flag register, When “1” can be written, block number register BN is “1”, one terminal BN0 of register BN is L, and the other terminal BN1 is H, L is output to terminal FREW of the flag register Then, “0” can be written to the flag memory cell.

  If the number of bits of “0” data in the data register RE is large and the B side terminal is more H level, there are more transistors connected to the T side output terminal OUTT. Since it is turned on, the output terminal OUTT on the T side is amplified to a lower voltage than the output terminal OUTB on the B side. Therefore, the output MST1 of the inverter IV5 is L, and the output MST0 of the inverter IV6 is H. At this time, if the block number register BN is “0”, one terminal BN0 of the register BN is H, and the other terminal BN1 is L, L is output to the flag register terminal FREW, and the flag flag “0” can be written to the memory cell, the block number register BN register is “1”, one terminal BN0 of the register BN is L, and the other terminal BN1 is H, the F flag register H is output to the terminal LGW, and “1” can be written to the flag memory cell.

  The encoding control circuit ENCNTL performs data pattern determination using an analog circuit in parallel, and there is no need to examine the contents of a register bit by bit as in the prior art, so that data pattern analysis is fast. For this reason, it is possible to perform encoding with little sacrifice of access and cycle time.

  FIG. 6 shows operation waveforms of the encoding circuit EN and the encoding control circuit ENCNTL. When a prefetch command PFC is input and a block is selected, data is read from the sense amplifier of the block to the data main I / O line MIO and the flag main I / O line MIOF.

  First, the flag input clock PFF is activated, data is read from the flag main I / O line MIOF into the flag register FRE, and data is read from the block number register main I / O line MION into the block number register BN. Based on the data of the flag, the polarity of the switch is selected in the encoding circuit EN. In FIG. 6, since the state of the flag register FRE is “1” (the terminal FRET is at the H level and the terminal FREB is at the L level), the data on the data main I / O line MIO is inverted and read into the data register RE. That is, the T / B of the main I / O line MIO0 and the T / B of the data register I / O line REI0 are inverted.

  The encoding control circuit ENCNTL activates the counter activation signal CNTE every time the write command WRT is input and the contents of the data register RE are rewritten, and determines whether there is more “1” data or “0” data. Then, the flag column selection line YSF is activated to update the state of the flag register FRE. During restoration, data in the data register RE is written to the main I / O line MIO in an inverted or non-inverted state depending on the state of the flag register FRE. At the same time, the state of the flag register FRE is also changed to the flag main I / O line MIOF. Then, the data is written to the sense amplifier and the memory cell.

<Embodiment 2>
FIG. 7 is a block diagram showing an example of an embodiment when the present invention is applied to a register built-in type DRAM. First, the operation of the DRAM of this embodiment will be described. An address signal ADD is input to the address buffer ADDBUF. The command decoder COMDEC receives a chip selection signal / CS, a row address strobe signal / RAS, a column address strobe signal / CAS, and a write enable signal / WE. A clock CLK and a clock enable signal CKE are input to the clock generation circuit CLKGEN. The command decoder COMDEC decodes the input control signal and determines an operation mode such as read, write, and precharge. The control logic LOGIC generates internal control signals necessary for the operation mode, and the current operation mode is held in the mode register MDREG.

  When the activate command is input, the word line is activated by the row decoder XDEC, and the data from the memory cell array MCA is amplified and held by the sense amplifier array SAB. When a prefetch command is input, a part of the data in the sense amplifier array SAB is selected by the block decoder BDEC and read into the data register string REB selected by the register selection decoder RESEL via the encoding circuit array ENB. It is.

  Conversely, in the restore operation, data is written from the data register string REB to the sense amplifier string SAB via the encoding circuit string ENB. The operations of the encoding circuit array ENB and the encoding control circuit ENCTNL at this time are as described in the first embodiment. When a read command is input, the data in the data register RE is selected by the column decoder YDEC and output from the input / output terminal DQ to the outside of the chip by the I / O buffer IOB via the data control circuit DTCNTL and the latch LTC. . When a write command is input, data input from the I / O buffer IOB is written to the selected column decoder YDEC via the latch LTC and the data control circuit DTCNTL. At this time, the data control circuit uses the data mask signal DQM to perform data mask processing.

  When there are a plurality of data register strings in the chip as shown in FIG. 7, if the encoding circuit EN and the encoding control circuit ENCNTL are shared, an encoding circuit and an encoding are provided for each data register string REB. The increase in chip area can be made smaller than when a control circuit is provided. Even if these circuits are shared, the prefetch, restore, and write operations are always performed on one register, so that the operation speed does not decrease.

  In addition, when the number of registers provided in one data register row REB in the same figure is large and data from a plurality of word lines are simultaneously read into one register row, the same word line is used. The belonging data is set as a sub-block, the encoding described in FIG. 1 is performed for each sub-block, and a flag memory cell is provided for each sub-block.

<Embodiment 3>
FIG. 8 shows an example of an embodiment in which the present invention is applied to a multichip module MCP. On the multi-chip module MCP, a plurality of chips that are difficult to integrate on a single chip, such as a DRAM chip 80, a flash (FLASH) memory chip 81, and a logic (LOGIC) chip 82, are mounted on a silicon substrate 83. Wiring between chips is performed using a silicon process. For this reason, the number of wirings can be remarkably increased as compared with mounting on a normal printed circuit board. Also, the mounting size can be reduced.

Accordingly, since the input / output pins of the chip can be increased, the main I / O line MIO of FIG. 1 can be output to the DRAM chip 80 outside the chip via the bidirectional buffer BDB. If the data register string REB and the encoding circuit string ENB are provided on the logic chip 82 side, the DRAM chip 80 can have a standard specification, and the specification can be changed on the LOGIC chip 82 side. In this way, the DRAM chip 80 can be mass-produced by sharing multiple types of multi-chip modules MCP, and if only the logic chip 82 is designed according to the type, low noise coding can be achieved without increasing costs. realizable.
In addition, SRAM and FLASH memory are provided in the multi-chip module MCP, programs are stored in the FLASH memory, data is held in SRAM, and DRAM is used as an image cache and application work memory. A memory system with low power can be configured. This leads to a longer operation time in mobile devices such as mobile phones.

  Although several preferred embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various design changes can be made without departing from the spirit of the present invention. Of course you get. For example, in the embodiment, a one-intersection memory cell array has been described as an example. However, even in a two-intersection memory cell array, when the difference between two parasitic capacitances between two bit lines complementary to a word line is large, noise cannot be offset. It goes without saying that the same effect can be obtained by applying the present invention. In other words, a data pattern including a randomly accessible data register, a flag memory cell, an encoding circuit, and an encoding control circuit may be encoded and decoded.

FIG. 4A is a configuration diagram of the semiconductor memory device of the present invention, and FIG. 4B is an explanatory diagram of array noise reduction by encoding of the semiconductor memory device of the present invention. FIG. 5 is an operation waveform diagram of the semiconductor memory device of the present invention. FIG. 2 is a conceptual diagram of low noise encoding according to the present invention, in which FIGS. (A) and (b) are during a restore operation and (c) and (d) are during a prefetch operation. FIG. 2 is a specific circuit diagram of a principal part of the encoding circuit shown in FIG. 1. FIG. 2 is a specific circuit diagram of a principal part of the encoding control circuit shown in FIG. 1. FIG. 6 is an operation waveform diagram of the encoding circuit and the encoding control circuit shown in FIGS. 4 and 5. FIG. 6 is a diagram showing an example of application of the semiconductor memory device of the present invention to a register built-in type DRAM. FIG. 10 is a diagram showing an example of application of the semiconductor memory device of the present invention to a multichip module. The figure explaining the generation | occurrence | production principle of the word line noise in one intersection array. The figure which shows the structural example of the conventional encoding DRAM.

Explanation of symbols

  10 ... Semiconductor memory chip, 80 ... DRAM chip, 81 ... FLASH memory chip, 82 ... Logic chip, 83 ... Silicon substrate, MC ... Memory cell, BL ... Bit line, WL ... Word line, SA ... Sense amplifier, SWD ... Subword Driver, BSL ... Block selection signal, MIO ... Main I / O line, EN ... Encoding circuit, RE ... Data register, FRE ... Flag register, BN ... Block number register, ENCNTL ... Encoding control circuit, YDEC ... Column Decoder, YS ... Column selection line, IOB ... I / O buffer, IV1 to IV6 ... Inverter, GIO ... Global I / O line, DQ ... I / O terminal.

Claims (7)

A word line,
A plurality of first bit lines intersecting the word line;
A plurality of second bit lines intersecting the word line;
A first flag bit line intersecting the word line;
A second flag bit line intersecting the word line;
A first memory cell group disposed at a location where the word line and the plurality of first bit lines intersect;
A second memory cell group disposed at the intersection of the word line and the plurality of second bit lines;
A first flag memory cell disposed at a location where the word line and the first flag bit line intersect;
A memory cell array including a second flag memory cell disposed at a location where the word line intersects the second flag bit line;
A plurality of first sense amplifiers connected to each of the first bit lines;
A plurality of second sense amplifiers connected to each of the second bit lines;
A first flag sense amplifier connected to the first flag bit line;
A second flag sense amplifier connected to the second flag bit line;
The plurality of first bit lines and the plurality of second bit lines are alternately arranged,
The memory cell array is disposed between the plurality of first sense amplifiers and the plurality of second sense amplifiers,
The data held in the plurality of first sense amplifiers and the data held in the plurality of second sense amplifiers are independently encoded,
The first flag memory cell stores information corresponding to data stored in the plurality of first memory cells;
The semiconductor memory device, wherein the second flag memory cell stores information corresponding to data stored in the plurality of second memory cells. The semiconductor memory device according to claim 1.
A plurality of main bit lines connected to each of the first sense amplifiers and each of the second sense amplifiers;
And an encoding circuit connected to the plurality of main bit lines and encoding data read from one of the plurality of first sense amplifiers or the plurality of second sense amplifiers. Semiconductor memory device. The semiconductor memory device according to claim 2.
Each of the plurality of main bit lines is a relative bit line. The semiconductor memory device according to claim 1.
Further, a plurality of data registers for holding data input from the data input / output circuit terminals,
An encoding control circuit for detecting a ratio of the number of data having “1” data held in each of the data registers;
The semiconductor memory device, wherein the encoding control circuit determines whether to invert the data held in the plurality of data registers by the encoding circuit. The semiconductor memory device according to claim 1.
The semiconductor memory device, wherein the plurality of first bit lines and the plurality of second bit lines have an open bit line structure. The semiconductor memory device according to claim 1.
The semiconductor memory device, wherein each of the plurality of first memory cells and the plurality of second memory cells includes a MOS transistor and a capacitor. The semiconductor memory device according to claim 1.
The semiconductor memory device, wherein data of the plurality of first sense amplifiers is encoded in a batch, and data of the plurality of second sense amplifiers is encoded in a batch.

Images