JP2008204554A - Semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform reading and writing of data at high speed without increasing operation frequency. <P>SOLUTION: When read amplifier activation signal DAE becomes H-level, PMOS transistors 8 and 9 are OFF, and a read amplifier 72 is activated. At that time, the read amplifier 72 is laid in a state interrupted from a write amplifier 71, and thus amplifies and supplies data to an output buffer without being affected by the write amplifier 71. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device suitable for use in a DRAM.

2. Description of the Related Art Conventionally, a semiconductor memory device (memory chip) that enables high-speed operation and can be miniaturized has been disclosed (see, for example, Patent Document 1). As shown in FIG. ₁ , the read amplifier 42 ₁ and the write amplifier 43 ₁ are connected to the global I / O line 45 via the first switch (SW ₁ ) 44 ₁ . The pair of memory planes 11 ₁ and 12 ₁ share the combination of the precharge circuit 41 ₁ , the read amplifier 42 _1, and the write amplifier 43 ₁ .

With such a configuration, the read amplifier 42 ₁ reads data from the pair of memory planes 11 ₁ and 12 ₁ and outputs the read data to the outside via the global I / O line 45. The write amplifier 43 _1, the data supplied from the global I / O line 45 is written to a pair of memory planes 11 ₁ and 12 _1.
JP 2003-223785 A

As shown in FIG. 4 of the document, read amplifier 42 ₁ and the write amplifier 43 ₁ are connected to each other. Here, if the write cycle is to be executed during the read cycle, the write amplifier 43 ₁ affects the read amplifier 42 ₁ , so the read cycle and the write cycle cannot be executed in the same cycle. Therefore, in order to read and write data at high speed, it is necessary to increase the operating frequency in order to execute the read cycle and the write cycle in a short time.

  Depending on the application, different data can be written to the same address immediately after the data at a certain address is read out. However, such a semiconductor memory device needs to read and write data in a read cycle and a write cycle, respectively, and cannot be performed in the same cycle.

  The present invention has been proposed to solve the above-described problems, and an object of the present invention is to provide a semiconductor memory device capable of reading and writing data at high speed without increasing the operating frequency.

  A semiconductor memory device according to the present invention includes a memory bank in which a plurality of memory cells are arranged, data reading means for reading data from the memory bank via a data input / output line, and holding the data, and the data reading Data writing means for writing data to the memory bank via the data input / output line, and data input means for supplying data input from the outside to the data writing means, in the same cycle as the data reading by the means; Data output means for outputting the data held by the data reading means to the outside.

  In the semiconductor memory device having such a configuration, even when a change occurs in the voltage of the data input / output line, the data reading means holds the data read from the memory bank via the data input / output line. Can be read. As a result, the semiconductor memory device can normally read and write data in the same cycle.

  Here, the semiconductor memory device may further include a switching element that is provided on the data input / output line and is turned off when either the data reading unit or the data writing unit is activated. At this time, the data reading means may be connected to the data writing means via the switch element.

  The semiconductor memory device according to the present invention can read and write data at high speed without increasing the operating frequency.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

[First Embodiment]
FIG. 1 is a block diagram showing a configuration of a semiconductor memory device according to the first embodiment of the present invention.

  The semiconductor memory device includes a row clock generator 10 that generates a row clock, a column clock generator / burst counter 20 that generates a column address or counts a burst, and a row that temporarily accumulates a row address or counts the number of refreshes. An address buffer / refresh counter 30, a column address buffer 40 for temporarily storing column addresses, and a data mask buffer 50 for temporarily storing data masks are provided.

  In addition, the semiconductor memory device includes a memory bank 100A for storing data, a data control circuit 70 for performing control of writing or reading data to / from the memory bank 100A, and data D input from the outside to temporarily store data D An input buffer 61 that supplies the control circuit 70 and an output buffer 62 that temporarily stores the data Q read from the data control circuit 70 and outputs the data Q to the outside are provided.

  The memory bank 100A includes a memory cell array 101A in which a plurality of memory cells are arranged, a row decoder (X-decoder) 102A that controls the voltage of a word line based on a row address that is an address for selecting a row direction, and a column direction. A column decoder (Y-decoder) 103A for controlling the voltage of the column selection line based on a column address which is an address for selecting data, and a sense amplifier 104A for amplifying the voltage of the memory cell when reading data. Yes.

  The memory cell array 101A is composed of a plurality of memory cells arranged in a matrix. When a row address is supplied from the row address buffer / refresh counter 30, the row decoder 102A controls the word line voltage based on the row address and activates it in order to select a memory cell corresponding to the row address. .

  The column decoder 103A activates the column selection line of the memory cell array 101A. That is, when the column address is supplied from the column address buffer 40, the column decoder 103A controls and activates the voltage of the column selection line of the memory bank 100A based on the column address.

  As a result, a memory cell is selected based on the row address and the column address, and data is written to the selected memory cell, or data is read from the selected memory cell. The read data is amplified by the sense amplifier 104A.

  In addition, the memory bank 100A has a large number of input / output pins, for example, 512 input pins and output pins capable of simultaneous input or output of 512 bits of data. Read or write data 512 bits at a time.

  Here, the row clock generator 10 generates a row clock for synchronizing row addresses based on an externally supplied clock (CLK), chip select signal (CSB), and refresh signal (REF). The row clock generator 10 supplies this row clock to the row address buffer / refresh counter 30 and the memory bank 100A.

  The column clock generator / burst counter 20 determines the column address based on the clock (CLK), chip select signal (CSB), refresh signal (REF), read enable signal (REB), and write enable signal (WEB). Generate a column clock to synchronize. The column clock generator / burst counter 20 supplies the column clock to the column address buffer 40, the data mask buffer 50, the input buffer 61, the output buffer 62, and the data control circuit 70.

  The row address buffer / refresh counter 30 temporarily stores a row address Ai (i = 4 to 16) supplied from the outside in synchronization with the row clock generated by the row clock generator 10 and then stores the row address. Supply to the memory bank 100A. The row address buffer / refresh counter 30 counts the number of refreshes of the memory bank 100A.

  The column address buffer 40 temporarily stores the column address Ai (i = 0 to 3) supplied from the outside in synchronization with the column clock generated by the column clock generator / burst counter 20. Then, the column address buffer 40 supplies the column address to the column decoder 103A of the memory bank 100A.

  The data mask buffer 50 temporarily stores the data mask DMi [i = 0 to 63] supplied from the outside, and then supplies the data mask DMi to the data control circuit 70.

  The input buffer 61 temporarily stores 512-bit data D to be written, which is input via, for example, 512 multi-bit input terminals, and then supplies the data D to the data control circuit 70. The output buffer 62 temporarily stores the 512-bit data Q output from the data control circuit 70 and outputs the data Q to the outside via, for example, 512 multi-bit output terminals.

  When the 512-bit data is supplied from the input buffer 61, the data control circuit 70 writes 512-bit data at a time to the memory bank 100A. The data control circuit 70 also reads 512 bits of data at a time from the memory bank 100A, temporarily stores the data, outputs 512 bits at a time, and supplies the 512 bits of data Q to the output buffer 66.

  FIG. 2 is a circuit diagram showing the main configuration of the memory bank 100A and the data control circuit 70. As shown in FIG. The memory cell array 101A of the memory bank 100A has a plurality of memory cells arranged in a matrix, a plurality of word line pairs WL arranged in the row direction (WL1k to WL100), and arranged in the column direction. And a plurality of column selection lines CSL (CSL0 to CSLj). When a predetermined voltage is applied to the predetermined word line WL and activated, the charge of the memory cell is output to the bit line pair BL, / BL.

  Each word line WL is connected to the row decoder 102A. When a row address is supplied from the row address buffer / refresh counter 30 shown in FIG. 1, the row decoder 102A outputs a predetermined level signal to the word line WL corresponding to the row address and activates it for a predetermined time. The signal output is stopped later. The row decoder 102A has an internal delay element for automatically resetting the signal after outputting the signal so that the row decoder 102A can operate with only one command.

  The sense amplifier 104A amplifies and outputs each voltage of the bit line pair BL, / BL. Note that the output terminal of the sense amplifier 104A from which the amplified value of the bit line BL is output is connected to the source of the MOSFET2. The output terminal of the sense amplifier 104A from which the amplified value of the bit line / BL is output is connected to the source of the MOSFET 3.

  The drain of the MOSFET 2 is connected to the local input / output line LIOT, and the gate thereof is connected to the column selection line CSL. The drain of the MOSFET 3 is connected to the local input / output line LION, and the gate thereof is connected to the column selection line CSL. Accordingly, when a predetermined voltage is applied to the column selection line CSL and activated, the MOSFETs 2 and 3 are turned on. Then, the sense amplifier 104A outputs the voltage of the bit line BL to the local input / output line LIOT, and outputs the voltage of the bit line / BL to the local input / output line LION.

  The data control circuit 70 also includes a write amplifier 71 that writes data to the memory bank 100A, a read lamp 72 that reads data from the memory bank 100A, a negative OR circuit 6, a negative circuit 7, and PMOS transistors 8 and 9. It is equipped with.

  The write amplifier 71 is activated when the write amplifier activation signal WAE is supplied, amplifies the data supplied from the input buffer 61, and writes it to the memory bank 100A. The read amplifier 72 is a data latch type and holds (latches) data of the global input / output lines GIOT and GION. The read amplifier 72 is activated when the read amplifier activation signal DAE is supplied, amplifies the data, and supplies the amplified data to the output buffer 62.

  A global input / output line pair GIOT, GION is connected to the write amplifier 71 and the read amplifier 72. Therefore, the write amplifier 71 writes data to the memory bank 100A via the global input / output line pair GIOT and GION. The read amplifier 72 reads data from the memory bank 100A via the global input / output line pair GIOT, GION.

  The global input / output line pair GIOT is connected to the drain of the MOSFET 4. The source of the MOSFET 4 is connected to the local input / output line LIOT, and the selection signal SEL is input to its gate. The global input / output line pair GION is connected to the drain of the MOSFET 5. The source of the MOSFET 5 is connected to the local input / output line LION, and the selection signal SEL is input to its gate.

  Therefore, when the selection signal SEL changes from the low level to the high level, the MOSFETs 4 and 5 are turned on, and the local input / output line pair LIOT and LION are connected to the global input / output line pair GIOT and GIOTN. At this time, the write amplifier 71 can write data to the memory bank 100A via the global input / output line pair GIOT and GION, and the read amplifier 72 receives data from the memory bank 100A via the global input / output line pair GIOT and GION. Can be read out.

  The negative OR circuit 6 calculates the negative logical sum of the write amplifier activation signal WAE and the read amplifier activation signal DAE. The output terminal of the NOR circuit 6 is connected to the PMOS transistors 8 and 9 via the NOT circuit 7.

  Here, when both the write amplifier activation signal WAE and the read amplifier activation signal DAE are at L level, that is, when both the write amplifier 71 and the read amplifier 72 are not activated, the PMOS transistors 8 and 9 are turned on. Become. At this time, the read amplifier 72 holds (latches) the data of the global input / output lines GIOT and GION.

  When the read amplifier activation signal DAE becomes H level, the PMOS transistors 8 and 9 are turned off and the read amplifier 72 is activated. At this time, the read amplifier 72 is disconnected from the write amplifier 71, and the data is amplified and supplied to the output buffer 62 without being affected by the write amplifier 71.

  When the write amplifier activation signal WAE becomes H level, the PMOS transistors 8 and 9 remain off and the write amplifier 71 is activated. At this time, since the write amplifier 71 is disconnected from the read amplifier 72, the amplified data is written to the memory bank 100A via the global input / output lines GIOT and GION without affecting the read amplifier 72. be able to.

  FIG. 3 is a timing chart of external signals and internal signals of the semiconductor memory device according to the first embodiment. External signals of the semiconductor memory device include a clock (CLK), an address indicating one of a row address and a column address (Ai: i = 0, 1, 2,..., 16), a read enable signal (REB). , Write enable signal (WEB), input data (Di / DMj), and output data (Qi).

  As internal signals, a RAS bar signal RASB indicating activation in the row direction specified by the row address (indicating activation at the L level), a column selection indicating activation in the column direction specified by the column address There are a signal CSLk (k = 0, 1,...), A read amplifier activation signal DAE, and a write amplifier activation signal WAE.

  According to FIG. 3, the address A (i) is supplied to the semiconductor memory device every clock, and a write cycle, a read cycle, and a read-write cycle are performed.

(Light cycle)
When the clock 0 rises, the write enable signal WEB becomes L level, and the write cycle starts. At this time, data Di (0) and address A (0) indicating the storage destination of the data are input to the semiconductor memory device.

  Then, in synchronization with the rising edge of clock 0, RASB falls for a predetermined time, whereby the word line WL indicated by the row address is activated, and then the column selection signal CSL0 rises. As a result, the memory cell indicated by the row address and the column address is selected.

  Further, the write amplifier activation signal WAE rises after a predetermined time from the column selection signal CSL0. As a result, the write amplifier 71 shown in FIG. 2 writes data to the selected memory cell via the global input / output line GIOT / N and the local input / output line LIOT / N.

(Read cycle)
When the clock 1 rises, the read enable signal REB becomes L level and the read cycle starts. At this time, an address A (1) indicating a storage destination of data to be read is input to the semiconductor memory device.

  Then, in synchronization with the rise of clock 1, RASB falls for a predetermined time, thereby activating the word line WL indicated by the row address, and then the column selection signal CSL1 rises. As a result, the memory cell indicated by the row address and the column address is selected. The data of the selected memory cell is supplied to the read amplifier 72 via the global input / output line GIOT / N and the local input / output line LIOT / N.

  Further, the read amplifier activation signal DAE rises after a predetermined time from the column selection signal CSL1. As a result, the read amplifier 72 shown in FIG. 2 amplifies the data read from the memory cell and supplies the amplified data to the output buffer 62 shown in FIG.

(Read-write cycle)
When clock 2 rises, both the write enable signal and the read enable signal become L level, and the read-write cycle starts. At this time, the address A (2) indicating the storage destination of the data to be read and the storage destination of the new data Di (2) and the new data Di (2) are input to the semiconductor memory device. .

  Then, in synchronization with the rising edge of the clock 2, the word line WL indicated by the row address is activated when RASB falls for a predetermined time, and then the column selection signal CSL2 rises. As a result, the memory cell indicated by the row address and the column address is selected. The data of the selected memory cell is supplied to the read amplifier 72 via the global input / output line GIOT / N and the local input / output line LIOT / N.

  Further, the read amplifier activation signal DAE rises after a predetermined time delay from the column selection signal CSL0, and the write amplifier activation signal WAE rises after a predetermined time delay from the read amplifier activation signal DAE. As a result, the read amplifier 72 shown in FIG. 2 amplifies the data read from the memory cell and supplies the amplified data to the output buffer 62 shown in FIG. Thereafter, the write amplifier 71 writes data to the selected memory cell via the global input / output line GIOT / N and the local input / output line LIOT / N.

  FIG. 4 is a timing chart showing internal signals in the read-write cycle. When RASB falls, the word line WL rises and is activated after a predetermined time, and a difference signal is generated between the bit line pair BL and / BL.

  Next, when the column selection signal CSL rises, the data in the memory cell is supplied to the global input / output line pair GIOT / N. As a result, the global input / output line GIOT / N generates a difference signal from the VCC level. Then, the read amplifier activation signal DAE rises (period T1), and the read amplifier 72 shown in FIG. 2 is activated to amplify and output the difference signal of the global input / output line GIOT / N. At this time, since the PMOS transistors 8 and 9 shown in FIG. 2 are turned off, even if the global input / output line GIOT / N subsequently changes, the read amplifier 72 is not affected.

  Further, when the write amplifier activation signal WAE rises (period T2), the write amplifier 71 shown in FIG. 2 is activated and writes data via the global input / output line GIOT / N. As a result, the difference signal of the global input / output line GIOT / N is inverted. At this time, since the PMOS transistors 8 and 9 remain off, the write amplifier 71 can write data without affecting the read amplifier 72.

  As described above, the semiconductor memory device according to the first embodiment cuts off the connection state between the write amplifier 71 and the read amplifier 72 when either the write amplifier 71 or the read amplifier 72 is activated. Read or write data in the state. As a result, even if the difference signal of the global input / output line GIOT / N changes in the same cycle, the semiconductor memory device can normally write the data after reading the data normally. As a result, since the semiconductor memory device reads and writes data of 512 bits at the same cycle, it can process at high speed without increasing the operating frequency.

[Second Embodiment]
Next, a second embodiment of the present invention will be described. The same circuits as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  FIG. 5 is a block diagram showing a configuration of a semiconductor memory device according to the second embodiment of the present invention. The semiconductor memory device according to the second embodiment has a so-called two-bank configuration, and includes a memory bank 100B in addition to the configuration shown in FIG. The memory bank 100B includes a memory cell array 101B, a row decoder (X-decoder) 102B, a column decoder (Y-decoder) 103B, and a sense amplifier 104B. The data control circuit 70 is provided with two sets of circuits having the configuration shown in FIG. 2 (for the memory banks 100A and 100B).

  FIG. 6 is a timing chart of external signals and internal signals of the semiconductor memory device according to the second embodiment. Note that “A” attached to the data or signal indicates that the memory bank 100A is used, and “B” indicates that the memory bank 100B is used.

  As an external signal of the semiconductor memory device, there is ACTB in addition to the signal shown in FIG. As internal signals, instead of the CSLk shown in FIG. 3, a column selection signal CSLAk (k = 0, 1,...) For the memory bank 100A and a column selection signal CSLBk (k = 0, 1, ...).

  According to FIG. 6, an address A (i) is supplied to the semiconductor memory device every two clocks, and a write cycle, a read cycle, and a read-write cycle are performed.

(Light cycle)
When the clock 0 rises, the write enable signal WEB becomes L level, and the write cycle starts. At this time, data Di (0A), data Di (0B) after the elapse of one clock, and address A (0) indicating the storage destination of these data are input to the semiconductor memory device.

  Next, in synchronization with the rise of the clock 1, the word line WL indicated by the row address is activated when RASB falls for a predetermined time.

  In clock 2, the column selection signal CSLA0 / CSLB0 rises in synchronization with the fall of the RASB. As a result, the memory cell indicated by the row address and the column address is selected. Further, the write amplifier activation signal WAE rises after a predetermined time delay from the column selection signal CSLA0 / CSLB0. As a result, the write amplifier 71 shown in FIG. 2 writes data Di (0A) and Di (0B) to the selected memory cell via the global input / output line GIOT / N and the local input / output line LIOT / N.

(Read cycle)
When clock 2 rises, the read enable signal becomes L level, and a read cycle starts. At this time, an address A (1) indicating a storage destination of data to be read is input to the semiconductor memory device.

  Next, in synchronization with the rise of the clock 3, the word line WL indicated by the row address is activated when RASB falls for a predetermined time.

  In clock 4, the column selection signal CSLA1 / CSLB1 rises in synchronization with the fall of the RASB. As a result, the memory cell indicated by the row address and the column address is selected. The data of the selected memory cell is supplied to the read amplifier 72 via the global input / output line GIOT / N and the local input / output line LIOT / N.

  Further, the read amplifier activation signal DAE rises after a predetermined time from the column selection signal CSL1. As a result, the read amplifier 72 shown in FIG. 2 amplifies the data read from the memory cell and supplies the amplified data to the output buffer 62 shown in FIG. Then, the data Qi (A1) is output from the output buffer 62 to the outside.

(Read-write cycle)
When the clock 4 rises, both the write enable signal and the read enable signal become L level, and a read-write cycle starts. At this time, the semiconductor memory device has an address A (2) indicating a storage destination of data to be read and a storage destination of new data Di (2A) and Di (2B), and new data Di (2A). Data Di (2B) is input after one clock.

  Then, in synchronization with the rise of the clock 5, the word line WL indicated by the row address is activated when RASB falls for a predetermined time.

  In the clock 6, the column selection signal CSLA2 / CSLB2 rises in synchronization with the fall of the RASB. As a result, the memory cell indicated by the row address and the column address is selected. The data of the selected memory cell is supplied to the read amplifier 72 via the global input / output line GIOT / N and the local input / output line LIOT / N.

  Further, the read amplifier activation signal DAE rises after a predetermined time delay from the column selection signal CSLA2 / CSLB2, and the write amplifier activation signal WAE rises after a predetermined time delay from the read amplifier activation signal DAE. As a result, the read amplifier 72 shown in FIG. 2 is disconnected from the write amplifier 71, amplifies the data read from the memory cell, and supplies the amplified data to the output buffer 62 of FIG. The write amplifier 71 writes data to the selected memory cell via the global input / output line GIOT / N and the local input / output line LIOT / N while being disconnected from the read amplifier 72.

  As described above, the semiconductor memory device according to the second embodiment reads and writes 512-bit data in the same cycle even in the two-bank configuration, as in the first embodiment. High-speed processing can be performed without increasing the operating frequency.

[Third Embodiment]
Next, a third embodiment of the present invention will be described. In addition, the same code | symbol is attached | subjected about the same circuit as embodiment mentioned above, and the detailed description is abbreviate | omitted.

  FIG. 7 is a block diagram showing a configuration of a semiconductor memory device according to the third embodiment of the present invention. The semiconductor memory device according to the third embodiment has a so-called four-bank configuration, and includes memory banks 200A and 200B in addition to the configuration shown in FIG.

  FIG. 8 is a timing chart of external signals and internal signals of the semiconductor memory device according to the third embodiment. Note that “A”, “B”, “C”, and “D” attached to the data indicate that they are for the memory banks 100A, 100B, 200A, and 200B, respectively. Further, “A1”, “B1”, “A2”, and “B2” attached to the signals indicate that they are for the memory banks 100A, 100B, 200A, and 200B, respectively.

  According to FIG. 8, the address A (i) is supplied to the semiconductor memory device every four clocks, and a write cycle, a read cycle, and a read-write cycle are performed.

(Light cycle)
When the clock 0 rises, the write enable signal WEB becomes L level, and the write cycle starts. At this time, an address A (0) indicating a data storage destination and data Di (0A), Di (0B), Di (0C), and Di (0D) are input to the semiconductor memory device from clock 0 to clock 3. Is done. When the write amplifier activation signal WAE1 rises at clock 2, data Di (0A) and Di (0B) are written to the memory banks 100A and 100B, respectively. Further, when the write amplifier activation signal WAE2 rises at the clock 4, data Di (0C) and Di (0D) are written in the memory banks 200A and 200B, respectively.

(Read cycle)
When the clock 4 rises, the read enable signal REB becomes L level and the read cycle starts. At this time, an address A (1) indicating a storage destination of data to be read is input to the semiconductor memory device. When the read amplifier activation signal DAE1 rises at clock 6, data Qi (1A) and Qi (1B) are read from the memory banks 100A and 100B, respectively. Further, when the read amplifier activation signal DAE2 rises at the clock 8, data Qi (1C) and Qi (1C) are read from the memory banks 200A and 200B, respectively. These data Qi (1A), Qi (1B), Qi (1C), and Qi (1C) are output to the outside over clocks 9-12.

(Read-write cycle)
When the clock 8 rises, both the write enable signal and the read enable signal become L level, and the read-write cycle starts. At this time, the semiconductor memory device has an address A (2) indicating a storage destination of data to be read and a storage destination of new data Di (2A), Di (2B), Di (2C), Di (2D). Then, new data Di (2A), Di (2B), Di (2C), and Di (2D) are input.

  In the clock 10, the read amplifier activation signal DAE1 rises, and after a predetermined time elapses, the write amplifier activation signal WAE1 rises. As a result, after data Qi (2A) and Qi (2B) are read from the memory banks 100A and 100B, respectively, data Di (2A) and Di (2B) are written to the memory banks 100A and 100B, respectively.

  In the clock 12, the read amplifier activation signal DAE2 rises, and after a predetermined time elapses, the write amplifier activation signal WAE2 rises. As a result, after data Qi (2C) and Qi (2D) are read from the memory banks 200A and 200B, respectively, data Di (2C) and Di (2D) are written to the memory banks 100A and 100B, respectively.

  As described above, the semiconductor memory device according to the third embodiment reads and writes data in 512 bits at the same cycle even in the 4-bank configuration, as in the above-described embodiment. High-speed processing can be performed without increasing the frequency.

  Note that the present invention is not limited to the above-described embodiment, and it is needless to say that the present invention can also be applied to a design modified within the scope of the claims.

1 is a block diagram showing a configuration of a semiconductor memory device according to a first embodiment of the present invention. It is a circuit diagram which shows the principal part structure of a memory bank and a data control circuit. 3 is a timing chart of external signals and internal signals of the semiconductor memory device according to the first embodiment. It is a timing chart which shows the internal signal in a read-write cycle. It is a block diagram which shows the structure of the semiconductor memory device based on the 2nd Embodiment of this invention. 6 is a timing chart of external signals and internal signals of the semiconductor memory device according to the second embodiment. It is a block diagram which shows the structure of the semiconductor memory device based on the 3rd Embodiment of this invention. 12 is a timing chart of external signals and internal signals of the semiconductor memory device according to the third embodiment.

Explanation of symbols

6 NAND circuit 7 NAND circuit 8, 9 PMOS transistor 61 Input buffer 62 Output buffer 70 Data control circuit 71 Write amplifier 72 Read amplifier 100A, 100B, 200A, 200B Memory bank

Claims (2)

A memory bank in which a plurality of memory cells are arranged; and
Data reading means for reading data from the memory bank and holding the data via a data input / output line;
Data writing means for writing data to the memory bank via the data input / output line in the same cycle as the data reading by the data reading means;
Data input means for supplying data input from the outside to the data writing means;
Data output means for outputting the data held by the data reading means to the outside;
A semiconductor memory device. A switching element provided on the data input / output line, which is turned off when either the data reading means or the data writing means is activated;
The semiconductor memory device according to claim 1, wherein the data reading unit is connected to the data writing unit via the switch element.

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