JP2006338813A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of improving the stability of refresh operation in a standby state without reducing the speed of accessing a memory cell in an active state. <P>SOLUTION: A switch circuit SW1 selects the output signal of a delay circuit 40 when an internal chip enable signal int/CE is at an activated level (active state), and the output signal of a delay circuit 41 when the internal chip enable signal int/CE is at an inactivated level state (standby state). Delay time DL2 by the delay circuit 41 is set longer by predetermined time than delay time DL1 by the delay circuit 40. Thus, a refresh operation period in the standby state is set longer than that in the active state. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device, and more particularly to a dynamic semiconductor memory device capable of performing a refresh operation without depending on an external input signal.

  The pseudo SRAM is a semiconductor memory device that operates as an SRAM (static type semiconductor memory device) externally although the memory itself is a DRAM (dynamic type semiconductor memory device). In this pseudo SRAM, the same internal memory cells as those in the DRAM are used. On the other hand, external interfaces such as input control signals and address signals are the same as those of SRAM.

  The refresh operation of the pseudo SRAM is not controlled by an external signal unlike the refresh operation or the self-refresh operation of the conventional DRAM, but is a refresh output periodically output from a refresh circuit in the semiconductor memory device. This is performed based on the command signal / REFE. The refresh circuit includes a timer circuit which is a ring oscillator, and the refresh circuit outputs a refresh command signal / REFE in response to a cycle signal / Refcyc periodically output by the timer circuit. Since the timer circuit always outputs a cycle signal / Refcyc, this pseudo SRAM periodically refreshes both in an active state where data can be read or written and in a standby state where data is held. Execute.

For example, in Patent Document 1 below, the stability of the refresh operation is ensured in a semiconductor memory device having an operation state in which data can be read and written and a standby state in which data is held. A method for enabling is disclosed. According to this, it is possible to prevent the refresh operation and the read operation or the write operation from being performed at the same timing.
JP 2002-352577 A

  In the pseudo SRAM, the refresh operation period is set to be as short as possible in order to increase the access speed to the memory cell in the active state. However, if the refresh operation period is set short, there is a high possibility that the memory cell is not sufficiently refreshed. In particular, when the standby state is long, if a voltage drop occurs due to external noise or the like, there arises a problem that the stability of the refresh operation cannot be ensured. On the other hand, if the refresh operation period is set to be long, the refresh operation margin is improved and the stability of the refresh operation is ensured, but the access speed to the memory cell is slowed down.

  Therefore, a main object of the present invention is to provide a semiconductor memory device capable of improving the stability of the refresh operation in the standby state without reducing the access speed to the memory cell in the active state.

  A semiconductor memory device according to the present invention is a semiconductor memory device having an active state capable of executing a data read operation and a write operation and a standby state holding data, and is arranged in a matrix The refresh operation period in the active state is the first period and the refresh operation period in the standby state is the second period longer than the first period, and the data held in the plurality of memory cells is refreshed. A refresh circuit for outputting a refresh command signal for commanding, and refresh execution means for executing a refresh operation in response to the refresh command signal.

  Preferably, the refresh circuit instructs to refresh after completion of the read operation or the write operation in the active state, and to refresh at a predetermined cycle in the standby state.

  Preferably, the refresh circuit has a timer circuit that outputs a cycle signal at a time interval necessary for refreshing data held in a plurality of memory cells, and an activation level of a refresh command signal in response to the cycle signal. A command signal activation circuit that outputs a refresh flag signal requesting that the refresh command signal be output, a determination circuit that outputs a determination signal that determines whether or not the refresh command signal may be at an activation level, and a refresh signal in an active state. In response to the flag signal and the determination signal, the refresh command signal is activated for the first period. In the standby state, the refresh command signal is activated for the second period in response to the refresh flag signal and the determination signal. And a logic circuit for making it into a level.

  Preferably, the logic circuit selects the first and second delay circuits having delay times corresponding to the first and second periods, respectively, and the first delay circuit in the active state and in the standby state. A selection circuit for selecting the second delay circuit, and a latch for fixing the refresh command signal to the activation level by the delay time of the delay circuit selected by the selection circuit among the first and second delay circuits Circuit.

  In the semiconductor memory device according to the present invention, the plurality of memory cells arranged in a matrix, the refresh operation period in the active state is the first period, and the refresh operation period in the standby state is the second longer than the first period. In this period, there are provided a refresh circuit for outputting a refresh command signal for instructing to refresh data held in a plurality of memory cells, and refresh execution means for executing a refresh operation in response to the refresh command signal. Therefore, the refresh operation period in the standby state is configured to be longer than the refresh operation period in the active state. As a result, the refresh operation margin in the standby state is improved, and the stability of the refresh operation is greatly improved. In addition, since the refresh operation period in the active state can be set to be short, the access speed to the memory cell can be maintained at a high speed.

  FIG. 1 is a block diagram showing an overall configuration of a semiconductor memory device according to an embodiment of the present invention. Referring to FIG. 1, semiconductor memory device (pseudo SRAM) 1 includes an input terminal group which receives chip enable signal / CE, output enable signal / OE, write enable signal / WE, and control signals / LB and / UB. 10, an input / output terminal 11 through which a data signal DQ is input / output, and an input terminal 12 through which an address signal ADD is input.

  Chip enable signal / CE is a signal for switching to either an active state in which a data read or write operation can be performed or a standby state in which data is held. Specifically, in response to the chip enable signal / CE being set to the activation level “L”, the semiconductor memory device 1 is activated, and the chip enable signal / CE is set to the inactivation level “H”. The semiconductor memory device 1 is brought into a standby state in response to being set to the "" level.

  Output enable signal / OE is a signal for setting semiconductor memory device 1 to the read operation mode and activating the input / output buffer. Write enable signal / WE is a signal for setting semiconductor memory device 1 to the write operation mode. Control signal / LB is a signal for inputting / outputting data on the lower (Lower bit) side. Control signal / UB is a signal for inputting / outputting data on the upper bit side.

  The semiconductor memory device 1 further responds to a control signal input from the input / output terminal 11 with a control clock corresponding to a predetermined operation mode of the semiconductor memory device 1 such as a write operation mode and a read operation mode for each block. And an address buffer 21 for transmitting the address signal ADD from the input terminal 12 in response to an output clock of the control circuit 20. Semiconductor memory device 1 further receives an internal address signal output from address buffer 21 in response to an output clock of control circuit 20, and receives a column decoder 22 for designating a column address and an internal address signal output from address buffer 21. A row decoder 23 which receives a response in response to an output clock of the control circuit 20 and designates a row address, a memory cell array 24 including memory cells arranged in a matrix, and an output from the memory cell array 24 are amplified to perform a read operation. Sense amplifier + input / output control circuit 25. Semiconductor memory device 1 further includes an input / output buffer 26 that receives data signal DQ from input / output terminal 11 in response to the output clock of control circuit 20 and transmits the data signal to input / output control circuit 25.

  Semiconductor memory device 1 further includes a refresh circuit 27. The refresh circuit 27 outputs a refresh command signal / REFE, which is a periodically activated signal, to the control circuit 20. Control circuit 20 receives refresh command signal / REFE and outputs an operation instruction signal for executing a refresh operation to each block.

  FIG. 2 is a circuit block diagram showing a configuration of refresh circuit 27 shown in FIG. Referring to FIG. 2, this refresh circuit 27 includes a command signal activation circuit 30, a determination circuit 31, NAND gates 32 and 35, an inverter 33, a flip-flop 36, a buffer 39, a delay circuit 34, 40, 41 and a switch circuit SW1.

  The command signal activation circuit 30 outputs a refresh flag signal Refflag requesting that the refresh command signal / REFE be set to the activation level. The determination circuit 31 outputs a determination signal Refwin that determines whether or not the refresh command signal / REFE may be set to the activation level.

  The NAND gate 32 receives the refresh flag signal Refflag and the determination signal Refwin, calculates a logical product of the refresh flag signal Refflag and the determination signal Refwin, and outputs a signal obtained by inverting the calculation result as a signal / REFSF.

  Inverter 33 receives signal / REFSF output from NAND gate 41 and outputs its inverted signal φA1. The delay circuit 34 receives the signal / REFSF, delays it for a predetermined time, and outputs it.

  NAND gate 35 receives output signal φA1 of inverter 33 and the output signal of delay circuit 34, calculates a logical product of signal φA1 and the output signal of delay circuit 34, and outputs a signal / REFS obtained by inverting the calculation result. To do.

  The flip-flop 36 includes NAND gates 37 and 38. NAND gate 37 receives signal / REFS and output signal φA3 of NAND gate 38, calculates a logical product of signal / REFS and signal φA3, and outputs signal φA2 obtained by inverting the calculation result. NAND gate 38 receives output signal φA2 of NAND gate 37 and signal φA4 from switch circuit SW1, calculates the theoretical product of signal φA2 and signal φA4, and outputs signal φA3 obtained by inverting the calculation result. Buffer 39 receives signal φA3 and outputs refresh command signal / REFE.

  The delay circuit 40 receives the refresh command signal / REFE output from the buffer 39, delays it for a predetermined time DL1, and outputs it. The delay circuit 41 receives the refresh command signal / REFE output from the buffer 39, and outputs it after delaying by a predetermined time DL2. Here, it is assumed that the delay time DL2 is longer than the delay time DL1 by a predetermined time.

  Switch circuit SW1 receives the output signals of delay circuits 40 and 41, selects one of the signals in response to internal chip enable signal int / CE, and outputs the selected signal as signal φA4. Specifically, when the internal chip enable signal int / CE is at the “L” level (active state) of the activation level, the output signal of the delay circuit 40 is selected and the internal chip enable signal int / CE is at the inactivation level. In the case of “H” level (standby state), the output signal of the delay circuit 41 is selected. The control circuit 20 generates an internal chip enable signal int / CE according to the chip enable signal / CE input from the input terminal group 10.

  With the configuration as described above, the NAND gates 32 and 35, the inverter 33, the flip-flop 36, the buffer 39, and the delay circuit 34 are equal to the delay time by the delay circuit selected by the switch circuit SW1 among the delay circuits 40 and 41. A latch circuit for fixing refresh command signal / REFE to the activation level is configured.

  FIG. 3 is a circuit block diagram showing a configuration of command signal activation circuit 30 shown in FIG. Referring to FIG. 3, command signal activating circuit 30 includes a timer circuit 50 configured by a ring oscillator and outputting periodically activated cycle signal / Refcyc, flip-flop 51, NAND gate 54, Inverters 55 and 56 and a delay circuit 57 are included.

  The flip-flop 51 includes NAND gates 52 and 53. NAND gate 52 receives cycle signal / Refcyc and output signal φA11 of NAND gate 54, calculates a logical product of cycle signal / Refcyc and signal φA11, and outputs signal φA10 obtained by inverting the calculation result. The NAND gate 53 receives the output signal φA10 of the NAND gate 52 and the output signal φA12 of the NAND gate 54, calculates a logical product of the signal φA10 and the signal φA12, and outputs a signal φA11 obtained by inverting the calculation result. To do. Inverter 55 receives signal φA11 output from flip-flop 51, and outputs the inverted signal as refresh flag signal Refflag.

  Inverter 56 inverts refresh command signal / REFE and outputs it. Delay circuit 57 receives refresh command signal / REFE inverted by inverter 56, and outputs signal φA13 obtained by delaying inverted refresh command signal / REFE for a predetermined time. NAND gate 55 receives refresh command signal / REFE and signal φA13 output from delay circuit 57, calculates the logical product of refresh command signal / REFE and signal φA13, and outputs signal φA12 obtained by inverting the calculation result. To do.

  With the configuration as described above, this command signal activation circuit 30 sets the refresh flag signal Refflag to the “H” level of the activation level for a predetermined time in response to the cycle signal / Refcyc generated by the timer circuit 30. . Specifically, in response to the cycle signal / Refcyc being set to the activation level “L” level, the refresh flag signal Refflag is set to the activation level “H” level, and then the refresh command signal / REFE is turned off. In response to the activation level being set to the “H” level, the refresh flag signal Reffflag is set to the “L” level that is the deactivation level.

  FIG. 4 is a circuit block diagram showing a configuration of determination circuit 31 shown in FIG. Referring to FIG. 4, determination circuit 31 includes an AND gate 60, an OR gate 61, an inverter 62, and a delay circuit 63.

  Inverter 62 receives internal act signal int / ACT and outputs the inverted signal. Delay circuit 63 receives the signal output from inverter 62 and outputs a signal φA21 delayed for a predetermined time. The control circuit 20 shown in FIG. 1 generates an internal act signal int / ACT according to the output enable signal / OE and the write enable signal / WE input from the input terminal group 10.

  AND gate 60 receives internal act signal int / ACT and signal φA21 output from delay circuit 63, calculates a logical product thereof, and outputs the calculation result as signal φA22. The OR gate 61 receives the signal φA22 output from the AND gate 60 and the internal chip enable signal int / CE, calculates the logical sum thereof, and outputs the calculation result as the determination signal Refwin.

  With the above-described configuration, the determination circuit 31 always outputs the determination signal Refwin at the activation level “H” when the internal chip enable signal int / CE is at the “H” level (standby state) at the inactivation level. To level. On the other hand, when the internal chip enable signal int / CE is at the activation level “L” (active state), the internal act signal int / ACT is raised to the inactivation level “H” level. Thus, the determination signal Refwin is set to the “H” level of the activation level for a predetermined time set by the delay circuit 63.

  FIG. 5 is a timing chart showing the operation of the refresh circuit 27 in the standby state. Referring to FIG. 5, when internal chip enable signal / intCE is at the “H” level of the inactivation level, semiconductor memory device 1 is in a standby state. When internal chip enable signal / intCE is at “H” level, determination circuit 31 determines that a refresh operation can be performed. In other words, determination circuit 31 determines that refresh command signal / REFE may be set to the activation level. Therefore, when the internal chip enable signal / intCE is at the “H” level of the inactivation level, the determination signal Refwin output from the determination circuit 27 is at the “H” level of the activation level.

  At time t1, when the cycle signal / Refcyc output from the timer circuit 50 is set to the “L” level of the activation level, the refresh flag signal Refflag output from the command signal activation circuit 30 is set to the “H” level of the activation level. To the level. The NAND gate 32 included in the refresh circuit 27 receives the determination signal Refwin and the refresh flag signal Refflag that are respectively set to the “H” level, and sets the signal / REFSF to the “L” level of the activation level. In response to this, NAND gate 35 outputs a signal / REFS that has been set to the “L” level of the activation level for a predetermined time set by delay circuit 34.

  Here, the switch circuit SW1 selects the output signal of the delay circuit 41 in response to the internal chip enable signal int / CE being set to the “H” level of the inactivation level, and flip-flops the signal φA4 as the signal φA4. 36.

  In response to the signal / REFS being set to the “L” level of the activation level, the flip-flop 36 receives the signal φA3 that has been set to the “L” level of the activation level for the predetermined time DL2 set by the delay circuit 41. Output. Buffer 39 receives signal φA3, and outputs refresh command signal / REFE that has been set to the activation level of “L” for a predetermined time DL2 from time t1.

  With the above operation, when the refresh flag signal Reffflag output from the command signal activation circuit 30 at the time t1 is set to the activation level “H” level, the determination circuit 31 determines that the refresh operation can be performed. ing. That is, at time t1, the determination circuit 31 sets the determination signal Refwin to the “H” level of the activation level. Therefore, when the semiconductor memory device 1 is in the standby state, the refresh operation is executed for the predetermined time DL2 set by the delay circuit 41.

  The refresh command signal / REFE output from the refresh circuit 27 is set to the inactivation level “H” level at time t2 after the predetermined time DL2 set by the delay circuit 41 has elapsed. At this time, since the signal φA12 output from the NAND gate 54 in the command signal activation circuit 30 is at “L” level, the refresh flag signal Reffflag output from the command signal activation circuit 30 is also “inactivation level”. L ”level. The refresh circuit 27 performs the refresh operation as described above every predetermined cycle T.

  FIG. 6 is a timing chart showing the operation of the refresh circuit 27 in the active state. Referring to FIG. 6, when internal chip enable signal / intCE is at the “L” level of the activation level, semiconductor memory device 1 is in an active state. At time before time t11, internal act signal int / ACT is at the “H” level of the inactivation level, and therefore signal φA22 output from AND gate 60 in determination circuit 31 is at the “L” level. . Therefore, the determination signal Refwin output from the OR gate 61 in the determination circuit 31 is set to the “L” level of the inactivation level.

  At time t11, internal act signal int / ACT is set to the “L” level of the activation level, and the read or write operation is executed. At this time, signal φA21 output from delay circuit 63 in determination circuit 31 is at the “H” level. Signal φA22 output from AND gate 60 maintains the “L” level. Therefore, the determination signal Refwin output from the OR gate 61 maintains the “L” level of the inactivation level.

  At time t12, internal act signal int / ACT is set to the “H” level of the inactivation level, and the read or write operation is completed. At this time, the signal φA21 output from the delay circuit 63 in the determination circuit 31 is maintained at the “H” level for a certain period Δt after time t12. Therefore, signal φA22 output from AND gate 60 is at the “H” level for a certain period Δt from time t12. Therefore, the determination signal Refwin output from the OR gate 61 maintains the “H” level of the activation level for a certain period Δt after time t12. With the above operation, the determination circuit 31 determines that the refresh operation can be executed in a certain period Δt after the end of the read operation or the write operation.

  However, at time t12, cycle signal / Refcyc remains at the “H” level of the inactivation level. Therefore, the refresh flag signal Refflag output from the command signal activation circuit 30 also remains at the “L” level of the inactivation level. Therefore, at time t12, refresh command signal / REFE output from refresh circuit 27 maintains the “H” level of the inactivation level.

  Subsequently, when the cycle signal / Refcyc is set to the activation level “L” at time t13, the refresh flag signal Refflag output from the command signal activation circuit 30 is set to the activation level “H”. . At this time, the determination signal Refwin output from the determination circuit 31 is the “L” level of the inactivation level. Therefore, refresh command signal / REFE output from refresh circuit 27 maintains the “H” level of the inactivation level. Further, after time t13, the refresh flag signal Refflag output from the command signal activation circuit 30 holds the “H” level of the activation level.

  Subsequently, when the read or write operation is started again at time t14 and the read or write operation is completed at time t15, the determination signal Refwin output from the determination circuit 31 at time t15 is the same as the operation at time t12. Similarly, the activation level becomes “H” level only for a certain period Δt after time t15.

  At this time, since the refresh flag signal Reffflag maintains the “H” level of the activation level, the signal / REFS output from the NAND gate 35 in the refresh circuit 27 is only for a certain time set by the delay circuit 34. The activation level becomes the “L” level.

  Here, the switch circuit SW1 selects the output signal of the delay circuit 40 in response to the internal chip enable signal int / CE being set to the “L” level of the activation level, and the flip-flop 36 is selected as the signal φA4. Output to.

  The flip-flop 36 receives the signal φA3 that has been set to the “L” level of the activation level for a predetermined time DL1 set by the delay circuit 40 in response to the signal / REFS being set to the “L” level of the activation level. Output. Buffer 39 receives signal φA3 and outputs refresh command signal / REFE that has been set to the “L” activation level for a predetermined time DL1 from time t15. Therefore, the refresh operation is executed during this period. At time t16, when refresh command signal / REFE is set to the “H” level of the inactivation level, refresh flag signal Reffflag is also set to the “L” level of the inactivation level in response thereto.

  With the above operation, the determination circuit 31 determines that the refresh operation can be executed within a certain period after the end of the read operation or the write operation. Therefore, when the determination circuit 31 determines that the refresh operation can be performed, if the refresh flag signal Reffflag is “H” level of the activation level, the refresh command signal / REFE is a predetermined value set by the delay circuit 40. The activation level is set to the “L” level only for the time DL1. Therefore, when the semiconductor memory device 1 is in the active state, the refresh operation is executed only for the predetermined time DL1 set by the delay circuit 40.

  FIG. 7 is a diagram for explaining the refresh operation period in the standby state and the active state. Referring to FIG. 7, when semiconductor memory device 1 is in a standby state, a refresh operation is executed for a predetermined time DL2 set by delay circuit 41 shown in FIG. This refresh operation is executed every predetermined period T. Further, when the semiconductor memory device 1 is in the active state, the refresh operation is executed for a predetermined time DL1 set by the delay circuit 40 shown in FIG. This refresh operation is performed after the end of the read operation or the write operation.

  In the conventional semiconductor memory device (see Patent Document 1), the delay circuit 41 and the switch circuit SW1 shown in FIG. 2 are not provided. That is, in the standby state and the active state, the refresh operation period is fixed to the predetermined time DL1 set by the delay circuit 40. In order to increase the access speed to the memory cell in the active state, the refresh operation period DL1 is set to be as short as possible. However, when the standby state is long and a voltage drop occurs due to external noise or the like, there is a problem that the stability of the refresh operation cannot be ensured.

  Therefore, in this embodiment, the delay circuit 41 and the switch circuit SW1 are provided so that the refresh operation period DL2 in the standby state is longer than the refresh operation period DL1 in the active state. As a result, the refresh operation margin in the standby state is improved, and the stability of the refresh operation is greatly improved. In addition, since the refresh operation period DL1 in the active state can be set to be short, the access speed to the memory cell can be maintained at a high speed.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a block diagram showing an overall configuration of a semiconductor memory device according to an embodiment of the present invention. FIG. 2 is a circuit block diagram illustrating a configuration of a refresh circuit illustrated in FIG. 1. FIG. 3 is a circuit block diagram showing a configuration of a command signal activation circuit shown in FIG. 2. FIG. 3 is a circuit block diagram illustrating a configuration of a determination circuit illustrated in FIG. 2. 3 is a timing chart showing the operation of the refresh circuit in a standby state. 3 is a timing chart showing the operation of the refresh circuit in an active state. It is a figure for demonstrating the refresh operation period in a standby state and an active state.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Semiconductor memory device, 10 input terminal group, 11 input / output terminal, 12 input terminal, 20 control circuit, 21 address buffer, 22 column decoder, 23 row decoder, 24 memory cell array, 25 sense amplifier + input / output control circuit, 26 input Output buffer, 30 command signal activation circuit, 31 determination circuit, 32, 35, 37, 38, 52, 53, 54 NAND gate, 33, 55, 56, 62 inverter, 36, 51 flip-flop, 39 buffer, 34, 40, 41, 57, 63 Delay circuit, 50 timer circuit, 60 AND gate, 51 OR gate, SW1 switch circuit.

Claims (4)

A semiconductor memory device having an active state capable of executing a data read operation and a write operation and a standby state for holding the data,
A plurality of memory cells arranged in a matrix,
The refresh operation period in the active state is a first period, and the refresh operation period in the standby state is a second period longer than the first period, so that data held in the plurality of memory cells is refreshed. A semiconductor memory device comprising: a refresh circuit that outputs a refresh command signal for commanding; and a refresh execution means for executing a refresh operation in response to the refresh command signal.   2. The semiconductor memory according to claim 1, wherein the refresh circuit instructs refreshing after completion of a reading operation or a writing operation in the active state, and refreshing at a predetermined cycle in the standby state. apparatus. The refresh circuit includes:
A timer circuit for outputting a cycle signal at a time interval necessary for refreshing data held in the plurality of memory cells;
A command signal activation circuit for outputting a refresh flag signal for requesting the refresh command signal to be at an activation level in response to the cycle signal;
A determination circuit for outputting a determination signal for determining whether or not the refresh command signal may be activated; and, in the active state, in response to the refresh flag signal and the determination signal, the refresh command signal A logic circuit that is activated only during the first period, and in the standby state, the refresh command signal is activated only during the second period in response to the refresh flag signal and the determination signal; The semiconductor memory device according to claim 1 or 2. The logic circuit is
First and second delay circuits each having a delay time corresponding to the first and second periods,
The first delay circuit is selected in the active state, the selection circuit that selects the second delay circuit in the standby state, and the selection circuit selected from among the first and second delay circuits. 4. The semiconductor memory device according to claim 3, further comprising a latch circuit for fixing the refresh command signal to an activation level by a delay time by the delay circuit.

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