JP2006333515A - Voltage-current conversion circuit and balanced amplifier using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit whose limit of an output signal amplitude is high under the condition of low voltage power supply, in a voltage-current conversion circuit for eliminating an in-phase component of an input voltage. <P>SOLUTION: When input voltages to voltage-current conversion circuits Gm1 and Gm2 are set to V1 and V2 and differential components of the input voltages are set to 2Vin and in-phase components of the input voltages is set to Vcm, V1=Vin+Vcm, V2=-Vin+Vcm. When potential on a line to which 4 terminals of in2 and Out2 of Gm1 and Gm2 is set to Va, an output current is represented by I1=-Gm(V1+Va), I2=-Gm(V2+Va). Since the input impedance of Gm1 and Gm2 are extremely large, the current fed back can flow into neither of reverse-phase input terminals in2 of Gm1 nor Gm2, thus, it becomes I1+I2=0. That is, feedback for offsetting the in-phase component is applied to the reverse-phase input terminals in2, the in-phase component is eliminated from the output current. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a voltage-current conversion circuit and a balanced amplifier using the same.

  A balanced amplifier that has the gain only for the differential component of the input signal and has the characteristic of removing the in-phase component can remove the noise mixed in as the in-phase component, compared to the case where the differential signal amplitude is single phase. Since it can be doubled, it is often used in analog / digital mixed integrated circuits and circuits operating at low voltage. Conventionally, a circuit for removing a common-mode component of an input voltage by combining a differential pair and a common-mode feed-back (hereinafter referred to as CMFB) circuit in order to remove the common-mode component has been proposed (for example, Patent Document 1).

  FIG. 13 is a circuit diagram of a differential pair having a conventional CMFB circuit, and a similar circuit is disclosed in Patent Document 1.

  In the differential pair of FIG. 13, the input voltages input to the input terminals 1n1 and In2 are input to the gates of the transistors M3 and M4, respectively, and the predetermined bias voltage Vbias2 is input to the gate of the transistor M5. In addition, an output terminal Out1 is provided between the transistors M1 and M3, an output terminal Out2 is provided between the transistors M2 and M4, and a CMFB circuit 121 for fixing the operating point of the output terminals Out1 and Out2 is connected to provide a feedback voltage. Vbias1 is input to transistors M1 and M2 whose gates are connected in common.

  In such a conventional circuit, there is a lower limit to the number of vertically stacked transistors because the common-phase component removal property of the differential pair is utilized, and the output signal amplitude limit when operated under low voltage conditions. There is a problem that is low.

  For example, in a semiconductor integrated circuit, an analog circuit is often created on the same chip as a digital circuit. In order to increase the degree of circuit integration, it is advantageous to operate the digital circuit and the analog circuit at the same voltage. However, if the process is further miniaturized in the future, further reduction of the power supply voltage is inevitable. For example, the operating voltage of a digital circuit in a 0.11 μm process integrated circuit, which is expected to be put into practical use in the near future, is about 1.5 V, but it is expected that the operating voltage will be further lowered if the process is further miniaturized.

The limit of the output signal amplitude is obtained for the circuit of FIG. Let Vsat be the saturation voltage of each transistor (potential difference between the drain and source of the transistor), and Vt be the threshold voltage (potential difference between the source and gate of the transistor). Since there are transistors M5, M4, and M2 (or transistors M5, M3, and M1 may be considered) between the power supply lines, the output signal amplitude limit Vmax is determined from the power supply voltage Vdd to the drain and drain of these three transistors. This is the source voltage minus Vss. Since the minimum required voltage between the drain and the source is Vsat, Vmax = Vdd− (Vsat + Vsat + Vsat) −Vss = Vdd−3Vsat−Vss.
For example, consider a case where the saturation voltage Vsat of each transistor is 0.2 V, the threshold voltage Vt is 0.5 V, and Vss = 0 V (ground). In the case of the above-mentioned 0.11 μm process, Vdd = 1.5V, so Vmax = 0.9V, but if the operating voltage is reduced to Vdd = 1.0V, it is less than half of Vdd = 1.5V. Vmax = 0.4V.

In other words, if the power supply voltage further decreases in the future, the differential pair will not be able to obtain sufficient performance, that is, sufficient output amplitude even if it is operated at the same voltage as that of the digital circuit. Even if the removal circuit is configured, it is expected that it will be difficult to obtain sufficient noise removal performance.
Japanese Patent Laid-Open No. 2000-148262 (FIG. 15)

  Since balanced amplifiers utilize the common-mode component elimination property of differential pairs, there is a lower limit on the number of transistors stacked in cascade, and there is a problem that the output signal amplitude limit is low when operated under low voltage conditions. is there.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a voltage-current converter circuit having a high output signal amplitude limit and a balanced amplifier having a high output signal amplitude upper limit even at a low voltage.

  The first aspect of the present invention is applied to the first input terminal, the second input terminal, the first output terminal, the second output terminal, and the first and second input terminals, respectively. Input addition means for adding and outputting voltage signals, and corresponding to the first and second output terminals, respectively, inverting and amplifying the output of the input addition means, and first and second inverting amplification outputs And the first and second inversion amplifying means, and the first and second inversion amplifying means provided corresponding to the first and second output terminals, respectively. The amplified outputs are inverted and amplified to generate first and second current signals, and the first and second current signals are output to the first and second output terminals, respectively. Means and a third inverting amplification means provided between the input end and the output end of the third inversion amplification means Provided by the capacitive element, the voltage-current converter comprising an input end and a second capacitive element provided between an output terminal of said fourth inverting amplifying means.

  According to a second aspect of the present invention, there is provided a balanced amplifier including a voltage-current conversion circuit according to the first aspect.

  The balanced amplifier of the present invention is composed of a voltage-current conversion circuit using a simple source-grounded amplifier circuit. As a result, the output signal amplitude limit is lower than before even in low voltage operation without losing the conventional common-mode component removal capability. It became high.

  Further, since the common-mode output voltage can be controlled by the positive-phase input terminal of the voltage-current conversion circuit used in the balanced amplifier of the present invention, the time constant can be easily controlled when a filter is configured.

  Hereinafter, a balanced amplifier and a filter using the same according to the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 shows a block diagram of a first embodiment of a balanced amplifier according to the present invention. This balanced amplifier is composed of two voltage-current conversion circuits Gm1 and Gm2 each having four terminals of negative phase input terminals in1 and in2 and positive phase output terminals out1 and out2. The positive-phase output terminal out2 and negative-phase input terminal in2 of the voltage-current converter circuit Gm1 and the positive-phase output terminal out2 and negative-phase input terminal in2 of the voltage-current converter circuit Gm2 are connected in common, and the differential input signal Is input from the negative phase input terminal in1 of the voltage current conversion circuit Gm1 and the positive phase input terminal in1 of the voltage current conversion circuit Gm2, and the differential output signal is the positive phase output terminal out1 of the voltage current conversion circuit Gm1 and the voltage current conversion circuit Gm2. Is output from both of the negative phase output terminals out1.

  The operation of the voltage / current conversion circuits Gm1 and Gm2 will be described. The voltage-current conversion circuits Gm1 and Gm2 convert the input voltages to the respective negative-phase input terminals in1 and in2 into currents and output them to both the positive-phase output terminals out1 and out2. The output from the positive phase output terminal outl depends on both the negative phase input terminals in1 and in2. Similarly, the output from the positive phase output terminal out2 depends on both the negative phase input terminals in1 and in2.

  Next, the operation of the balanced amplifier according to this embodiment will be described. In order to simplify the explanation, the currents output from the positive phase output terminals out1 and out2 of the voltage-current conversion circuits Gml and Gm2 are always equal, but in actuality, the output current from the positive phase output terminal out1 is positive. The output currents from the phase output terminal out2 need not be equal.

  If the input voltage to the voltage-current converter Gm1 is V1, the input voltage to the voltage-current converter Gm2 is V2, the differential component of the input voltage is 2Vin, and the common-mode component is Vcm, then V1 = Vin + Vcm, V2 =- Vin + Vcm. The transconductance of the voltage / current conversion circuit Gml, Gm2 is set to Gm, the output from the positive phase output terminal outl and out2 of the voltage / current conversion circuit Gm1 is 11, and the output from the positive phase output terminals outl and out2 of the voltage / current conversion circuit Gm2 Is the voltage on the line connecting the 4 terminals of in2 and out2 of the voltage-current conversion circuit Gm1, Gm2 with Va, the output current is the converted input voltage, and I1 = -Gm (V1 + Va), I2 = -Gm (V2 + Va).

  By the way, since the input impedance of the voltage-current conversion circuits Gm1, Gm2 is very large, the feedback current cannot flow into the negative-phase input terminal in2 of either of the voltage-current conversion circuits Gm1, Gm2, n + I2 = 0.

When Va, I1, and I2 are calculated from the equations I1 = -Gm (V1 + Va) and I2 = -Gm (V2 + Va), Va = -Vcm, n = -Gm · Vin, and I2 = Gm · Vin. . That is, it can be seen that feedback that cancels out the in-phase component is applied to the anti-phase input terminal in2, and the in-phase component is removed from the output current.
FIG. 8 shows a first specific configuration example of the voltage-current conversion circuits Gm1 and Gm2 used in the present embodiment. The circuit of FIG. 8 includes a power supply line having a potential Vdd, a power supply line having a potential Vss, negative phase input terminals in1 and in2, positive phase output terminals out1 and out2, current sources J1 and J2, and signals from the input terminals. N-channel transistors M1 to M4.

  The sources of the transistors M1 to M4 are connected to the power supply line of the potential Vss, the current sources J1 and J2 are connected to the power supply line of the potential Vdd, and the other end of the current source J1 and the drains of the transistors M1 and M2 are shared. A positive phase output terminal out1 is provided on the connection line. The other end of the current source J2 and the drains of the transistors M3 and M4 are connected in common, and a positive phase output terminal out2 is provided on this connection line. The gates of the transistors M1 and M3 are connected, and a reverse phase input terminal inl is provided on this connection line. The gates of the transistors M2 and M4 are connected, and a reverse phase input terminal in2 is provided on this connection line. As described above, a voltage-current conversion circuit with two inputs and two outputs is configured.

  The operation of the voltage / current converter circuit of FIG. 8 will be described. First, the output current from the positive phase output terminal outl will be described.

  A current corresponding to the input voltage to the negative phase input terminal in1 flows between the drain and source of the transistor M1, and similarly a current corresponding to the input voltage to the negative phase input terminal in2 flows between the drain and source of the transistor M2. As a result, the output current from the positive phase output terminal out1 is the current obtained by subtracting the sum of the currents corresponding to the respective input voltages to the negative phase input terminals in1 and in2 from the current supplied from the current source J1. Become. The same applies to the positive-phase output terminal out2, which is a current obtained by subtracting the sum of the currents corresponding to the respective input voltages to the negative-phase input terminals in1 and in2 from the current supplied from the current source J2.

  In the voltage-current converter circuit of FIG. 8, assuming that the saturation voltage of each transistor is Vsat and the threshold voltage is Vt, the limit Vmax of the output signal amplitude is the potential difference between both ends of the current source J1 than the operating voltage Vdd, and the drain-source of the transistor M1. This is the value obtained by subtracting the inter-voltage component and Vss. Usually, the current source J1 has a configuration in which a predetermined voltage is applied to the gate of the transistor, and in order to operate as a current source, a potential difference between both ends needs to be at least Vsat, so Vmax = Vdd-Vsat-Vsat-Vss = Vdd-2sat-Vss.

  For example, if the saturation voltage Vsat of each transistor is 0.2V, the threshold voltage Vt is 0.5V, the power supply voltage Vdd is 1.0V, and Vss is 0V (grounded), Vmax = 0.6V, and the conventional differential pair and CMFB circuit are combined. Compared with the balanced amplifier, the limit of the output signal amplitude is improved, and it is expected that sufficient performance can be exhibited even at a lower voltage than in the past.

  FIG. 9 shows a second specific configuration example of the voltage / current conversion circuits Gml and Gm2 used in the present embodiment. This circuit includes a power supply line 91 having a potential Vdd, a power supply line 92 having a potential Vss, reverse-phase input terminals in1 and in2, positive-phase output terminals out1 and out2, n-channel transistors M1 to M8, and a p-channel. Type transistors M9 to M12.

  The sources of the transistors M1 to M8 are connected to the power supply line 92, and the sources of the transistors M9 to M12 are connected to the power supply line 91. The drains of the transistors M5, M6, and Mll are connected in common, and the positive phase output terminal out1 is provided on this connection line. The drains of the transistors M7, M8, and M12 are connected in common, and the positive phase output terminal out2 is provided on this connection line. The gates of the transistors M5 and M7 are connected, and a reverse phase input terminal in1 is provided on this connection line. The gates of the transistors M6 and M8 are connected, and a reverse phase input terminal in2 is provided on this connection line.

  The gates of the transistors M1 and M3 are connected, and a positive phase input terminal in3 is provided on this connection line. The gates of the transistors M2 and M4 are connected, and a positive phase output terminal in4 is provided on this connection line.

  The gates of the transistor M11, the gate and drain of the transistor M10, and the drains of the transistors M3 and M4 are connected in common. Similarly, the gate of the transistor M12, the gate and drain of the transistor M9, and the drains of the transistors M1 and M2 are connected in common. As described above, a voltage-current conversion circuit having a negative phase two-input positive phase two-input positive phase two-output is configured.

  The operation of the voltage-current conversion circuit of FIG. 9 will be described. A current equal to the sum of currents corresponding to the input voltages to the positive phase input terminals in3 and in4 flows between the source and drain of the transistor M10. Since the transistors M10 and M11 form a current mirror, the current flowing between the source and drain of the transistor M11 is eventually controlled by the positive phase input terminals in3 and in4. Similarly, the current flowing between the source and drain of the transistor M12 is also controlled by the positive phase input terminals in3 and in4. That is, the transistors M11 and M12 are variable current sources controlled by the positive phase input terminals in3 and in4.

  9 has a configuration in which the constant current sources J1 and J2 in FIG. 8 are replaced by transistors M11 and M12 that function as variable current sources, so that the positive-phase output terminals out1 and out2 are connected. Output current is equal to the sum of the currents corresponding to the input voltages to the positive phase input terminals in3 and in4, minus the sum of the currents corresponding to the input voltages to the negative phase input terminals in1 and in2. .

  In the voltage-current conversion circuit used in the circuit of FIG. 1, the positive-phase input terminals in3 and in4 shown in FIG. 9 are shielded from the outside of the voltage-current conversion circuit after being connected to a predetermined potential point inside the voltage-current conversion circuit. In this state, the input from the outside of the voltage-current converter circuit is not received, but the configuration is not limited to this configuration, and the positive-phase input terminals in3 and in4 can receive inputs from the outside. It doesn't matter. In this case, as the voltage-current converter circuit of FIG. 1, a voltage-current converter circuit of one-stage amplification, anti-phase, two-input, positive-phase, two-input, positive-phase, and two-output is used.

  The voltage-current conversion circuit of FIG. 9 has a configuration of a common-source amplifier circuit in which the number of transistors connected in series between the power supply lines 91 and 92 is up to two. The limit is high.

  In the voltage-current converter circuit of FIG. 9, assuming that the saturation voltage of each transistor is Vsat and the threshold voltage is Vt, the output signal amplitude limit Vmax is subtracted from the drain-source voltage of transistors M8 and M12 and Vss from the operating voltage Vdd. Therefore, Vmax = Vdd-Vsat-Vsat-Vss = Vdd-2sat-Vss.

  For example, if the saturation voltage Vsat of each transistor is 0.2V, the threshold voltage Vt is 0.5V, the power supply voltage Vdd is 1.0V, and Vss is 0V (grounded), Vmax = 0.6V, and the conventional differential pair and CMFB circuit are combined. Compared with the balanced amplifier, the limit of the output signal amplitude is improved, and it is expected that sufficient performance can be exhibited even at a lower voltage than in the past.

  FIG. 10 shows a third specific configuration example of the voltage-current conversion circuits Gm1 and Gm2 used in the present embodiment. A power supply line 101 having a potential of Vdd, a power supply line 102 having a potential of Vss, reverse phase input terminals in1 and in2, n-channel transistors M1 to M6, p-channel transistors M7 to M12, and capacitors C1 and C2. Consists of positive-phase output terminals out1 and out2.

  The sources of the transistors Ml to M6 are connected to the power supply line 102, and the sources of the transistors M7 to M12 are connected to the power supply line 101. A common bias voltage is applied to the gates of the transistors M7 to M12, and the transistors M7 to M12 function as current sources.

  The entire circuit of FIG. 10 is a voltage-current conversion circuit having two negative-phase input and two positive-phase outputs. The functions are divided into two-input one-output voltage-current conversion circuit 103, one-input one-output current-voltage conversion circuit 104, one-input one-output amplifier circuit 105, and one-input two-output amplifier circuit 106. Divided.

  The two input signals input to the negative phase input terminals in1 and in2 are input to the voltage / current conversion circuit 103 having two inputs and one output, and the current / voltage conversion circuit 104 having one input and one output, and the amplifier circuit 105 having one input and one output. The final two output signals pass through the input two-output amplifier circuit and 106 in order, and are output from the positive phase output terminals outl and out2.

  The 2-input 1-output voltage-current conversion circuit 103 includes transistors M1, M2, M7, and M8. The drains of these four transistors are connected to each other and output from the line connecting the drains to the subsequent circuit.

  The 1-input 1-output current-voltage conversion circuit 104 includes transistors M3 and M9. The gate and drain of the transistor M3 and the drain of the transistor M9 are connected to each other, and an input from the preceding circuit is received on this connection line and output to the succeeding circuit.

  The 1-input 1-output amplifier circuit 105 includes transistors M4 and M10. A signal from the preceding circuit is input to the gate of the transistor M4. The transistors M4 and M10 are connected between their drains, and output from this connection line to the subsequent circuit.

  The 1-input 2-output amplifier circuit 106 includes transistors M5, M6, M11, M12, and capacitors C1, C2. The gates of the transistors M5 and M6 are connected to each other, and a signal from the previous circuit is input to this connection line. The drains of the transistors M5 and M11 are connected, and a positive phase output terminal out1 is provided on this connection line. Similarly, the drains of the transistors M6 and M12 are also connected, and a positive phase output terminal out2 is provided on this connection line. The gates and drains of the transistors M5 and M6 are connected via capacitors C1 and C2 for phase compensation.

  In the voltage-current conversion circuits Gm1 and Gm2 used in the circuit of FIG. 1, the transistors M7 to M12 of FIG. 10 are configured as constant current sources, and the gate voltages Vbias of the transistors M7 to M12 of FIG. However, the circuit is not limited to the circuit of this configuration, but has a bias circuit and positive phase input terminals in3 and in4 in addition to the circuit of FIG. 10, and these positive phase input terminals in3 and in4 are externally connected. Alternatively, a configuration may be used in which a bias circuit for receiving Vbias and controlling the bias circuit for supplying Vbias by the inputs from the positive phase input terminals in3 and in4 is used. In this case, the voltage-current converter circuit of FIG. 1 is a two-stage amplification negative-phase two-input positive-phase two-input positive-phase two-output voltage-current converter circuit.

  The voltage-current conversion circuit of FIG. 10 has a configuration of a common-source amplifier circuit in which the number of transistors stacked vertically between the power supply lines 101 and 102 is up to two. In addition to the high limit, the configuration of a two-stage amplifier is characterized in that the transconductance of the voltage-current conversion circuit can be increased.

  In the voltage-current converter circuit of FIG. 10, assuming that the saturation voltage of each transistor is Vsat and the threshold voltage is Vt, the output signal amplitude limit Vmax is the operating voltage Vdd minus the drain-source voltage of the transistors M8 and M12 and Vss. Therefore, Vmax = Vdd-Vsat-Vsat-Vss = Vdd-2sat-Vss.

  For example, if the saturation voltage Vsat of each transistor is 0.2V, the threshold voltage Vt is 0.5V, the power supply voltage Vdd is 1.0V, and Vss is 0V (grounded), Vmax = 0.6V, and the conventional differential pair and CMFB circuit are combined. Compared with the balanced amplifier, the limit of the output signal amplitude is improved, and it is expected that sufficient performance can be exhibited even at a lower voltage than in the past.

(Second Embodiment)
FIG. 2 shows a block diagram of a second embodiment of the balanced amplifier of the present invention. This balanced amplifier includes voltage-current conversion circuits Gm1 and Gm2 each having four terminals of negative-phase input terminals in1 and in2, and positive-phase output terminals out1 and out2, and a negative-phase input terminal in1 of the voltage-current conversion circuit Gm1. The impedance element 21a is connected in parallel between the positive phase output terminal out1, and the impedance element 21b is connected in parallel between the negative phase input terminal in1 and the positive phase output terminal out1 of the voltage-current conversion circuit Gm2. It is a balanced amplifier with a voltage input voltage output. The four terminals of the negative-phase input terminal in2 and the positive-phase output terminal out2 of each of the voltage-current conversion circuits Gml and Gm2 are connected to each other.

  Next, the operation of the balanced amplifier according to this embodiment will be described. In order to simplify the explanation, it is assumed that the output currents from the positive phase output terminals out1 and out2 of the voltage-current conversion circuits Gm1 and Gm2 are always equal.

  The input voltage to the voltage-current converter circuit Gm1 is V1, the input voltage to the voltage-current converter circuit Gm2 is V2, the differential component of the input voltage is 2Vin, the common-mode component is Vcm, and the transconductance of the voltage-current converter circuits Gm1 and Gm2 is Both the impedance of Gm and impedance elements 21a and 21b are Z1, the output voltage of positive-phase output terminal out1 of voltage-current converter circuit Gm1 is V3, the output voltage from positive-phase output terminal out1 of voltage-current converter circuit Gm2 is V4, and the voltage The output current from out1 and out2 of current conversion circuit Gm1 is I1, the output current from out1 and out2 of voltage current conversion circuit Gm2 is I2, and the potential of the line that connects out2 and in2 of voltage current conversion circuits Gm1 and Gm2 Let Va be.

  The voltage / current conversion circuits Gm1 and Gm2 output the input voltage converted into current, and the relationship between the input voltage and the output current is n = −Gm (V1 + Va) and I2 = −Gm (V2 + Va). By the way, since the balanced amplifier of this embodiment is normally used to output an output signal to a circuit having a high input impedance such as a buffer circuit, all the output current is fed back as long as it is used normally. Therefore, V3 = V1 + I1 · Zl and V4 = V2 + I2 · Z1. Since the current output to the positive phase output terminal out2 of the voltage / current conversion circuits Gm1 and Gm2 cannot flow to any of the negative phase input terminals in2, I1 + I2 = 0. Since V1 = Vin + Vcm and V2 = -Vin + Vcm, calculating Va, V3, V4, Va = -Vcm, V3 = Vcm-Vin-Gm ・ Z1 ・ Vin, and V4 = Vcm-Vin + Gm・ Z1 ・ Vin.

  By the way, since the differential voltage gain is usually increased (Gm · Z1 >> 1 in this embodiment), it can be expressed as V3 to Vcm−Gm · Z1 · Vin and V4 to Vcm + Gm · Z1 · Vin. That is, the input differential voltage is multiplied by Gm · Z1, and the input common-mode voltage appears at the output as it is. Since the common-mode rejection ratio (hereinafter referred to as CMRR) is defined by (differential voltage gain) / (common-mode voltage gain), the CMRR of the circuit of this embodiment is Gm · Z1, as described above. Since Gm · Z1 >> 1, a large CMRR can be obtained.

  In the present embodiment, it is conceivable to use, for example, the circuits shown in FIGS. 8 to 10 as the voltage-current conversion circuits Gm1 and Gm2. The handling of the positive-phase input terminal in the voltage-current conversion circuit of FIG. However, the present invention is not limited to this, and as the voltage-current conversion circuits Gm1 and Gm2 of the present embodiment, for example, the circuit of FIG. May be used.

  As described above, by using these voltage-current conversion circuits, there is an advantage that a high output amplitude limit can be obtained even under a low voltage operation as compared with a balanced amplifier combining a conventional differential pair and a CMFB circuit. Further, since the circuit of FIG. 10 can increase the transconductance Gm as compared with the circuits of FIGS. 8 and 9, the CMRR can be further increased as compared with the case of using the circuits of FIGS. is there.

  The advantage of this embodiment is that a CMRR having a magnitude corresponding to the gain of the amplifier can be obtained, and that a high output signal amplitude limit can be obtained even when operating at a lower voltage than in the prior art.

(Third embodiment)
FIG. 3 shows a block diagram of a third embodiment of the balanced amplifier of the present invention. The balanced amplifier includes voltage-current conversion circuits Gm1 and Gm2 each having four terminals of negative-phase input terminals in1 and in2, and positive-phase output terminals outl and out2, and a negative-phase input terminal in1 of the voltage-current conversion circuit Gm1. An impedance element 31a connected in parallel between the positive phase output terminal out1, an impedance element 31b connected in parallel between the negative phase input terminal in1 and the positive phase output terminal out1 of the voltage-current conversion circuit Gm2, A voltage input comprising an impedance element 32a having one end connected between the negative phase input terminal in1 of the voltage / current conversion circuit Gm1 and an impedance element 32b having one end connected to the negative phase input terminal in1 of the voltage / current conversion circuit Gm2. This is a balanced amplifier with voltage output. The four terminals of the negative-phase input terminal in2 and the positive-phase output terminal out2 of each of the voltage-current conversion circuits Gm1 and Gm2 are connected to each other.

  Next, the operation of the balanced amplifier according to this embodiment will be described. In order to simplify the description, the output currents from the positive phase output terminals out1 and out2 of the voltage-current conversion circuits Gm1 and Gm2 are always equal, but they may not be equal in practice.

  The input voltage to the impedance element 32a side of the balanced amplifier of this embodiment is Vl, the input voltage to the impedance element 32b side is V2, the differential component of the input voltage is 2Vin, the in-phase component is Vcm, and the voltage-current conversion The transconductance of the circuits Gm1 and Gm2 is Gm, the impedances of the impedance elements 31a and 31b are both Z1, the impedances of the impedance elements 32a and 32b are both Z2, and the output of the positive-phase output terminal outl of the voltage-current conversion circuit Gm1 The voltage is V3, the output voltage from the positive phase output terminal out1 of the voltage-current converter circuit Gm2 is V4, the output current from the voltage-current converter circuit Gml out1, out2 is I1, the output current of the voltage-current converter circuit Gm2 is out1, out2 The output current from I2 is I2, the potential on the line connecting the negative phase input terminal in1 of the voltage-current conversion circuit Gm1 and the impedance elements 31a, 32a is Va, The potential on the line connecting the negative phase input terminal in1 of the voltage-current converter circuit Gm2 and the impedance elements 31b and 32b is Vb, and the potential on the line connecting the four terminals out2 and in2 of the voltage-current converter circuits Gm1 and Gm2. Vc.

  The voltage-current converters Gm1 and Gm2 output the input voltage converted into current, and the relationship between the input voltage and the output current is I1 = −Gm (Va + Vc), I2 = −Gm (Vb + Vc). By the way, since the balanced amplifier of this embodiment is normally used to output an output signal to a circuit having a high input impedance such as a buffer circuit, all the output current is fed back as long as it is used normally. Therefore, V3 = Va + I1 · Z1 and V4 = Vb + I2 · Z1. Since the current output to the positive phase output terminal out2 of the voltage / current conversion circuits Gm1 and Gm2 cannot flow to any negative phase input terminal in2, n + I2 = 0. Since the current fed back from the positive phase output terminal out1 cannot flow into the negative phase input terminal in1 (because the impedance is very high), Va = Vl + Il · Z2 and Vb = V2 + I2 · Z2. Furthermore, since V1 = Vin + Vcm and V2 = -Vin + Vcm, calculating Va, Vb, Vc, V3, V4,

It is.

  If Gm · Z1 >> 1 and Gm · Z2 >> 1

  Therefore, it can be seen that the input differential voltage is multiplied by Z1 / Z2 but the input common-mode voltage appears at the output as it is. Therefore, the CMRR of the circuit according to the present embodiment is Z1 / Z2, and since a differential voltage gain is normally (Zl / Z2) >> 1, a large CMRR can be obtained. Further, since the differential voltage gain is determined by the magnitudes of Z1 and Z2, it is possible to keep the differential voltage gain constant even when the transconductance Gm varies due to temperature and temporal factors.

  As the voltage-current conversion circuits Gm1 and Gm2 of this embodiment, for example, the circuits shown in FIGS. 8 to 10 may be used. The handling of the positive-phase input terminal in the voltage-current converter circuit of FIG. 9 is as described above, and the positive-phase input terminal is used as a voltage-current converter circuit with two negative-phase input and two positive-phase outputs. However, the present invention is not limited to this, and the voltage-current conversion circuits Gm1 and Gm2 of the present embodiment are configured as the voltage-current conversion circuit having the above-described FIG. 9 and FIG. May be used. By using these circuits as the voltage-current converters Gm1 and Gm2, there is an advantage that the limit of the output signal amplitude is higher than that of the balanced amplifier combining the conventional differential pair and the CMFB circuit as described above.

  The advantage of this embodiment is that a CMRR having a magnitude corresponding to the gain of the amplifier can be obtained, and the CMRR can be determined by a relatively stable value of the ratio of the impedance values of the impedance elements. It is possible to obtain a high output signal amplitude even if the circuit is operated at a lower voltage than in the prior art by using the circuits of FIGS. It is in the point to become.

(Fourth embodiment)
FIG. 4 shows a block diagram of a fourth embodiment of the balanced amplifier of the present invention. This balanced amplifier includes voltage-current conversion circuits Gm1, Gm2, and Gm3 each having four terminals of negative-phase input terminals in1 and in2, positive-phase input terminals in3 and in4, and positive-phase output terminals out1 and out2. An impedance element 41a connected in parallel between the negative phase input terminal in1 and the positive phase output terminal outl of the circuit Gm1, and a parallel connection between the negative phase input terminal in1 and the positive phase output terminal out1 of the voltage-current conversion circuit Gm2. The connected impedance element 41b, the impedance element 42a having one end connected between the negative-phase input terminal in1 of the voltage-current conversion circuit Gm1 and the impedance element 41a, and the negative-phase input terminal inl of the voltage-current conversion circuit Gm2. And an impedance element 42b having one end connected between the impedance element 41b and a voltage input voltage output balanced amplifier.

  The positive-phase input terminals in3 and in4 of the voltage-current conversion circuits Gm1 and Gm2 are connected to a common potential. The four terminals of the negative-phase input terminal in2 and the positive-phase output terminal out2 of each of the voltage-current conversion circuits Gm1 and Gm2 are connected to each other. The negative-phase input terminal in1 and the positive-phase input terminal out1 of the voltage-current converter circuit Gm3 are connected to the negative-phase input terminal inl of the voltage-current converter circuit Gm1, and the negative-phase input terminal in2 and the positive-phase input terminal out2 of the voltage-current converter circuit Gm3. Is connected to the negative phase input terminal in1 of the voltage / current converter circuit Gm2, and the positive phase input terminals in3 and in4 of the voltage / current converter circuit Gm3 are connected to a common potential.

  Next, the operation of the balanced amplifier according to this embodiment will be described. In order to simplify the description, it is assumed that the output currents from the positive phase output terminals out1 and out2 of the voltage / current conversion circuit Gm1 are always equal. The same applies to the voltage / current conversion circuits Gm2 and Gm3, but the voltage / current conversion circuits Gm1 and Gm2 may not be equal.

  In the balanced amplifier of the present invention, the input voltage to the impedance element 42a side is V1, the input voltage to the impedance element 42a side is V2, the differential component of the input voltage is 2Vin, and the in-phase component is Vcm. The transconductance of Gm1 and Gm2 is Gma, the transconductance of the voltage-current conversion circuit Gm3 is Gmb, the impedances of the impedance elements 41a and 41b are both Z1, the impedances of the impedance elements 42a and 42b are both Z2, and the voltage current The output voltage from the positive phase output terminal out1 of the conversion circuit Gm1 is V3, the output voltage from the positive phase output terminal out1 of the voltage / current conversion circuit Gm2 is V4, and the output current from the out1 and out2 of the voltage / current conversion circuit Gm1 is I1 The output current from out1, out2 of the voltage-current converter circuit Gm2 is I2, the output current from out1, out2 of the voltage-current converter circuit Gm3 is I3, The potential of the negative phase input terminal in1 of the current conversion circuit Gm1 is Va, the potential of the negative phase input terminal in1 of the voltage / current conversion circuit Gm2 is Vb, and the negative phase input of each of the voltage / current conversion circuit Gm1 and the voltage / current conversion circuit Gm2 The potential of the terminal in2 is Vc, the reference voltage input to the positive-phase input terminals in3 and in4 of the voltage-current conversion circuits Gm1 and Gm2 is Vref1, and the positive-phase input terminals in3 and in4 of the voltage-current conversion circuit Gm3 The reference voltage is Vref2.

  The voltage-current converters Gm1, Gm2, and Gm3 output the input voltage converted to current, and the relationship between the input voltage and the output voltage is I1 = Gma (2Vref1-Va-Vc), I2 = Gma (2Vref1-Vb-Vc ), And I3 = Gmb (2Vref2-Va-Vb).

  By the way, since the balanced amplifier of this embodiment normally outputs an output signal to a circuit having a high input impedance such as a buffer circuit, all the output current is fed back as long as it is used normally. Therefore, V3 = Va + I1 · Z1 and V4 = Vb + I2 · Z1. Since the current output to the positive phase output terminal out2 of the voltage / current conversion circuits Gm1 and Gm2 cannot flow to any of the negative phase input terminals in2, I1 + I2 = 0. Since the negative-phase input terminals in1 and in2 of the voltage-current conversion circuit Gm3 have high impedance, current cannot flow, so Va = V1 + (I1 + I3) Z2 and Vb = V2 + (I2 + I3) Z2. The differential input signals of the balanced amplifier of this embodiment are expressed as V1 = Vin + Vcm and V2 = −Vin + Vcm.

  From the above, Va, Vb, Vc, V3, V4 are calculated.

It is.

  Here, if you ignore the minute terms as Gma ・ Z1 >> 1, Gmb ・ Z1 >> 1, Gma ・ Z2 >> 1, Gmb ・ Z2 >> 1,

It becomes.

In other words, the differential gain is Z1 / Z2 times and is determined by the impedance element and is not affected by fluctuations in transconductance Gm, and the common-mode output voltage is input to the positive-phase input terminals in3 and in4 of the voltage-current converter circuit Gm3. Since it becomes equal to the reference voltage Vref2, it can be seen that the input voltage Vref to the positive phase input terminals in3 and in4 of the voltage-current conversion circuit Gm3 is a bias voltage for controlling the common-mode output voltage. For example, if Vref2 is 0.7V, the in-phase component of the output voltage is also 0.7V.
Here, if Vref1 = Vref2 = Vref, Va = Vb = Vc = Vref, so the input voltages of all voltage-current conversion circuits are equal, so the input terminals in1, in2, in3, In4 can be regarded as a virtual short. As a result, each of the voltage / current conversion circuits Gml, Gm2, and Gm3 can be configured such that a transistor that receives an input signal has a narrow linear input range.

  The circuit of FIG. 9 can be used as the voltage-current conversion circuits Gm1, Gm2, and Gm3 in the present embodiment. Further, the voltage-current conversion circuit of FIG. 10 is configured by adding a circuit capable of controlling the bias voltage applied to the transistors M7 to M12 by the input voltage to the positive-phase input terminals in3 and in4. The current conversion circuits Gm1 to Gm3 may be used.

  The advantage of this embodiment is that the differential gain can be determined by a relatively stable value of the ratio of impedance values, and the operating point of the output voltage can be determined by the voltage input from the outside to the positive phase input terminal, A high output signal amplitude can be obtained even when operated at a lower voltage than in the prior art.

(Fifth embodiment)
FIG. 5 shows a block diagram of a fifth embodiment of the balanced amplifier of the present invention. Note that description of parts common to the fourth embodiment is omitted.

  The balanced amplifier of this embodiment has a configuration using single-phase input single-phase output voltage / current conversion circuits Gm4 and Gm5 instead of the impedance elements 42a and 42b in the fourth embodiment. The balanced amplifier according to the present embodiment includes voltage-current conversion circuits Gm1, Gm2, and Gm3 each having four terminals of negative phase input terminals in1 and in2, positive phase input terminals in3 and in4, and positive phase output terminals out1 and out2. The impedance element 51a connected in parallel between the negative phase input terminal in1 and the positive phase output terminal outl of the voltage-current conversion circuit Gml, and between the negative phase input terminal in1 and the positive phase output terminal out1 of the voltage-current conversion circuit Gm2. Is a balanced amplifier of voltage input voltage output comprising an impedance element 51b connected in parallel to each other and single phase input single phase output voltage current conversion circuits Gm4 and Gm5.

  The positive-phase input terminals in3 and in4 of the voltage-current conversion circuits Gm1, Gm2, and Gm3 are connected to a common potential. The output terminal of the single-phase input single-phase output voltage-current converter circuit Gm4 is connected at one end to the negative-phase input terminal in1 of the voltage-current converter circuit Gml, and the output terminal of the single-phase input single-phase output voltage-current converter circuit Gm5 is One end of the voltage-current conversion circuit Gm2 is connected to the negative phase input terminal in1. The four terminals of the negative-phase input terminal in2 and the positive-phase output terminal out2 of each of the voltage-current conversion circuits Gm1 and Gm2 are connected in common. In the voltage-current converter circuit Gm3, the negative-phase input terminal in1 and the positive-phase input terminal out1 are connected to the negative-phase input terminal in1 of the voltage-current converter circuit Gm1, and the negative-phase input terminal in2 and the positive-phase input terminal out2 are voltage-current converters. It is connected to the negative phase input terminal in1 of the circuit Gm2. The positive phase input terminals in3 and in4 of each of the voltage / current conversion circuits Gm1, Gm2, and Gm3 are connected to a common potential.

  Next, the operation of the balanced amplifier according to this embodiment will be described. In order to simplify the description, it is assumed that the output currents from the positive phase output terminals out1 and out2 of the voltage-current conversion circuits Gm1, Gm2, and Gm3 are always equal.

  In the balanced amplifier of the present invention, the input voltage to the input terminal of the single-phase input single-phase output voltage current conversion circuit Gm4 is V1, and the input voltage to the input terminal of the single-phase input single-phase output voltage current conversion circuit Gm5 is V2. The differential component of the input voltage is 2Vin, the in-phase component is Vcm, the transconductance of the voltage-current conversion circuit Gm1, Gm2 is Gma, the transconductance of the voltage-current conversion circuit Gm3 is Gmb, and the single-phase input single-phase output Both the transconductances of the voltage-current converters Gm4 and Gm5 are Gmc, the impedances of the impedance elements 51a and 51b are both Z1, the output voltage of the positive-phase output terminal out1 of the voltage-current converter Gm1 is V3, and the voltage-current converter The output voltage from the positive phase output terminal out1 of the circuit Gm2 is V4, the output current from the voltage current conversion circuit Gml out1, the output current from out2 is I1, the output current from the voltage current conversion circuit Gm2 out1, out2 is I2, The output current from out1 and out2 of the voltage-current converter circuit Gm3 is I3, the potential of the negative-phase input terminal in1 of the voltage-current converter circuit Gm1 is Va, and the potential of the negative-phase input terminal in1 of the voltage-current converter circuit Gm2 is Vb , The voltage of the negative-phase input terminal in2 of each of the voltage-current conversion circuit Gml and the voltage-current conversion circuit Gm2 is Vc, the bias voltage input to the positive-phase input terminals in3, in4 of the voltage-current conversion circuits Gml, Gm2, Gm3 Is Vref.

  The voltage-current converters Gm1, Gm2, and Gm3 output the input voltage converted to current, and the relationship between input voltage and output current is I1 = Gma (2Vref-Va-Vc), I2 = Gma (2Vref-Vb-Vc ), I3 = Gmb (2Vref-Va-Vb).

  By the way, since the balanced amplifier of this embodiment is normally used to output an output signal to a circuit having a high input impedance such as a buffer circuit, all the output current is fed back as long as it is used normally. Therefore, V3 = Va + I1 · Z1 and V4 = Vb + I2 · Z1. Since the current output to the positive phase output terminal out2 of the voltage / current conversion circuits Gm1 and Gm2 cannot flow to any of the negative phase input terminals in2, Il + I2 = 0. Since the impedance of the negative phase input terminals in1 and in2 of the voltage-current converter Gm1, Gm2, and Gm3 is high, current cannot flow, so I1 + I3 + Gmc ・ V1 = 0, I2 + I3 + Gmc ・ V2 = 0 is there. The differential input signals of the balanced amplifier of this embodiment are expressed as V1 = Vin + Vcm and V2 = −Vin + Vcm.

  From the above, calculating V3 and V4

It is. At this time, ignoring the minute terms as Gma · Z1 >> 1 and Gmb · Z1 >> 1

  It becomes. As a result, the CMRR becomes 2 Gmb · Z1, and a large CMRR can be obtained. It can also be seen that in this embodiment, Vref is a bias voltage for controlling the common-mode output voltage.

  As the single-phase input single-phase output voltage-current conversion circuits Gm4 and Gm5 of this embodiment, for example, a source-grounded transistor circuit as shown in FIG. 7 can be used, which can be configured with a very simple circuit.

  For example, the circuit of FIG. 9 can be used as the voltage-current conversion circuits Gm1, Gm2, and Gm3 in the present embodiment. Further, the voltage-current conversion circuit of FIG. 10 is configured by adding a circuit capable of controlling the bias voltage applied to the transistors M7 to M12 by the input voltage to the positive-phase input terminals in3 and in4. The current conversion circuits Gm1 to Gm3 may be used.

  As will be described later, the advantage of this embodiment is that when the filter is configured using this balanced amplifier, the value of Gmc can be varied, for example, by changing the in-phase component Vcm of the input voltage, thereby changing the frequency characteristics of the filter. It is easy to control. In order to change the common-mode component Vcm of the input voltage, for example, another balanced amplifier of this embodiment is connected to the previous stage of the balanced amplifier of this embodiment, and the bias voltage applied to the previous balanced amplifier is changed. . Then, since the common-mode output voltage Vcm from the previous stage also changes, the common-mode input voltage Vcm of the subsequent-stage balanced amplifier changes, and the Gmc value of the subsequent-stage balanced amplifier changes.

(Sixth embodiment)
FIG. 6 shows a block diagram of a sixth embodiment of the balanced amplifier of the present invention. Note that description of parts common to the fifth embodiment is omitted.

  The balanced amplifier according to the present embodiment is obtained by increasing the number of single-phase input and single-phase output voltage / current conversion circuits Gm4 and Gm5 in the balanced amplifier according to the fifth embodiment to three to provide six inputs. . The balanced amplifier according to the present embodiment includes voltage-current conversion circuits Gm1, Gm2, and Gm3 each having four terminals of negative phase input terminals inl and in2, positive phase input terminals in3 and in4, and positive phase output terminals out1 and out2. The impedance element 61a connected in parallel between the negative phase input terminal in1 and the positive phase output terminal out1 of the voltage current conversion circuit Gm1, and between the negative phase input terminal inl and the positive phase output terminal outl of the voltage current conversion circuit Gm2. Is a balanced amplifier of voltage input voltage output comprising an impedance element 61b connected in parallel to each other and single phase input single phase output voltage current conversion circuits Gm4 to Gm9.

  The positive-phase input terminals in3 and in4 of the voltage-current conversion circuits Gm1, Gm2, and Gm3 are connected to a common potential. The output terminal of the single-phase input single-phase output voltage-current converter circuit Gm4, Gm5, Gm6 is connected to the negative-phase input terminal in1 of the voltage-current converter circuit Gm1, the single-phase input single-phase output voltage-current converter circuit Gm7, Gm8 , Gm9 has an output terminal connected to the negative phase input terminal in1 of the voltage-current converter circuit Gm2. The four terminals of the negative-phase input terminal in2 and the positive-phase output terminal out2 of each of the voltage-current conversion circuits Gm1 and Gm2 are connected in common. In the voltage-current converter circuit Gm3, the negative-phase input terminal in1 and the positive-phase input terminal out1 are connected to the negative-phase input terminal in1 of the voltage-current converter circuit Gm1, and the negative-phase input terminal in2 and the positive-phase input terminal out2 are voltage-current converters. It is connected to the negative phase input terminal in1 of the circuit Gm2. The positive phase input terminals in3 and in4 of each of the voltage / current conversion circuits Gm1, Gm2, and Gm3 are connected to a common potential. The transconductances of the single-phase input single-phase output voltage current conversion circuits Gm4 to Gm9 are all equal.

  Next, the operation of the balanced amplifier according to this embodiment will be described. Description of operations common to the balanced amplifier of the fifth embodiment is omitted.

  In the voltage-current converter circuit of this embodiment, the first differential input signal is applied to the input voltages Vla, Vlb of the single-phase input single-phase output voltage-current converter circuits Gm4, Gm7, and the single-phase input single-phase output voltage-current converter circuit Gm5. The second differential input signal is input to the input voltages V2a and V2b of Gm8, and the third differential input signal is input to the input voltages V3a and V3b of the single-phase input single-phase output voltage / current conversion circuits Gm6 and Gm9. That is, the sum of three differential input signals can be taken, and the same operation as the circuit of the fifth embodiment is performed except that the sum of the three differential input signals is taken. A differential output signal corresponding to the sum of the input signals is output.

  In this embodiment, three differential input signals are accepted. However, as in this embodiment, by increasing the number of single-phase input single-phase output voltage-current converter circuits, a more multi-input configuration can be easily realized. it can.

  Further, here, in order to simplify the explanation, the transconductances of the single-phase input single-phase output voltage-current conversion circuits Gm4 to Gm9 are all equal, but this is not limited in application. For example, if the transconductance of the single-phase input single-phase output voltage / current conversion circuits Gm4 and Gm7 for inputting the first differential input signal is made higher than the others, the differential component of the first differential input signal is reduced. It is only possible to increase the gain relatively higher than the differential components of other differential input signals.

  Furthermore, in the present embodiment, the number of single-phase input single-phase output voltage-current conversion circuits connected to each of the voltage-current conversion circuits Gml and Gm2 is made equal, but the number need not necessarily be equal.

  The configuration using the impedance elements 42a and 42b (see FIG. 4) of the fourth embodiment is different from the configuration using the single-phase input single-phase output voltage current conversion circuits Gm4 and Gm5 in the fifth embodiment. As described above, an impedance element may be used instead of the single-phase input single-phase output voltage-current conversion circuits Gm4 to Gm9 in the present embodiment. In this case, similar to the above-described transconductance, the impedances of the impedance elements may not be equal.

  The advantage of this embodiment is that, in addition to the advantage of the fifth embodiment, a multi-input type balanced amplifier can be provided.

(Seventh embodiment)
FIG. 11 shows a block diagram of an embodiment in which the balanced amplifier of the present invention is applied to a filter.

  The filter according to the present embodiment is a fifth-order leapfrog filter, and includes multi-input integrators 11 to 15. These multi-input integrators 11 to 15 can be realized by configuring the impedance elements 61a and 61b (see FIG. 6) of the balanced amplifier according to the sixth embodiment of the present invention using capacitors. As in this embodiment, even when a multi-input integrator is required, a balanced amplifier according to the present invention can be applied to operate at a low voltage and a filter with a high output signal amplitude can be realized.

  Since the circuit of FIG. 6 is used for the integrators 11 to 15 in this embodiment, the value of the transconductor Gmc of the single-phase input single-phase output voltage current conversion circuit of FIG. 6 is changed by changing the common-mode voltage of the input signal. Can be changed. In addition, since the time constant, that is, the frequency characteristic of the filter circuit of the present embodiment changes according to the value of Gmc, the frequency characteristic of the filter can be changed by changing the in-phase component of the input signal.

  As described above, the in-phase component of the output voltage of the balanced amplifier (FIG. 6) used in the integrators 11 to 15 is the input voltage to all the positive phase input terminals in3 and in4 of the voltage-current conversion circuits Gm1 to Gm3. Since it is determined by Vref (approximately equal to Vref), changing the value of Vref will change the output common mode voltage. Since the integrators 11 to 15 have their outputs and inputs connected to each other, increasing Vref increases the input common-mode voltage and increases the value of Gmc. As a result, the time constant of the filter circuit of FIG. 11 also changes. If Vref is changed in the entire circuit, it is possible to change frequency characteristics such as a cutoff frequency.

  In this embodiment, an LPF (Low Pass Filter) is assumed. However, the filter circuit using the balanced amplifier of the present invention is not limited to this, and an HPF (High Pass Filter) or BPF can be obtained by changing the configuration of the filter circuit. (Band Pass Filter) can be created.

  The filter of the present embodiment employs a leap frog configuration, but the filter circuit using the balanced amplifier of the present invention is not limited to this. In addition, regarding the characteristics of the filter, for example, by changing the characteristics of the integrator used in this embodiment, a circuit having various characteristics such as Butterworth, Chebyshev, and Bessel can be configured.

(Eighth embodiment)
FIG. 12 is a block diagram of a voltage-current converter circuit according to the eighth embodiment of the present invention. This voltage-current conversion circuit includes an input addition stage 201, a pair of first-stage inverting amplification stages AMP1-1 and AMP1-2, and a pair of second-stage inverting amplification stages AMP2-1 and AMP2-2. . The inverting input terminal of the input addition stage 201 is connected to the input terminals in1 and in2. The output terminal of the input adding stage 201 is connected to the inverting input terminals of the first inverting amplification stages AMP1-1 and AMP1-2. The non-inverting output terminals of the first inverting amplification stages AMP1-1 and AMP1-2 are respectively connected to the inverting input terminals of the second inverting amplification stages AMP2-1 and AMP2-2 via the internal terminals n1-1 and nl-2. Connected. The non-inverting output terminals of the second inverting amplification stages AMP2-1 and AMP2-2 are connected to output terminals out1 and out2, respectively. A capacitor C1 is connected between the inverting input terminal and the non-inverting output terminal of the second inverting amplification stage AMP2-1. Similarly, the inverting input terminal and the non-inverting output terminal of the second inverting amplification stage AMP2-2 are connected to each other. A capacitor C2 is connected between the two.

  In the voltage-current conversion circuit having the above configuration, the signals input to the input terminals inl and in2 are added and inverted by the input addition stage 201, and further, the first-stage inversion provided separately for the two output terminals outl and out2 Amplified by the amplification stages AMP1-1 and AMPL-2 and the second inversion amplification stages AMP2-1 and AMP2-2.

  By providing two first and second inversion amplification stages corresponding to the output terminals outl and out2, respectively, as in this embodiment, the internal terminals n1-1 and nl-2 do not interfere with each other. That is, the internal terminal nl-1 between the first inverting amplification stage AMPL-1 and the second inverting amplification stage AMP2-1 is connected to the first inverting amplification stage AMPL-2 and the second inverting amplification stage AMP2-2. Does not interfere with the internal terminal nl-2 between. Therefore, the output fluctuation at the internal terminal n1-1 does not affect the internal terminal n1-2.

If a balanced amplifier is configured using the voltage-current converter circuit according to the present embodiment, even if the phase compensation capacitor C2 is sufficiently large to ensure sufficient stability for the common-mode component, the effect on the differential component is not affected. Therefore, a stable balanced amplifier can be realized.
As shown in FIG. 10, the input addition stage 201, the first inversion amplification stages AMP1-1 and AMP1-2, and the second inversion amplification stages AMP2-1 and AMP2-2 are connected between power supply lines ( A circuit composed of up to two transistors connected in series between the power supply voltage Vdd and the power supply voltage Vss may be used.

  A correspondence relationship between the voltage-current conversion circuit of FIG. 12 and the circuit of the voltage-current conversion circuit of FIG. 10 will be described. The input addition stage 201 in FIG. 12 corresponds to the voltage-current conversion circuits 103 and 104 in FIG. 10, and the inverting amplification stages AMP1-1 and AMP1-2 in FIG. 12 correspond to the amplification circuit 105 in FIG. The amplification stages AMP2-1 and AMP2-2 correspond to n-channel transistors M5 and M11. That is, the input adding stage 201 is constituted by two pairs of transistors M1, M7 and M2, M8 connected in series and a pair of transistors M3.M9 shown in FIG. Each of the inverting amplification stages AMP1-1 and AMP1-2 includes a pair of transistors M4 and M10 connected in series as shown in FIG. The inverting amplification stage AMP2-1 is constituted by a pair of transistors M5 and M11 connected in series, and the inverting amplification stage AMP2-2 is constituted by a pair of transistors M6 and M12 connected in series.

  The voltage-current conversion circuit shown in FIG. 12 can be applied to the balanced amplifier shown in FIG. That is, this current-voltage conversion circuit can be applied to the voltage-current conversion circuits Gm1 and Gm2 shown in FIG.

1 is a block diagram of a balanced amplifier according to a first embodiment of the present invention. The block diagram of the balanced amplifier which concerns on the 2nd Embodiment of this invention. The block diagram of the balanced amplifier which concerns on the 3rd Embodiment of this invention. The block diagram of the balanced amplifier which concerns on the 4th Embodiment of this invention. The block diagram of the balanced amplifier which concerns on the 5th Embodiment of this invention. The block diagram of the balanced amplifier which concerns on the 6th Embodiment of this invention. FIG. 6 is a circuit diagram showing an example of a single-phase input single-phase output voltage-current conversion circuit in FIG. 5. FIG. 7 is a circuit diagram showing an example of a specific configuration of a voltage / current conversion circuit when a source-grounded single-stage amplifier is used for the voltage / current conversion circuits Gm1 to Gm3 in FIGS. FIG. 7 is a circuit diagram showing an example of a specific configuration of a voltage / current conversion circuit when a source-grounded single-stage amplifier is used for the voltage / current conversion circuits Gm1 to Gm3 in FIGS. FIG. 7 is a circuit diagram showing an example of a specific configuration of a voltage / current conversion circuit when a source-grounded two-stage amplifier is used for the voltage / current conversion circuits Gm1 to Gm3 in FIGS. FIG. 10 is a block diagram of a fifth-order leapfrog filter to which a balanced amplifier according to the present invention is applied according to a seventh embodiment of the present invention. The block diagram of the balanced amplifier which concerns on the 8th Embodiment of this invention. The circuit diagram which shows an example of the balanced amplifier which combined the conventional differential pair and CMFB circuit.

Explanation of symbols

  Gm1, Gm2 ... Voltage-current converter with two negative-phase input terminals and two positive-phase output terminals, in1, in2 ... Negative-phase input terminal of voltage-current converter, out1, out2 ... Positive-phase output of voltage-current converter Terminal, V1, V2 ... Differential input signal (voltage), I1, I2 ... Differential output signal (current), 21a, 21b ... Impedance element, 31a, 31b, 32a, 32b ... Impedance element, 41a, 41b, 42a, 42b ... impedance element, 51a, 51b ... impedance element, 61a, 61b ... impedance element, 81 ... power supply line of potential Vdd, 82 ... power supply line of potential Vss, 91 ... power supply line of potential Vdd, 92 ... power supply line of potential Vss DESCRIPTION OF SYMBOLS 101 ... Power supply line of potential Vdd, 102 ... Power supply line of potential Vss, 103 ... Two-input / one-output voltage / current conversion circuit, 104 ... One-input / one-output current / voltage conversion circuit, 105 ... One-input / one-output amplification circuit 106 ... 1 Input 2 Output amplifier circuit, 121 ... CMFB circuit

Claims (3)

  A voltage signal applied to each of the first input terminal, the second input terminal, the first output terminal, the second output terminal, and the first and second input terminals is added and output. First and second, which are provided corresponding to input addition means and the first and second output terminals, respectively, and invert and amplify the output of the input addition means to generate first and second inverted amplification outputs. And the first and second output terminals of the first and second inverting amplifiers for inverting and amplifying the first and second inverting amplifier outputs, respectively. Third and fourth inversion amplifying means for generating first and second current signals and outputting the first and second current signals to the first and second output terminals, respectively; and the third inversion A first capacitive element provided between an input end and an output end of the amplifying means; Voltage-current converting circuit and a second capacitive element provided between the input and the output of the fourth inverting amplifying means.   Each of the adding means, the first inverting amplification means, the second inverting amplification means, the third inverting amplification means, and the fourth inverting amplification means is between a first power supply and a second power supply. The voltage-current converter circuit according to claim 1, comprising two transistors connected in series to each other.   Each of the first and second voltage / current conversion circuits is constituted by the voltage / current conversion circuit according to claim 1, and the second input terminal and the second output terminal of the first voltage / current conversion circuit, A total of four terminals, a second input terminal and a second output terminal of the second voltage-current conversion circuit, are connected in common, and a differential input signal is connected to the first input terminal of the first voltage-current conversion circuit. The differential output signal is input from the first output terminal of the first voltage-current conversion circuit and the first output terminal of the second voltage-current conversion circuit. A balanced amplifier characterized by output.

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