JP2006174033A - Calculation amplifier circuit, sample-hold circuit, and filter circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a calculation amplifier circuit capable of reducing a common-mode gain and power consumption. <P>SOLUTION: Variable current sources M2, M4 are provided to the common emitter of a differential amplifier 11. Output is directly fed back to each of the control terminals of the variable current sources. A new circuit is not required since common-mode feedback can be formed by the feedback. Consequently, a common-mode feedback circuit with less power consumption can be constituted. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an operational amplifier, and more particularly to an operational amplifier circuit that is effective in reducing power consumption.

  A differential circuit is used because of the demand for low voltage driving. In this type of circuit, noise or the like is carried on the signal as an in-phase component, so it is desirable to keep the in-phase gain low in order to improve the characteristics.

  A circuit shown in FIG. 11 is known as an operational amplifier circuit with a reduced common-mode gain. That is, the transistors M35 and M36 for inputting the output voltages of the output terminal Out + and the output terminal Out− are connected between the sources of the transistors M51 and M52 constituting the current source and the power source Vss, and the transistors M35 and M36 are linearly connected. A configuration is known in which a current corresponding to the common-mode voltage of the output terminals Out + and Out− is generated and fed back by operating in a region and connecting drains in common (see Non-Patent Document 1 and Patent Document 1).

However, in this operational amplifier circuit, a differential input circuit composed of transistors M31 and M32 and a current source I31 is provided as an input part separately from the output part, so that the current source circuit composed of transistors M41 and M42 is provided. In each case, it was necessary to pass a current more than twice that of the current source I31. For this reason, there exists a problem that power consumption will become large.
Tat. C. Choi, RT Kaneshiro, RW Brodersen, PR Gray, WB Jett, M. Wilcox, “High-Frequency CMOS Switched-Capacitor Filters for Communications application,” IEEE Journal of Solid-State Circuits, Vol. SC-18, No. 6, pp.652-664, December, 1983

JP 2002-163894A (FIGS. 8 and 11)

  As described above, the operational amplifier circuit having the conventional common-mode feedback circuit has a problem that power consumption increases.

  The present invention has been made in view of the problems of the conventional operational amplifier as described above, and provides an operational amplifier circuit capable of reducing the common-mode gain and reducing the power consumption by the common-mode feedback circuit. With the goal.

  According to the first aspect of the present invention, the first transistor having the first input terminal connected to the gate and the first output terminal connected to the drain, and the drain connected to the source of the first transistor. A second transistor whose source is connected to the first power source, a first current source circuit connected between the drain of the first transistor and the second power source, and a second input terminal as the gate A third transistor having a second output terminal connected to the drain; a fourth transistor having a drain connected to the source of the third transistor and a source connected to the first power supply; A second current source circuit connected between the drain of the second transistor and a second power source, and the sources of the first transistor and the third transistor are connected in common, Serial first output terminal connected to a gate of said second transistor, said second output terminal to provide an operational amplifier circuit, characterized by comprising connected to the gate of said fourth transistor.

  According to such an operational amplifier circuit, there is an effect that the power consumption can be halved as compared with the conventional configuration in which the input unit and the output unit are separated. At this time, the voltage-current conversion gain (transconductance) for the differential signal of the input circuit composed of the first, second, third, and fourth transistors is larger than the voltage-current conversion gain (transconductance) for the in-phase signal. In addition, there is an effect that the common-mode gain of the operational amplifier circuit can be significantly reduced from the differential gain by the common-mode feedback circuit in the second transistor and the fourth transistor.

  According to the second aspect of the present invention, the first input terminal is connected to the gate, the drain is connected to the source of the first transistor, and the source is connected to the first power source. A second transistor; a fifth transistor having a drain connected to the source and a drain connected to the first output terminal; and a drain between the fifth transistor and the second power source. A first current source circuit connected to the first transistor, a third transistor having a second input terminal connected to the gate, a drain connected to the source of the third transistor, and the source connected to the first power source A fourth transistor connected; a sixth transistor having a drain connected to the source; the drain connected to the second output terminal; and the sixth transistor. And a second current circuit connected between the drain of the star and the second power supply, and the sources of the first transistor and the third transistor are connected in common, and the first output There is provided an operational amplifier circuit characterized in that a terminal is connected to the gate of the second transistor and the second output terminal is connected to the gate of the fourth transistor.

  According to such an operational amplifier circuit, there is an advantage that an operational amplifier circuit having a higher gain than that of the operational amplifier circuit according to claim 1 can be obtained.

  According to claim 3 of the present invention, in the operational amplifier circuit according to claim 1 or 2, the first input terminal is connected to a gate, and a source and a drain are connected to a source and a drain of the second transistor, respectively. And an eighth transistor having the second input terminal connected to the gate and the source and drain connected to the source and drain of the fourth transistor, respectively. It is characterized by.

  According to such an operational amplifier circuit, the seventh and eighth drain-source voltages are determined so that the seventh and eighth transistors operate in the linear region. Since the drain-source voltages of the second and fifth transistors are equal to the seventh and eighth drain-source voltages, there is an advantage that the second and fourth transistors can be easily operated in the linear region. is there.

  According to claim 4 of the present invention, it is possible to provide a sample hold circuit characterized by using the operational amplifier circuit according to claim 1 or claim 2.

  According to such a sample hold circuit, a low power consumption sample hold circuit can be obtained.

  According to claim 5 of the present invention, it is possible to provide a filter circuit characterized by using the operational amplifier circuit according to claim 1 or 2.

  According to such a filter circuit, a filter circuit with low power consumption can be obtained.

  According to the present invention, it is possible to obtain an operational amplifier circuit that can reduce the common-mode gain and reduce the power consumption by the common-mode feedback circuit.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<First Embodiment>
FIG. 1 is a diagram showing a configuration of an operational amplifier circuit according to a first embodiment of the present invention. An input signal voltage is applied to the input terminals In + and In−. The NMOS transistors M1, M2, M3, and M4 constitute the input unit 11 of this operational amplifier circuit. The gate terminal of the transistor M1 is connected to the input terminal In +, and the gate terminal of the transistor M3 is connected to the input terminal In−.

  The sources of the transistors M1 and M3 are connected in common, and are also connected in common to the drains of the transistors M2 and M4. The sources of the transistors M2 and M4 are connected to the power supply Vss. The drains of the transistors M1 and M2 serving as outputs of the input unit are connected to output terminals Out− and Out +, respectively. A bias voltage Vc1 is applied to the gates of the PMOS type transistors M11 and M12. Each of the current source circuits 12 is configured (hereinafter collectively referred to as a current source circuit), and the output terminals Out− and Out + are connected to the power source Vdd. Connected between.

  In FIG. 1, the line from the voltage Vc1 passes through the transistor M12 of the current source circuit 12 and is connected to the gate of the transistor M11. This is because the gates of the transistors M11 and M12 are connected in common. It means that Similarly, the common connection of the gates of the transistors is displayed.

  Here, the gates of the transistors M2 and M4 are connected to Out− and Out +, respectively. The transistors M2 and M4 are designed to operate in the linear region.

  In the input section 11 of this operational amplifier circuit, the differential signal component of the input signal voltage applied to the gates of the transistors M1 and M3 constitutes a differential pair by commonly connecting the sources of the transistors M1 and M3. It is determined by the voltage-current conversion gain of the transistors M1 and M3.

  On the other hand, for the in-phase signal component of the input signal voltage applied to the gates of the transistors M1 and M3, the output resistors ro2 and ro4 (ro4 = ro2) connected in parallel of the transistors M2 and M4 are connected to the transistors M1 and M3. Between source and power supply Vss. Therefore, the voltage-current conversion gain for the in-phase signal component of the input unit is gm1 / (1 + gm1 (ro2 / 2)), where the voltage-current conversion gains of the transistors M1 and M3 are gm1 and gm3 (gm3 = gm1). The voltage / current conversion gain for the dynamic signal component can be reduced to 1 / (1 + gm1 (ro2 / 2)).

  In addition, since the gates of the transistors M2 and M4 operating in the linear region are connected to the output terminals Out− and Out +, respectively, a current corresponding to the output voltage of the output terminal Out− flows through the transistor M2, and the transistor M4 Current flows according to the output voltage of the output terminal Out +. Therefore, a current proportional to the sum of the output voltage at the output terminal Out− and the output voltage at the output terminal Out + flows through the common source of the transistors M1 and M3.

  Since the sum of the output voltage at the output terminal Out− and the output voltage at the output terminal Out + is proportional to the in-phase signal component of the output voltage, this input section is a current proportional to the in-phase component of the output voltage at the output terminals Out− and Out +. The common-mode feedback circuit that feeds back is realized. With this common-mode feedback circuit, the load on the common-mode component is 1/2 gm, that is, 1 / gm2 when the voltage-current conversion gains of the transistors M2 and M4 are gm2 and gm4 (gm4 = gm2).

  On the other hand, the loads on the differential components are the output resistances ro11 and ro12 (ro12 = ro11) of the transistors M11 and M12 constituting the current source circuit 12, and the output resistances ro1 and ro2 (ro2) of the transistors M1 and M2 constituting the input unit 11. = Ro1). Therefore, the differential gain of this operational amplifier circuit is gm1 · (ro11 // ro1), and the common-mode gain is expressed as gm1 / {gm2 (1 + gm1 (ro2 / 2))}. Therefore, the current consumption can be halved and the common-mode gain can be greatly reduced compared to the differential gain, compared to the configuration in which the input unit and the output unit configured by the differential pair are separated as in the conventional circuit shown in FIG.

<Second Embodiment>
FIG. 2 is a diagram illustrating an example of the operational amplifier circuit according to the second embodiment of the present invention in which the gate ground circuits 23a and 23b are inserted into the input unit 21 and the current source circuit 22 to increase the gain. Also in this embodiment, the NMOS transistors M1, M2, M3, and M4 constitute the input unit 21 of the operational amplifier circuit.

  Since the transistors M5 and M6 having the bias voltage Vc3 applied to the gate are inserted between the drains of the transistors M1 and M3 and the output terminal, the output resistance when the input unit 21 is viewed from the output terminal is increased by 5 times gm5 · ro. . Here, gm5 and gm6 (gm6 = gm5) are voltage / current conversion gains of the transistors M5 and M6, and ro5 and ro6 (ro6 = ro5) are output resistances of the transistors M5 and M6.

  In addition, transistors M13 and M14 having a gate to which a bias voltage Vc2 is applied are inserted between the drains of the transistors M11 and M12 and the output terminal. Therefore, the output resistance when the current source circuit is viewed from the output terminal is gm13 · ro13 times higher. Here, gm13 and gm14 (gm13 = gm14) are voltage-current conversion gains of the transistors M13 and M14, and ro13 and ro14 (ro13 = ro14) are output resistances of the transistors M13 and M14.

  Further, the voltage-current conversion gain for the input signal of the input unit 21 does not change even when the gate grounding by the transistors M5 and M6 is inserted. Since the gain is determined by the product of the voltage-current conversion gain of the input section and the output resistance viewed from the output terminal, a high gain can be realized by inserting a grounded gate circuit.

<Third Embodiment>
FIG. 3 is a diagram showing a circuit example of the third embodiment in which the input unit in the operational amplifier circuit of the embodiment of the present invention is modified. In FIG. 3, transistors M7 and M8 are added to the input section of the operational amplifier circuit shown in FIG. That is, the input unit 31 is configured by NMOS transistors M1, M2, M3, M4, M7, and M8.

  The transistor M7 has its drain and source connected to the drain and source of the transistor M2, respectively, and the transistor M8 has its drain and source connected to the drain and source of the transistor M4. In this configuration, the transistors M1 and M7 are stacked vertically and have a common gate. Similarly, the transistors M3 and M8 are stacked vertically and have a common gate.

  According to such a circuit configuration, the drain-source voltages of the transistors M7 and M8 are determined so that the transistors M7 and M8 operate in a linear region. Since the drain-source voltages of the transistors M2 and M4 are equal to the drain-source voltages of the transistors M7 and M8, the transistors M2 and M4 can be easily designed to operate in the linear region.

<Fourth Embodiment>
FIG. 4 is an embodiment showing a bias voltage generating circuit 43 for setting a bias voltage at the gate of the transistor constituting the current source circuit 42 in the operational amplifier circuit shown in FIG. The input unit 41 is composed of NMOS transistors M1, M2, M3, M4, M7, and M8.

  The transistors M21 and M22 simulate the input unit, and a voltage Vb corresponding to the operating point of the input signal applied from the input terminal is applied to the gate of the transistor M21, and the output signal is applied to the gate of the transistor M22. A voltage Vcm corresponding to the operating point is applied.

  A bias voltage Vc3 is applied to the gates of the transistors M5, M6, and M23, and a bias voltage Vc2 is applied to the gates of the transistors M13, M14, and M26 to form the gate ground circuit 44.

  The source of the NMOS transistor M25 constituting the bias voltage generation circuit 43 is connected to the power supply Vdd, the drain thereof is connected to the source of the NMOS transistor M26, and the drain of this transistor is connected to the drain of the PMOS transistor M23. The gate of the NMOS transistor M25 is connected to the gates of the transistors M11 and M12, the gate of the NMOS transistor M26 is connected to the gates of the transistors M13 and M14, and the gate of the transistor M23 is connected to the gates of the transistors M5 and M6. Yes.

  As described above, by applying the voltage Vb to the gate of the transistor M21 and applying the voltage Vcm to the gate of the transistor M22, the bias of the current source circuit 42 is set so that an appropriate bias current flows through the input unit 41. The voltage Vc1 can be set.

<Fifth Embodiment>
FIG. 5 similarly shows an embodiment showing a bias voltage generation circuit 53 for setting a bias voltage at the gate of a transistor constituting the current source circuit 52 in the operational amplifier circuit shown in FIG. An NMOS 51 transistors M1, M2, M3, M4, M7, and M8 constitute an input unit 51.

  The transistors M21, M22, and M24 simulate the input unit, and a voltage Vb corresponding to the operating point of the input signal applied from the input terminal is applied to the gates of the transistors M21 and M24, and the gate of the transistor M22 is applied. By applying a voltage Vcm corresponding to the operating point of the output signal, the bias voltage Vc1 of the current source circuit can be set so that an appropriate bias current flows through the input section.

<Sixth Embodiment>
FIG. 6 is an example in which the grounded gate circuit is replaced with a regulated cascode circuit 65 using inverting amplifier circuits A1 to A6 in order to further increase the gain in the operational amplifier circuit shown in FIG.

  The input unit 61 includes transistors M1, M2, M3, and M4, and the current source circuit 62 includes transistors M11 and M12. The regulated cascode circuit 65 includes transistors M5, M6, M13, M14, M23, and M26, and inverting amplifier circuits A1, A2, A3, A4, A5, and A6.

  The source of the transistor M5 is connected to the input terminal of the inverting amplifier circuit A1 and the drain of the transistor M1, and the gate of this transistor is connected to the output terminal of the inverting amplifier circuit A1.

  The source of the transistor M6 is connected to the input terminal of the inverting amplifier circuit A2 and the drain of the transistor M3, and the gate of this transistor is connected to the output terminal of the inverting amplifier circuit A2.

The source of the transistor M13 is connected to the input terminal of the inverting amplifier circuit A3 and the drain of the transistor M11, and the gate of this transistor is connected to the output terminal of the inverting amplifier circuit A3.

  The source of the transistor M14 is connected to the input terminal of the inverting amplifier circuit A4 and the drain of the transistor M12, and the gate of this transistor is connected to the output terminal of the inverting amplifier circuit A3.

  The drains of the transistors M13 and M5 are connected to the gate of the transistor M2 and the output terminal Out−, and the drains of the transistors M14 and M6 are connected to the gate of the transistor M4 and the output terminal Out +.

  The source of the transistor M23 is connected to the input terminal of the inverting amplifier circuit A5 and the drain of the transistor M21, and the gate of this transistor is connected to the output terminal of the inverting amplifier circuit A5.

  The source of the transistor M26 is connected to the input terminal of the inverting amplifier circuit A6 and the drain of the transistor M25, and the gate of this transistor is connected to the output terminal of the inverting amplifier circuit A6.

  The drains of the transistors M23 and M26 are connected to the gate of the transistor M25.

  By replacing the grounded gate circuit shown in FIG. 4 with the regulated cascode circuit 65, the output resistance viewed from the output terminal can be increased by a factor of the inverting amplifier circuit A1, and the current from the output terminal can be increased. The output resistance viewed from the source circuit can be increased by the amplification factor times that of the inverting amplifier circuit A3. Thereby, the gain of the operational amplifier circuit can be further increased.

<Embodiment in which the operational amplifier circuit according to the present invention is used in a sample and hold circuit>
7 and 8 show examples of the configuration and operation of a sample and hold circuit configured using the operational amplifier circuit of the present invention. This sample and hold circuit includes switches SW1 and SW2 having one ends connected to input terminals IN1 and IN2, capacitors C1 and C2 having one ends connected to the other ends of the switches SW1 and SW2, and capacitors C1 and C2. Switches SW3 and SW4 each having one end connected to the other end and grounded at the other end, switches SW5 and SW6 having one end connected to the other end of each of the capacitors C1 and C2, and the switches SW5 and SW6. Switches SW7 and SW8 having one end connected to the other end, an operational amplifier circuit OPA having two input terminals connected to the other ends of the switches SW5 and SW6, and output terminals OUT1 and OUT2 of the operational amplifier circuit OPA. A switch connected between the connection point of the switch SW1 and the capacitor C1, and between the connection point of the switch SW2 and the capacitor C2. Made from the blood SW9, SW10 Metropolitan.

  The other ends of the switches SW7 and SW8 are connected to the output terminals OUT1 and OUT2 of the operational amplifier circuit OPA, respectively.

  At the time of writing, as shown in FIG. 7, the input terminal SW1 and the switches SW1 to SW4, SW7, SW8 are closed, and the switches SW5, SW6, SW9, SW10 are opened. In this state, when the input signals IN1 and IN2 are input, the input signals are accumulated in the capacitors C1 and C2, and the input signal is stored. At the time of reading, as shown in FIG. 8, the switches SW1 to SW4, WS7, SW8 are opened, and the switches SW5, SW6, SW9, SW10 are closed. At this time, signals accumulated in the capacitors C1 and C2 are input to the operational amplifier circuit OPA.

  In the sample and hold circuit as described above, the switch is configured by a MOS transistor. MOS transistors have channel formation when they are turned on and off. When this channel is formed, charge components enter in phase. For this reason, the voltage rises in the channel portion, and if this voltage rise is not suppressed, it becomes saturated.

  In this embodiment of the present invention, the common-mode component is canceled out in the operational amplifier circuit OPA, so that the common-mode gain is reduced and the power supply voltage of the sample-and-hold circuit can be reduced, and the power consumption is higher than that of the conventional operational amplifier circuit. Therefore, the power consumption of the sample and hold circuit can be reduced.

<Embodiment Using the Operational Amplifier Circuit According to the Present Invention for the Filter Circuit>
FIG. 10 shows a filter circuit using the integrators Int1 to Int5. As shown in FIG. 9, these integrators are composed of, for example, an amplifier Amp1, resistors R1 to R4, and capacitors C3 and C4. The operational amplifier circuit according to the present invention as described above is used for the amplifier Amp1.

  One end of the resistor R1 is connected to the input terminal IN1 +, one end of the resistor R2 is connected to the input terminal IN2 +, one end of the resistor R3 is connected to the input terminal IN1-, and one end of the resistor R4 is connected to the input terminal IN2-.

  The other ends of the resistor R1 and the resistor R2 are connected, connected to one input terminal of the two inputs of the amplifier Amp1, and one end of the capacitor C3, and the other end is connected to the output terminal OUT- of the amplifier Amp1. The other ends of the resistor R3 and the resistor R4 are connected, connected to the other input terminal of the two inputs of the amplifier Amp1 and one end of the capacitor C4, and the other end is connected to the output terminal OUT + of the amplifier Amp1.

  The integrator Int1 has three positive and negative input terminals, and the other integrators Int2 to Int5 have two positive and negative input terminals. One positive / negative input terminal of the integrator Int1 is connected to one positive / negative input terminal of the integrator Int2, and the other positive / negative input terminal of the integrator Int1 is connected to one positive / negative input terminal of the integrator Int3. . The other positive / negative input terminal of the integrator Int2 is connected to one positive / negative input terminal of the integrator Int4, and the other positive / negative input terminal of the integrator Int3 is connected to one positive / negative input terminal of the integrator Int5. Is done.

  The positive / negative output terminal of the integrator Int1 is connected to one positive / negative input terminal of the integrator Int2, the positive / negative output terminal of the integrator Int2 is connected to one positive / negative input terminal of the integrator Int3, and the positive / negative output terminal of the integrator Int3 is The integrator Int4 is connected to one positive / negative input terminal, and the integrator Int4 has a positive / negative output terminal connected to one positive / negative input terminal of the integrator Int5.

  The positive / negative output terminal of the integrator Int5 is connected to the other positive / negative input terminal of the integrator Int4 and the output terminal of this filter circuit. The input terminal of this filter circuit is connected to still another positive / negative input terminal of the integrator Int1.

  In this embodiment of the present invention, the common-mode component is canceled out in the operational amplifier circuit constituting the integrator, so that the common-mode gain is reduced, and a low power supply voltage of the filter circuit using this integrator can be realized. In addition, since the power consumption can be reduced as compared with the conventional operational amplifier circuit, the power consumption of the filter circuit can be reduced.

  The present invention is not limited to the above-described embodiment, and various modifications and additions of components can be made at the stage of implementation. The technical scope of the present invention is not deviated from the technical idea of the present invention. include.

The figure which shows the structural example of the operational amplifier circuit of 1st Embodiment by this invention. The figure which shows the structural example of the operational amplifier circuit of 2nd Embodiment by this invention. The figure which shows the structural example of the operational amplifier circuit of 3rd Embodiment by this invention. The figure which shows the structural example of the operational amplifier circuit of 4th Embodiment by this invention. The figure which shows the structural example of the operational amplifier circuit of 5th Embodiment by this invention. The figure which shows the structural example of the operational amplifier circuit of 6th Embodiment by this invention. The figure for demonstrating the structural example and operation | movement of one Embodiment which used the operational amplifier circuit by this invention for the sample hold circuit. The figure for demonstrating operation | movement of one Embodiment which used the operational amplifier circuit by this invention for the sample hold circuit. The figure which shows the structural example of one Embodiment which comprises the operational amplifier circuit by this invention which comprises a filter circuit. The figure which shows one Embodiment which used the operational amplifier circuit by this invention for the integrator, and comprised this to the filter circuit. The figure which shows the structural example of the conventional operational amplifier.

Explanation of symbols

M1, M2, M3, M4, M5, M6, M7, M8, M11, M12, MM1, 3M14, M21, M22, M23, M24, M25, M26...
In +, In-, In1, In2, ... input terminals,
Out +, Out−, OUT1, OUT2... Output terminals,
Vdd, Vss ... power supply,
11, 21, 31 ... input section,
12, 22, 42, 52, 62 ... current source circuit,
23a, 23b ... Gate grounding circuit,
43, 53... Bias voltage generation circuit,
65 ... Regulated cascode circuit,
A1, A2, A3, A4, A5, A6... Amplifying circuit,
C1, C2, C3, C4 ... capacitors,
SW1, SW2, SW3, SW4, SW5, SW6, SW7, SW8, SW9, SW10... Switch,
R1, R2, R3, R4 ... resistors,
OPA: operational amplifier circuit,
Int1, Int2, Int3, Int4, Int5 ... integrators.

Claims (5)

A first transistor having a first input terminal connected to the gate and a first output terminal connected to the drain;
A second transistor having a drain connected to a source of the first transistor and a source connected to a first power source;
A first current source circuit connected between the drain of the first transistor and a second power supply;
A third transistor having a second input terminal connected to the gate and a second output terminal connected to the drain;
A fourth transistor having a drain connected to the source of the third transistor and a source connected to the first power source;
A second current source circuit connected between the drain of the second transistor and a second power source;
The sources of the first transistor and the third transistor are connected in common, the first output terminal is connected to the gate of the second transistor, and the second output terminal is connected to the fourth transistor. An operational amplifier circuit characterized by being connected to a gate. A first transistor having a first input terminal connected to the gate;
A second transistor having a drain connected to a source of the first transistor and a source connected to a first power source;
A fifth transistor having a drain connected to the source and a drain connected to the first output terminal;
A first current source circuit connected between the drain of the fifth transistor and a second power source;
A third transistor having a second input terminal connected to the gate;
A fourth transistor having a drain connected to a source of the third transistor and a source connected to the first power source;
A sixth transistor in which the drain of the third transistor is connected to the source and the drain is connected to the second output terminal;
A second current circuit connected between the drain of the sixth transistor and the second power supply;
The sources of the first transistor and the third transistor are connected in common, the first output terminal is connected to the gate of the second transistor, and the second output terminal is connected to the fourth transistor. An operational amplifier circuit characterized by being connected to a gate. A seventh transistor having the first input terminal connected to the gate and the source and drain connected to the source and drain of the second transistor;
2. The eighth transistor according to claim 1, further comprising: an eighth transistor having the second input terminal connected to the gate and a source and a drain connected to the source and the drain of the fourth transistor, respectively. 3. The operational amplifier circuit according to 2.   A sample and hold circuit comprising the operational amplifier circuit according to claim 1 or 2.   A filter circuit comprising the operational amplifier circuit according to claim 1 or 2.

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