JP2006332667A - Tape package preventing crack at lead bonding - Google Patents

Tape package preventing crack at lead bonding Download PDF

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Publication number
JP2006332667A
JP2006332667A JP2006143311A JP2006143311A JP2006332667A JP 2006332667 A JP2006332667 A JP 2006332667A JP 2006143311 A JP2006143311 A JP 2006143311A JP 2006143311 A JP2006143311 A JP 2006143311A JP 2006332667 A JP2006332667 A JP 2006332667A
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Japan
Prior art keywords
wiring
tape package
semiconductor chip
package according
lead wiring
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Pending
Application number
JP2006143311A
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Japanese (ja)
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JP2006332667A5 (en
Inventor
Ye-Chung Chung
鄭　禮貞
Shiin Kyo
姜　思尹
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Priority claimed from KR20050043810A external-priority patent/KR100618898B1/en
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of JP2006332667A publication Critical patent/JP2006332667A/en
Publication of JP2006332667A5 publication Critical patent/JP2006332667A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/36—Assembling printed circuits with other printed circuits
    • H05K3/361—Assembling flexible printed circuits with other printed circuits
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
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    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
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    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/73265—Layer and wire connectors
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009—Pre-treatment of the layer connector or the bonding area
    • H01L2224/83051—Forming additional members, e.g. dam structures
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    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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    • H01L2924/151—Die mounting substrate
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    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
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    • H05K2201/09154—Bevelled, chamferred or tapered edge
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    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
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  • Chemical & Material Sciences (AREA)
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  • Wire Bonding (AREA)
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a tape package which prevents formation of cracks at outer lead bonding of the bonding output leads of the tape package, to a glass panel. <P>SOLUTION: The tape package has solder resist that covers input lead wiring and the part of output lead wiring, excluding their terminations. A wiring failure preventive means, having an expanded lead width, is formed on the part of the exposed output lead wiring that does not have solder resist coating connected to wiring on the glass panel, that is, a region of the exposed output lead wiring, where cracks tend to develop. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、半導体素子に係り、特にＬＣＤ（Ｌｉｑｕｉｄ Ｃｒｙｓｔａｌ Ｄｉｓｐｌａｙ）素子のような平板表示素子（Ｆｌａｔ Ｐａｎｅｌ Ｄｉｓｐｌａｙ：ＦＰＤ）に使われるテープパッケージに関する。   The present invention relates to a semiconductor device, and more particularly, to a tape package used for a flat panel display (FPD) such as an LCD (Liquid Crystal Display) device.

最近、ディスプレイ装置は、既存のＣＲＴ（Ｃａｔｈｏｄｅ Ｒａｙ Ｔｕｂｅ）型からＦＰＤに転換されつつ、ＬＣＤ及びＰＤＰ（Ｐｌａｓｍａ Ｄｉｓｐｌａｙ Ｐａｎｅｌ）のような表示装置が活発に開発されている。このようなＦＰＤは、ガラスパネルと駆動回路基板との連結を、テープパッケージという独特な構造の半導体パッケージを使用して実施する。   Recently, display devices such as LCDs and PDPs (Plasma Display Panels) have been actively developed as display devices are being converted from existing CRT (Cathode Ray Tube) types to FPDs. In such an FPD, a glass panel and a driving circuit board are connected using a semiconductor package having a unique structure called a tape package.

図１は、一般的なテープパッケージが使われるＦＰＤの内部構造を説明するための斜視図である。   FIG. 1 is a perspective view for explaining an internal structure of an FPD in which a general tape package is used.

図１に示すように、画像表示の用途として使われるガラスパネル５０は、前面パネル５１及び背面パネル５２から構成されている。そして、前記ガラスパネル５０の背面には、シャーシベース２０があり、前記シャーシベース２０には、複数個の駆動回路基板４０が付着されている。このとき、テープパッケージ１２は、前記ガラスパネル５０と前記駆動回路基板４０とを側面に連結する構造の半導体パッケージである。   As shown in FIG. 1, a glass panel 50 used for image display is composed of a front panel 51 and a back panel 52. A chassis base 20 is provided on the rear surface of the glass panel 50, and a plurality of drive circuit boards 40 are attached to the chassis base 20. At this time, the tape package 12 is a semiconductor package having a structure in which the glass panel 50 and the driving circuit board 40 are connected to side surfaces.

図２は、一般的なテープパッケージの平面図である。   FIG. 2 is a plan view of a general tape package.

図２に示すように、一般的に、テープパッケージ１２は、ポリイミドのような柔軟性材質のベース基板３０上に形成される。前記ベース基板３０には、中央部に搭載された半導体チップ３２、前記半導体チップ３２と連結された銅箔パターン３８で駆動回路基板と連結される入力リード配線３４、及び前記半導体チップ３２と連結された銅箔パターンでガラスパネルと連結される出力リード配線３６がある。   As shown in FIG. 2, the tape package 12 is generally formed on a base substrate 30 made of a flexible material such as polyimide. The base substrate 30 is connected to the semiconductor chip 32 mounted in the center, the input lead wiring 34 connected to the driving circuit board by the copper foil pattern 38 connected to the semiconductor chip 32, and the semiconductor chip 32. There is an output lead wiring 36 connected to the glass panel with a copper foil pattern.

図３は、テープパッケージがＦＰＤのガラスパネルに付着されることを示す断面図である。   FIG. 3 is a cross-sectional view showing that the tape package is attached to the glass panel of the FPD.

図３に示すように、ガラスパネル５０には、ＩＴＯ（Ｉｎｄｉｕｍ−Ｔｉｎ Ｏｘｉｄｅ）材質の透明回路パターン５２が形成されている。また、前記ガラスパネル５０の終端は、傾斜して処理されている。このとき、テープパッケージの出力リード配線３６は、導電性を有する異方性接着剤１４により前記ガラスパネル５０と電気的に連結されつつ付着される。前記出力リード配線３６は、ベース基板３０における銅箔パターン３８上での該銅箔パターン３８の絶縁に使われるソルダレジスト４０により覆われていた。   As shown in FIG. 3, a transparent circuit pattern 52 made of ITO (Indium-Tin Oxide) material is formed on the glass panel 50. Further, the end of the glass panel 50 is processed in an inclined manner. At this time, the output lead wiring 36 of the tape package is attached while being electrically connected to the glass panel 50 by the anisotropic adhesive 14 having conductivity. The output lead wiring 36 was covered with a solder resist 40 used for insulating the copper foil pattern 38 on the copper foil pattern 38 in the base substrate 30.

図３のように、導電性を有する異方性接着剤１４を使用して、ガラスパネル５０にテープパッケージの出力リード配線３６を電気的に連結しつつ付着する工程をＯＬＢ（Ｏｕｔｅｒ Ｌｅａｄ Ｂｏｎｄｉｎｇ）工程という。しかし、ＯＬＢ工程でソルダレジストにより覆われずに露出された銅箔パターン３８にクラックやオープン欠陥が発生するおそれがある。   As shown in FIG. 3, the process of attaching the output lead wiring 36 of the tape package to the glass panel 50 while electrically connecting it using the conductive anisotropic adhesive 14 is an OLB (Outer Lead Bonding) process. That's it. However, cracks and open defects may occur in the copper foil pattern 38 exposed without being covered with the solder resist in the OLB process.

図３において、Ａ部分は、テープパッケージの出力リード配線３６においてガラスパネル５０にある透明回路パターン５２と連結される部分であり、Ｃ部分は、テープパッケージの出力リード配線３６においてソルダレジスト４０により覆われる部分である。そして、Ｂ部分は、Ａ部分のようにソルダレジスト４０により覆われずに露出されるが、ガラスパネル５０にある透明回路パターン５２と連結されずにクラックやオープン欠陥が頻繁に発生する領域である。   In FIG. 3, A part is a part connected to the transparent circuit pattern 52 on the glass panel 50 in the output lead wiring 36 of the tape package, and C part is covered with the solder resist 40 in the output lead wiring 36 of the tape package. It is a part to be called. And B part is an area | region where a crack and an open defect generate | occur | produce frequently, without being connected with the transparent circuit pattern 52 in the glass panel 50, although it is exposed without being covered with the solder resist 40 like the A part. .

図４は、一般的なテープパッケージの出力リード配線の終端を示す平面図である。前述したように、ＯＬＢ工程の進行時、銅箔パターン３８のサイズが一定である場合、図４でＢ部分に対して引張や圧力が集中しうるため、Ｂ部分にある銅箔パターン３８でクラックや銅箔パターンが切れる不良が発生し、これは、信頼性のあるテープパッケージの具現のために改善されねばならない品質問題のうちの一つである。   FIG. 4 is a plan view showing an end of output lead wiring of a general tape package. As described above, when the size of the copper foil pattern 38 is constant during the OLB process, tension and pressure may concentrate on the B portion in FIG. In other words, a defect that cuts the copper foil pattern occurs, which is one of the quality problems that must be improved to realize a reliable tape package.

本発明が解決しようとする課題は、前述した問題点を解決するために、テープパッケージの内部に配線欠陥防止手段をさらに設置して、リードボンディング時にクラックを防止するテープパッケージを提供することである。   The problem to be solved by the present invention is to provide a tape package for preventing cracks during lead bonding by further providing a wiring defect prevention means inside the tape package in order to solve the above-mentioned problems. .

前記課題を解決するために、本発明によるリードボンディング時にクラックを防止するテープパッケージは、柔軟性を有する絶縁材質のベース基板、前記ベース基板に形成された半導体チップ搭載領域、前記半導体チップ搭載領域に付着された半導体チップ、前記半導体チップ搭載領域と電気的に連結されて駆動回路基板の方向に拡張される入力リード配線、前記半導体チップ搭載領域と電気的に連結されてガラスパネルの方向に拡張される出力リード配線、前記入力リード配線及び出力リード配線の終端を除いた部分を覆うソルダレジスト、及び前記ソルダレジストにより覆われずに露出された出力リード配線の終端のうち、前記ガラスパネルの配線と連結されていない部分に形成され、拡張されたリード幅を有する配線欠陥防止手段を備えることを特徴とする。   In order to solve the above-mentioned problems, a tape package for preventing cracks during lead bonding according to the present invention includes a base substrate made of a flexible insulating material, a semiconductor chip mounting region formed on the base substrate, and a semiconductor chip mounting region. Adhered semiconductor chip, input lead wiring electrically connected to the semiconductor chip mounting area and extended in the direction of the driving circuit board, electrically connected to the semiconductor chip mounting area and extended in the direction of the glass panel Out of the output lead wiring, the solder lead covering the input lead wiring and the portion excluding the terminal end of the output lead wiring, and the terminal of the output lead wiring exposed without being covered with the solder resist, Wiring defect prevention means with extended lead widths formed on unconnected parts And wherein the Rukoto.

本発明の望ましい実施形態によれば、前記ソルダレジストにより覆われずに露出された出力リード配線の終端は、“Ｙ”字状を有することが望ましく、前記配線欠陥防止手段の拡張されたリード幅は、前記出力リード配線の終端で前記ガラスパネルの配線と連結される部分のリード幅より広いか、または前記配線欠陥防止手段の拡張されたリード幅は、前記ソルダレジストにより覆われる出力リード配線の幅より広いことが望ましい。   According to a preferred embodiment of the present invention, the end of the output lead wiring exposed without being covered with the solder resist preferably has a “Y” shape, and the extended lead width of the wiring defect prevention means is increased. Is wider than the lead width of the portion connected to the glass panel wiring at the end of the output lead wiring, or the expanded lead width of the wiring defect prevention means is the output lead wiring covered by the solder resist. Desirably wider than the width.

また、本発明の望ましい実施形態によれば、前記半導体チップは、前記半導体チップ搭載領域とソルダバンプを通じて電気的に連結されるか、またはワイヤを通じて電気的に連結されることが望ましい。   The semiconductor chip may be electrically connected to the semiconductor chip mounting region through a solder bump or electrically connected through a wire.

前記拡張されたリード幅を有する配線欠陥防止手段は、前記ベース基板上で厚さが均一であることが望ましく、前記ソルダレジストにより覆われる出力リード配線は、ボンディング時に使われる熱によるストレスが吸収可能な“Ｓ”字状であることが望ましい。   The wiring defect prevention means having the expanded lead width is preferably uniform in thickness on the base substrate, and the output lead wiring covered with the solder resist can absorb heat stress used during bonding. The “S” shape is desirable.

前記リードボンディング時にクラックを防止するテープパッケージは、前記半導体チップを密封する封止樹脂をさらに備える。   The tape package for preventing cracks during the lead bonding further includes a sealing resin for sealing the semiconductor chip.

前記課題を解決するために、本発明は、柔軟性を有する絶縁材質のベース基板、前記ベース基板に形成された半導体チップ搭載領域、前記半導体チップ搭載領域に付着された半導体チップ、前記半導体チップ搭載領域と電気的に連結されてディスプレイ駆動回路基板の方向に拡張される入力リード配線、前記半導体チップ搭載領域と電気的に連結されてガラスパネルの方向に拡張される出力リード配線、前記入力リード配線及び出力リード配線の終端を除いた部分を覆うソルダレジスト、及び前記入力リード配線及び出力リード配線に形成され、拡張されたリード幅を有する配線欠陥防止手段を備えることを特徴とするリードボンディング時にクラックを防止するテープパッケージを提供する。   In order to solve the above problems, the present invention provides a base substrate made of an insulating material having flexibility, a semiconductor chip mounting region formed on the base substrate, a semiconductor chip attached to the semiconductor chip mounting region, and the semiconductor chip mounting. An input lead wiring electrically connected to the area and extended in the direction of the display driving circuit board, an output lead wiring electrically connected to the semiconductor chip mounting area and extended in the direction of the glass panel, and the input lead wiring And a solder resist covering a portion excluding the terminal end of the output lead wire, and a wiring defect preventing means formed on the input lead wire and the output lead wire and having an extended lead width, and cracking at the time of lead bonding Provide tape package to prevent

本発明の望ましい実施形態によれば、前記拡張されたリード幅を有する配線欠陥防止手段は、前記ソルダレジストにより覆われる領域に形成されるか、または覆われない領域に形成されうる。   According to a preferred embodiment of the present invention, the wiring defect prevention means having the expanded lead width may be formed in a region covered by the solder resist or in a region not covered.

本発明によれば、ＯＬＢ工程でクラック及び銅箔パターンのクラックやオープンが集中的に発生する領域に対する銅箔パターンの幅はさらに広く拡張させて、この部分に対する物理的機械的強度を高めてテープパッケージの製造工程で発生する欠陥を抑制できる。   According to the present invention, the width of the copper foil pattern with respect to the region where cracks and cracks of the copper foil pattern are intensively generated in the OLB process is further expanded to increase the physical mechanical strength of the tape. Defects that occur in the manufacturing process of the package can be suppressed.

以下、添付された図面を参照して、本発明の望ましい実施形態を詳細に説明する。しかし、下記の詳細な説明で開示される実施形態は、本発明を限定しようとする意味ではなく、当業者に本発明の開示が実施可能な形態に完全になるように発明の範疇を知らせるために提供されるものである。   Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the embodiments disclosed in the following detailed description are not meant to limit the present invention, but to inform those skilled in the art of the scope of the invention so that the disclosure of the present invention can be fully implemented. Is provided.

図５は、本発明によるテープパッケージの平面図である。   FIG. 5 is a plan view of a tape package according to the present invention.

図５に示すように、一般的に、テープパッケージは、ポリイミドあるいはエポキシ系樹脂のような柔軟性材質のベース基板１００上に形成される。このようなベース基板１００上で、図５のＬ１の長さ内で一つのテープパッケージが形成される。このとき、ベース基板１００には、テープパッケージの加工を容易にするためのスプロケットホール１１２が明けられている。   As shown in FIG. 5, the tape package is generally formed on a base substrate 100 made of a flexible material such as polyimide or epoxy resin. On such a base substrate 100, one tape package is formed within the length of L1 in FIG. At this time, the base substrate 100 has a sprocket hole 112 for facilitating the processing of the tape package.

図５において、Ａ２点線により区分される領域は、一つのテープパッケージを作るために切断される領域であり、ＴＰ１及びＴＰ２領域は、テープパッケージを組み立てた後、Ａ２点線領域を切断する前に、テープパッケージの機能を検査するための検査パッド１１６が位置した領域をそれぞれ示す。   In FIG. 5, the area divided by the A2 dotted line is an area that is cut to make one tape package, and the TP1 and TP2 areas are assembled after the tape package is assembled and before the A2 dotted line area is cut. Each region in which a test pad 116 for testing the function of the tape package is located is shown.

前記図５には、中央に半導体チップ（図示せず）が搭載される空間である半導体チップ搭載領域１１８が設けられており、複雑な形態の銅箔パターン１３８がベース基板１００上に形成されている。このとき、駆動回路基板と連結される入力リード配線（図５のＢ１領域）が前記半導体チップ搭載領域１１８の上に位置し、ガラスパネルと連結される出力リード配線（図５のＢ２領域）が前記半導体チップ搭載領域１１８の下に位置する。前記ベース基板１００上で、銅箔パターン１３８、入力リード配線１３４及び出力リード配線１３６は、一部を除いてソルダレジストにより覆われる。図５においてＡ１点線で表示された部分は、ソルダレジストが塗布される領域を示す。   In FIG. 5, a semiconductor chip mounting region 118, which is a space in which a semiconductor chip (not shown) is mounted, is provided at the center, and a copper foil pattern 138 having a complicated shape is formed on the base substrate 100. Yes. At this time, the input lead wiring (B1 region in FIG. 5) connected to the drive circuit board is located on the semiconductor chip mounting region 118, and the output lead wiring (B2 region in FIG. 5) connected to the glass panel is formed. The semiconductor chip mounting area 118 is located below. On the base substrate 100, the copper foil pattern 138, the input lead wiring 134, and the output lead wiring 136 are covered with a solder resist except for a part thereof. In FIG. 5, a portion indicated by a dotted line A1 indicates a region to which the solder resist is applied.

本発明では、ＯＬＢ工程の進行時、出力リード配線１３６で主に発生するクラックや銅箔パターン１３８のオープン欠陥を抑制するために、配線欠陥防止手段をさらに備える。これについては、図６ないし図１１を参照して詳細に説明する。たとえ図５では出力リード配線１３６にのみ配線欠陥防止手段を設置したとしても、これは、クラック及び銅箔パターン１３８のオープン欠陥が発生しうる領域ならば、どこにも設置可能である。一例として、入力リード配線１３４にも設置が可能であり、必要ならば、ソルダレジストＡ１により覆われる領域の銅箔パターン１３８に対しても設置が可能である。   In the present invention, in order to suppress cracks mainly generated in the output lead wiring 136 and open defects of the copper foil pattern 138 during the OLB process, wiring defect prevention means is further provided. This will be described in detail with reference to FIGS. Even if the wiring defect prevention means is installed only on the output lead wiring 136 in FIG. 5, this can be installed anywhere as long as cracks and open defects of the copper foil pattern 138 can occur. As an example, it can also be installed on the input lead wiring 134 and, if necessary, can also be installed on the copper foil pattern 138 in the region covered with the solder resist A1.

図６は、本発明の一実施形態によるテープパッケージの出力リード配線の終端を示す平面図である。   FIG. 6 is a plan view showing the termination of the output lead wiring of the tape package according to the embodiment of the present invention.

図６に示す例は、ソルダレジスト１２０により覆われずに露出された出力リード配線１３６の終端から拡張されたリード幅を有する配線欠陥防止手段１１０を構成した例である。すなわち、一般的な銅箔パターン１３８の幅が１５ないし５０μｍであれば、クラック及びパターンのオープンが頻繁に発生する領域にある拡張されたリード幅を有する配線欠陥防止手段の幅を２０ないし８０μｍと広く形成する。このとき、出力リード配線１３８で、配線欠陥防止手段１１０は“Ｙ”字状に狭くなる。前記銅箔パターンは、銅及び銅合金からなる金属パターンでありうる。   The example shown in FIG. 6 is an example in which the wiring defect prevention means 110 having a lead width extended from the end of the output lead wiring 136 exposed without being covered with the solder resist 120 is configured. That is, if the width of the general copper foil pattern 138 is 15 to 50 μm, the width of the wiring defect prevention means having an extended lead width in a region where cracks and pattern open frequently occur is 20 to 80 μm. Form widely. At this time, in the output lead wiring 138, the wiring defect prevention means 110 is narrowed in a “Y” shape. The copper foil pattern may be a metal pattern made of copper and a copper alloy.

したがって、外部から引張力や曲げ力が作用するとき、既存の狭い幅を有する銅箔パターンと比較するとき、本発明による拡張されたリード幅を有する配線欠陥防止手段１００は、この部分Ｂで物理的機械的強度がさらに改善されて、クラックやパターンのオープンの発生を抑制できる。前記配線欠陥防止手段１００が形成された部分Ｂは、ガラスパネルの傾斜面（図３のＢ部分を参照）と対応する。   Accordingly, when a tensile force or bending force is applied from the outside, the wiring defect prevention means 100 having an extended lead width according to the present invention is physically connected to this portion B when compared with an existing copper foil pattern having a narrow width. The mechanical strength is further improved, and the occurrence of cracks and pattern opening can be suppressed. The portion B where the wiring defect prevention means 100 is formed corresponds to the inclined surface of the glass panel (see the portion B in FIG. 3).

図６において、Ａ部分は、銅箔パターン１３８がソルダレジスト１２０により覆われる部分を示し、Ｂ部分は、ソルダレジスト１２０により覆われずに外部に露出されるが、ガラスパネルにある透明回路パターン（図３の５２を参照）とは連結されていない部分を示し、Ｃ部分は、ガラスパターンの透明回路パターンと導電性を有する異方性接着剤により連結される部分をそれぞれ示す。   In FIG. 6, A part shows the part where the copper foil pattern 138 is covered with the solder resist 120, and B part is exposed outside without being covered with the solder resist 120, but the transparent circuit pattern ( (Refer to 52 in FIG. 3) indicates a portion that is not connected, and a portion C indicates a portion that is connected to the transparent circuit pattern of the glass pattern by an anisotropic adhesive having conductivity.

図７ないし図９は、本発明の他の実施形態によるテープパッケージの出力リード配線の終端を示す平面図である。   7 to 9 are plan views showing terminations of output lead wires of a tape package according to another embodiment of the present invention.

図７ないし図９を参照すれば、図６は、ソルダレジスト１２０により覆われる領域部分でのみ拡張されたリード幅を有する場合であったのに対して、図７は、ソルダレジスト１２０が覆われる領域の全体で拡張されたリード幅を有する場合である。すなわち、ソルダレジスト１２０により覆われる領域内で全体的に銅箔パターン１３８のリード幅を延長できるならば、図７のように全体的に延長して使用してもよい。   Referring to FIGS. 7 to 9, FIG. 6 shows a case where the lead width is expanded only in a region covered by the solder resist 120, whereas FIG. 7 shows that the solder resist 120 is covered. This is a case where the lead width is expanded over the entire area. That is, as long as the lead width of the copper foil pattern 138 can be extended entirely within the region covered with the solder resist 120, it may be extended as shown in FIG.

導電性を有する異方性接着剤を使用して、テープパッケージの出力リード配線１３６をガラスパネルに付着するＯＬＢ工程は、熱を使用して付着がなされる。このとき、銅箔パターン１３８は、ベース基板１００に付着された状態で上部が図１０のようにソルダレジスト１２０により固定される。このとき、銅箔パターン１３０の熱膨張係数とベース基板１００の熱膨張係数との差により、膨脹及び収縮が起きる程度に差がある。これにより露出された銅箔パターン（図面のＢ部分）にストレスが集中される。   The OLB process for attaching the output lead wiring 136 of the tape package to the glass panel using an anisotropic adhesive having conductivity is performed using heat. At this time, the upper part of the copper foil pattern 138 is fixed to the base substrate 100 by the solder resist 120 as shown in FIG. At this time, there is a difference in the degree of expansion and contraction due to the difference between the thermal expansion coefficient of the copper foil pattern 130 and the thermal expansion coefficient of the base substrate 100. This concentrates stress on the exposed copper foil pattern (B portion of the drawing).

このような問題を防止するために、本発明では、図８のようにソルダレジスト１２０により覆われる銅箔パターン１３８を“Ｓ”字状に曲げた。したがって、ＯＬＢ工程で熱による収縮及び膨脹が起きて、その力がＡ領域にある銅箔パターン１３８に加えられるとき、“Ｓ”字状に曲げられている銅箔パターン１３８は、前記力によるストレスを吸収できる。このように、ストレスを吸収できる形態を“Ｓ”字状にすることは一例であり、色々に曲げられている形状に設計できる。   In order to prevent such a problem, in the present invention, the copper foil pattern 138 covered with the solder resist 120 is bent into an “S” shape as shown in FIG. Therefore, when shrinkage and expansion due to heat occur in the OLB process and the force is applied to the copper foil pattern 138 in the region A, the copper foil pattern 138 bent in an “S” shape is stressed by the force. Can be absorbed. Thus, the “S” -shaped form capable of absorbing stress is an example, and can be designed to be bent in various ways.

図９の場合は、拡張されたリード幅を有する配線欠陥防止手段１１０を楕円形に構成した例である。図９に示すように、銅箔パターン１３８の終端がガラスパターンにある透明回路パターンと１：１に整合されるサイズに形成できる条件内で、クラックやパターンのオープン問題が発生する領域Ｂにある拡張されたリード幅を有する配線欠陥防止手段１１０の形態は、線形的に大きくなるか、または曲線形に大きくなり、その他の多様な形状に変形が可能である。本実施形態では、前記銅箔パターン１３８の幅は、例示的な意味として使用し、その幅は多様な幅に変形できる。   The case of FIG. 9 is an example in which the wiring defect prevention means 110 having an expanded lead width is configured in an elliptical shape. As shown in FIG. 9, the end of the copper foil pattern 138 is in a region B where a crack or pattern open problem occurs within the condition that it can be formed in a size that matches 1: 1 with the transparent circuit pattern in the glass pattern. The form of the wiring defect prevention means 110 having an extended lead width can be linearly enlarged or can be curved, and can be modified into various other shapes. In this embodiment, the width of the copper foil pattern 138 is used as an exemplary meaning, and the width can be changed to various widths.

図１０は、図７の斜視図であり、図１１は、図１０のＸ−Ｘ’の断面図である。   10 is a perspective view of FIG. 7, and FIG. 11 is a cross-sectional view taken along line X-X ′ of FIG.

図１０及び図１１に示すように、ベース基板１００上に銅箔パターン１３８が付着されており、図面のＣ領域では、ソルダレジスト１２０により銅箔パターン１３８の上部が固定されたことを確認できる。前記銅箔パターン１３８で拡張されたリード幅を有する配線欠陥防止手段１１０は、図１１のように、前記ベース基板１００上で均一な厚さを有することが望ましい。   As shown in FIGS. 10 and 11, the copper foil pattern 138 is attached on the base substrate 100, and it can be confirmed that the upper portion of the copper foil pattern 138 is fixed by the solder resist 120 in the region C of the drawing. The wiring defect prevention means 110 having a lead width expanded by the copper foil pattern 138 preferably has a uniform thickness on the base substrate 100 as shown in FIG.

図１２は、ソルダバンプを利用して半導体チップが搭載されるＣｏＦ（Ｃｈｉｐ ｏｎ Ｆｉｌｍ）パッケージの断面図であり、図１３は、ワイヤを通じて半導体チップが搭載されるＴＣＰ（Ｔａｐｅ Ｃａｒｒｉｅｒ Ｐａｃｋａｇｅ）の断面図である。   FIG. 12 is a cross-sectional view of a CoF (Chip on Film) package in which a semiconductor chip is mounted using solder bumps, and FIG. 13 is a cross-sectional view of a TCP (Tape Carrier Package) in which the semiconductor chip is mounted through a wire. is there.

図１２は、ソルダバンプ１２８を利用して半導体チップ１３０を半導体チップ搭載領域（図５の１１８）に搭載して、封止樹脂１３２で半導体チップ１３０を密封させて形成したＣｏＦパッケージ１５０である。このとき、前記半導体チップ１３０にあるソルダバンプ１２８が連結される半導体チップ搭載領域には、ソルダバンプ１２８と電気的連結のためのランドが形成されていることが望ましい。前記ランドは、電気的な連結能力の改善及び吸着性の改善のために表面にメッキ処理されたものが適している。前記表面処理は、金、スズ及びパラジウムのうちから選択された一つの金属あるいはそれを含む合金を使用してメッキ処理できる。   FIG. 12 shows a CoF package 150 formed by mounting the semiconductor chip 130 on the semiconductor chip mounting region (118 in FIG. 5) using the solder bump 128 and sealing the semiconductor chip 130 with the sealing resin 132. At this time, it is preferable that a land for electrical connection with the solder bump 128 is formed in the semiconductor chip mounting region to which the solder bump 128 on the semiconductor chip 130 is connected. The land is preferably plated on the surface in order to improve electrical connection ability and adsorption. The surface treatment may be performed using one metal selected from gold, tin and palladium or an alloy containing the same.

図１３は、ワイヤ１２６を利用して半導体チップ１３０を半導体チップ搭載領域（図５の１１８）に接着手段１２４で搭載させた後、封止樹脂１３２で半導体チップ１３０とワイヤ１２６とを密封させたＴＣＰ１５１である。図１２及び図１３には、出力リード配線の終端に本発明による拡張されたリード幅を有する配線欠陥防止手段１１０がそれぞれ形成されており、図面の１００はベースフィルムを、１３８は銅箔パターンを、１２０はソルダレジストをそれぞれ示す。   In FIG. 13, the semiconductor chip 130 is mounted on the semiconductor chip mounting region (118 in FIG. 5) by the bonding means 124 using the wire 126, and then the semiconductor chip 130 and the wire 126 are sealed with the sealing resin 132. TCP151. 12 and 13, wiring defect prevention means 110 having an extended lead width according to the present invention is formed at the end of the output lead wiring, respectively, in which 100 is a base film and 138 is a copper foil pattern. , 120 indicate solder resists, respectively.

本発明による拡張されたリード幅を有する配線欠陥防止手段の効果を確認するために、次のような実験を進めた。まず、テープパッケージで、出力リード配線の幅が図４のように一定なサイズを有するテープパッケージを準備した。そして、本発明のように、出力リード配線に拡張されたリード幅を有する配線欠陥防止手段が追加されたテープパッケージを準備した。次いで、ソルダレジストのある領域（図６のＣ）を固定させ、ガラスパネルの透明回路パターンと連結される領域（図６のＡ）を時計錘として、ベース基板を１８０°に反復的に曲げるベンディング検査を進めた。これにより、前記クラック欠陥が頻繁に発生する領域Ｂにストレスを集中させた。   In order to confirm the effect of the wiring defect prevention means having the extended lead width according to the present invention, the following experiment was advanced. First, a tape package having a fixed size as shown in FIG. 4 was prepared as the width of the output lead wiring. Then, as in the present invention, a tape package was prepared in which wiring defect prevention means having an extended lead width was added to the output lead wiring. Next, the solder resist resist region (C in FIG. 6) is fixed, and the base substrate is repeatedly bent to 180 ° using the region (A in FIG. 6) connected to the transparent circuit pattern of the glass panel as a clock spindle. The inspection proceeded. As a result, stress was concentrated on the region B where the crack defects frequently occur.

次いで、クラックが発生する程度を点検した結果、図４のように一定な出力リード配線の幅を有する場合は、平均的に４０回のベンディング検査でクラックが発生し、本発明のように拡張されたリード幅を有する配線欠陥防止手段が設けられた場合は、平均的に６０回のベンディング検査でクラックが発生することが確認された。これにより、本発明は、従来の技術と比較してクラックの発生頻度において、約５０％の改善が起きたことを類推して解釈できる。   Next, as a result of checking the extent of occurrence of cracks, if the width of the output lead wiring is constant as shown in FIG. 4, the cracks are generated on average by 40 bending inspections and are expanded as in the present invention. On the other hand, it was confirmed that cracks occurred on average by 60 bending inspections when the wiring defect prevention means having a large lead width was provided. As a result, the present invention can be interpreted by analogy with an improvement of about 50% in the occurrence frequency of cracks compared to the conventional technique.

本発明は、前記した実施形態に限定されず、当業者により多様な変形が可能であることが明白である。   It is obvious that the present invention is not limited to the above-described embodiments, and various modifications can be made by those skilled in the art.

本発明は、半導体素子関連の技術分野に適用可能である。   The present invention is applicable to a technical field related to semiconductor elements.

一般的なテープパッケージが使われるＦＰＤの内部構造を説明するための斜視図である。It is a perspective view for demonstrating the internal structure of FPD in which a general tape package is used. 一般的なテープパッケージの平面図である。It is a top view of a general tape package. テープパッケージがＦＰＤのガラスパネルに付着されることを示す断面図である。It is sectional drawing which shows that a tape package is attached to the glass panel of FPD. 一般的なテープパッケージの出力リード配線の終端を示す平面図である。It is a top view which shows the termination | terminus of the output lead wiring of a general tape package. 本発明によるテープパッケージの平面図である。It is a top view of the tape package by this invention. 本発明の一実施形態によるテープパッケージの出力リード配線の終端を示す平面図である。It is a top view which shows the termination | terminus of the output lead wiring of the tape package by one Embodiment of this invention. 本発明の他の実施形態によるテープパッケージの出力リード配線の終端を示す平面図である。It is a top view which shows the termination | terminus of the output lead wiring of the tape package by other embodiment of this invention. 本発明の他の実施形態によるテープパッケージの出力リード配線の終端を示す平面図である。It is a top view which shows the termination | terminus of the output lead wiring of the tape package by other embodiment of this invention. 本発明の他の実施形態によるテープパッケージの出力リード配線の終端を示す平面図である。It is a top view which shows the termination | terminus of the output lead wiring of the tape package by other embodiment of this invention. 図７の斜視図である。FIG. 8 is a perspective view of FIG. 7. 図１０のＸ−Ｘ’の断面図である。It is sectional drawing of X-X 'of FIG. ソルダバンプを利用して半導体チップが搭載されるＣｏＦパッケージの断面図である。It is sectional drawing of the CoF package in which a semiconductor chip is mounted using a solder bump. ワイヤを通じて半導体チップが搭載されるＴＣＰの断面図である。It is sectional drawing of TCP with which a semiconductor chip is mounted through a wire.

符号の説明Explanation of symbols

１００ ベース基板
１１０ 配線欠陥防止手段
１２０ ソルダレジスト
１３０ 半導体チップ
１３４ 入力リード配線
１３６ 出力リード配線の終端
１３８ 出力リード配線（銅箔パターン） DESCRIPTION OF SYMBOLS 100 Base substrate 110 Wiring defect prevention means 120 Solder resist 130 Semiconductor chip 134 Input lead wiring 136 Termination of output lead wiring 138 Output lead wiring (copper foil pattern)

Claims (22)

柔軟性を有する絶縁材質のベース基板と、
前記ベース基板に形成された半導体チップ搭載領域と、
前記半導体チップ搭載領域に付着された半導体チップと、
前記半導体チップ搭載領域と電気的に連結されて駆動回路基板の方向に拡張される入力リード配線と、
前記半導体チップ搭載領域と電気的に連結されてガラスパネルの方向に拡張される出力リード配線と、
前記入力リード配線及び出力リード配線の終端を除いた部分を覆うソルダレジストと、
前記ソルダレジストにより覆われずに露出された出力リード配線の終端のうち、前記ガラスパネルの配線と連結されていない部分に形成され、拡張されたリード幅を有する配線欠陥防止手段と、を備えることを特徴とするテープパッケージ。 A flexible insulating base substrate; and
A semiconductor chip mounting region formed on the base substrate;
A semiconductor chip attached to the semiconductor chip mounting region;
An input lead wiring electrically connected to the semiconductor chip mounting area and extending in the direction of the driving circuit board;
An output lead wiring electrically connected to the semiconductor chip mounting region and extending in the direction of the glass panel;
A solder resist covering a portion excluding the terminal ends of the input lead wiring and the output lead wiring;
Wiring defect prevention means having an extended lead width formed at a portion not connected to the wiring of the glass panel among the terminal ends of the output lead wiring exposed without being covered with the solder resist. Tape package characterized by 前記ソルダレジストにより覆われずに露出された出力リード配線の終端は、“Ｙ”字状を有することを特徴とする請求項１に記載のテープパッケージ。   2. The tape package according to claim 1, wherein an end of the output lead wiring exposed without being covered with the solder resist has a “Y” shape. 前記配線欠陥防止手段の拡張されたリード幅は、前記出力リード配線の終端で前記ガラスパネルの配線と連結される部分のリード幅より広いことを特徴とする請求項１に記載のテープパッケージ。   2. The tape package according to claim 1, wherein an extended lead width of the wiring defect prevention means is wider than a lead width of a portion connected to the glass panel wiring at the end of the output lead wiring. 前記配線欠陥防止手段の拡張されたリード幅は、前記ソルダレジストにより覆われる出力リード配線の幅より広いことを特徴とする請求項１に記載のテープパッケージ。   2. The tape package according to claim 1, wherein an extended lead width of the wiring defect prevention means is wider than a width of an output lead wiring covered with the solder resist. 前記ベース基板の絶縁材質は、ポリイミド及びエポキシ系樹脂のうちいずれか一つであることを特徴とする請求項１に記載のテープパッケージ。   The tape package according to claim 1, wherein the insulating material of the base substrate is any one of polyimide and epoxy resin. 前記ガラスパネルは、前記出力リード配線と連結される終端に傾斜面が形成されたことを特徴とする請求項１に記載のテープパッケージ。   The tape package according to claim 1, wherein the glass panel has an inclined surface formed at a terminal end connected to the output lead wiring. 前記半導体チップは、前記半導体チップ搭載領域とワイヤを通じて電気的に連結されることを特徴とする請求項１に記載のテープパッケージ。   The tape package according to claim 1, wherein the semiconductor chip is electrically connected to the semiconductor chip mounting region through a wire. 前記半導体チップは、前記半導体チップ搭載領域とソルダバンプを通じて電気的に連結されることを特徴とする請求項１に記載のテープパッケージ。   The tape package according to claim 1, wherein the semiconductor chip is electrically connected to the semiconductor chip mounting region through a solder bump. 前記半導体チップ搭載領域は、半導体チップのソルダバンプが連結されうるランドが形成されたことを特徴とする請求項８に記載のテープパッケージ。   The tape package according to claim 8, wherein the semiconductor chip mounting region is formed with lands to which solder bumps of the semiconductor chip can be connected. 前記ランドは、半導体チップにあるソルダバンプがよく接着されるように表面処理されたことを特徴とする請求項９に記載のテープパッケージ。   The tape package according to claim 9, wherein the land is surface-treated so that solder bumps on a semiconductor chip are well adhered. 前記表面処理は、金、スズ及びパラジウムのうちから選択された一つの金属を利用したメッキ処理であることを特徴とする請求項１０に記載のテープパッケージ。   The tape package according to claim 10, wherein the surface treatment is a plating treatment using one metal selected from gold, tin, and palladium. 前記ソルダレジストにより覆われる出力リード配線は、ボンディング時に使われる熱によるストレスが吸収可能な“Ｓ”字状であることを特徴とする請求項１に記載のテープパッケージ。   The tape package according to claim 1, wherein the output lead wiring covered with the solder resist has an “S” shape capable of absorbing stress due to heat used during bonding. 前記テープパッケージは、前記半導体チップを密封する封止樹脂をさらに備えることを特徴とする請求項１２に記載のテープパッケージ。   The tape package according to claim 12, wherein the tape package further comprises a sealing resin for sealing the semiconductor chip. 前記拡張されたリード幅を有する配線欠陥防止手段は、前記ベース基板上で厚さが均一であることを特徴とする請求項１に記載のテープパッケージ。   The tape package according to claim 1, wherein the wiring defect preventing means having the expanded lead width has a uniform thickness on the base substrate. 前記テープパッケージは、ＴＣＰであることを特徴とする請求項１に記載のテープパッケージ。   The tape package according to claim 1, wherein the tape package is TCP. 前記テープパッケージは、ＣｏＦであることを特徴とする請求項１２に記載のテープパッケージ。   The tape package according to claim 12, wherein the tape package is CoF. 柔軟性を有する絶縁材質のベース基板と、
前記ベース基板に形成された半導体チップ搭載領域と、
前記半導体チップ搭載領域に付着された半導体チップと、
前記半導体チップ搭載領域と電気的に連結されてディスプレイ駆動回路基板の方向に拡張される入力リード配線と、
前記半導体チップ搭載領域と電気的に連結されてガラスパネルの方向に拡張される出力リード配線と、
前記入力リード配線及び出力リード配線の終端を除いた部分を覆うソルダレジストと、
前記入力リード配線及び出力リード配線に形成され、拡張されたリード幅を有する配線欠陥防止手段と、を備えることを特徴とするテープパッケージ。 A flexible insulating base substrate; and
A semiconductor chip mounting region formed on the base substrate;
A semiconductor chip attached to the semiconductor chip mounting region;
An input lead wiring electrically connected to the semiconductor chip mounting area and extending in the direction of the display driving circuit board;
An output lead wiring electrically connected to the semiconductor chip mounting region and extending in the direction of the glass panel;
A solder resist covering a portion excluding the terminal ends of the input lead wiring and the output lead wiring;
A tape package comprising: wiring defect prevention means formed on the input lead wiring and the output lead wiring and having an extended lead width. 前記拡張されたリード幅を有する配線は、前記ソルダレジストにより覆われる領域でボンディング時に使われる熱によるストレスが吸収可能な“Ｓ”字状であることを特徴とする請求項１７に記載のテープパッケージ。   18. The tape package according to claim 17, wherein the wiring having the expanded lead width has an "S" shape capable of absorbing stress due to heat used during bonding in a region covered with the solder resist. . 前記テープパッケージは、前記半導体チップを密封する封止樹脂をさらに備えることを特徴とする請求項１７に記載のテープパッケージ。   The tape package according to claim 17, further comprising a sealing resin that seals the semiconductor chip. 前記配線欠陥防止手段の拡張されたリード幅は、前記入力リード配線及び出力リード配線の終端で前記駆動回路基板及びガラスパネルの配線と連結される部分のリード幅より広いことを特徴とする請求項１７に記載のテープパッケージ。   The extended lead width of the wiring defect prevention means is wider than a lead width of a portion connected to the wiring of the driving circuit board and the glass panel at the end of the input lead wiring and the output lead wiring. The tape package according to 17. 前記拡張されたリード幅を有する配線欠陥防止手段は、前記ソルダレジストにより覆われる領域に形成されたことを特徴とする請求項１７に記載のテープパッケージ。   18. The tape package according to claim 17, wherein the wiring defect prevention means having the expanded lead width is formed in a region covered with the solder resist. 前記拡張されたリード幅を有する配線欠陥防止手段は、前記ソルダレジストにより覆われていない領域に形成されたことを特徴とする請求項１７に記載のテープパッケージ。   18. The tape package according to claim 17, wherein the wiring defect prevention means having the expanded lead width is formed in a region not covered with the solder resist.
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Cited By (2)

* Cited by examiner, † Cited by third party
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