JP2006332604A5 - - Google Patents
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- JP2006332604A5 JP2006332604A5 JP2006104784A JP2006104784A JP2006332604A5 JP 2006332604 A5 JP2006332604 A5 JP 2006332604A5 JP 2006104784 A JP2006104784 A JP 2006104784A JP 2006104784 A JP2006104784 A JP 2006104784A JP 2006332604 A5 JP2006332604 A5 JP 2006332604A5
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- film
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- gate electrode
- insulating film
- density plasma
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Claims (8)
前記半導体膜上にゲート絶縁膜を形成し、
前記ゲート絶縁膜上にゲート電極を形成し、
前記ゲート電極表面を0.5eV以上1.5eV以下の電子温度で、かつ1.0×10 11 cm −3 以上1.0×10 13 cm −3 以下の電子密度の条件下の高密度プラズマにより窒化することによって前記ゲート電極の表面に窒化膜を形成することを特徴とする半導体装置の作製方法。 Forming a semiconductor film over a substrate having an insulating surface;
Forming a gate insulating film on the semiconductor film;
Forming a gate electrode on the gate insulating film;
The gate electrode surface is subjected to high-density plasma at an electron temperature of 0.5 eV to 1.5 eV and an electron density of 1.0 × 10 11 cm −3 to 1.0 × 10 13 cm −3. A method for manufacturing a semiconductor device, wherein a nitride film is formed on a surface of the gate electrode by nitriding.
前記半導体膜上にゲート絶縁膜を形成し、
前記ゲート絶縁膜上にゲート電極を形成し、
前記ゲート電極表面を0.5eV以上1.5eV以下の電子温度で、かつ1.0×10 11 cm −3 以上1.0×10 13 cm −3 以下の電子密度の条件下の高密度プラズマにより窒化することによって、前記ゲート電極の表面に窒化膜を形成し、
前記ゲート電極上に絶縁膜を形成し、
前記絶縁膜上に前記ソース領域または前記ドレイン領域と電気的に接続する配線を形成し、
前記配線表面を0.5eV以上1.5eV以下の電子温度で、かつ1.0×10 11 cm −3 以上1.0×10 13 cm −3 以下の電子密度の条件下の高密度プラズマにより窒化又は酸化することによって、前記配線表面に金属窒化膜又は金属酸化膜を形成することを特徴とする半導体装置の作製方法。 Forming a semiconductor film having a source region and a drain region over a substrate having an insulating surface;
Forming a gate insulating film on the semiconductor film;
Forming a gate electrode on the gate insulating film;
The gate electrode surface is subjected to high-density plasma at an electron temperature of 0.5 eV to 1.5 eV and an electron density of 1.0 × 10 11 cm −3 to 1.0 × 10 13 cm −3. By nitriding, a nitride film is formed on the surface of the gate electrode,
Forming an insulating film on the gate electrode;
Forming a wiring electrically connected to the source region or the drain region on the insulating film ;
The wiring surface is nitrided by high-density plasma at an electron temperature of 0.5 eV to 1.5 eV and an electron density of 1.0 × 10 11 cm −3 to 1.0 × 10 13 cm −3. Alternatively, a metal nitride film or a metal oxide film is formed on the surface of the wiring by oxidation.
前記半導体膜上にゲート絶縁膜を形成し、
前記ゲート絶縁膜上にゲート電極を形成し、
前記ゲート電極表面を0.5eV以上1.5eV以下の電子温度で、かつ1.0×10 11 cm −3 以上1.0×10 13 cm −3 以下の電子密度の条件下の高密度プラズマにより窒化することによって、前記ゲート電極の表面に窒化膜を形成し、
前記ゲート電極上に第1の絶縁膜を形成し、
前記第1の絶縁膜上に前記ソース領域または前記ドレイン領域と電気的に接続する配線を形成し、
前記配線表面を0.5eV以上1.5eV以下の電子温度で、かつ1.0×10 11 cm −3 以上1.0×10 13 cm −3 以下の電子密度の条件下の高密度プラズマにより窒化又は酸化することによって、前記配線表面に金属窒化膜又は金属酸化膜を形成し、
前記金属窒化膜又は金属酸化膜上に第2の絶縁膜を形成し、
前記第2の絶縁膜上に透明導電膜を形成し、
前記透明導電膜及び前記第2の絶縁膜を0.5eV以上1.5eV以下の電子温度で、かつ1.0×10 11 cm −3 以上1.0×10 13 cm −3 以下の電子密度の条件下の高密度プラズマにより窒化又は酸化することを特徴とする半導体装置の作製方法。 Forming a semiconductor film having a source region and a drain region over a substrate having an insulating surface;
Forming a gate insulating film on the semiconductor film;
Forming a gate electrode on the gate insulating film;
The gate electrode surface is subjected to high-density plasma at an electron temperature of 0.5 eV to 1.5 eV and an electron density of 1.0 × 10 11 cm −3 to 1.0 × 10 13 cm −3. By nitriding, a nitride film is formed on the surface of the gate electrode,
Forming a first insulating film on the gate electrode;
Forming a wiring electrically connected to the source region or the drain region on the first insulating film;
The wiring surface is nitrided by high-density plasma at an electron temperature of 0.5 eV to 1.5 eV and an electron density of 1.0 × 10 11 cm −3 to 1.0 × 10 13 cm −3. Or, by oxidizing, a metal nitride film or a metal oxide film is formed on the wiring surface,
Forming a second insulating film on the metal nitride film or metal oxide film;
Forming a transparent conductive film on the second insulating film;
The transparent conductive film and the second insulating film have an electron temperature of 0.5 eV to 1.5 eV and an electron density of 1.0 × 10 11 cm −3 to 1.0 × 10 13 cm −3. A method for manufacturing a semiconductor device, characterized by nitriding or oxidizing with high-density plasma under conditions .
前記高密度プラズマにより酸化するとき、酸素と希ガスとの混合ガス、又は酸素と水素と希ガスとの混合ガスを用いることを特徴とする半導体装置の作製方法。 In any one of Claims 2 thru | or 4,
A method for manufacturing a semiconductor device, which comprises using a mixed gas of oxygen and a rare gas or a mixed gas of oxygen, hydrogen, and a rare gas when oxidizing with the high-density plasma.
前記高密度プラズマにより窒化するとき、窒素と希ガスとの混合ガス、アンモニアと希ガスとの混合ガス、又は窒素と水素と希ガスとの混合ガスを用いることを特徴とする半導体装置の作製方法。 In any one of Claims 1 thru | or 5,
When nitriding with the high-density plasma, a mixed gas of nitrogen and a rare gas, a mixed gas of ammonia and a rare gas, or a mixed gas of nitrogen, hydrogen, and a rare gas is used. .
前記高密度プラズマにより窒化又は酸化するとき、前記基板を200℃から550℃の温度に加熱することを特徴とする半導体装置の作製方法。 In any one of Claims 1 thru | or 6,
A method for manufacturing a semiconductor device, wherein the substrate is heated to a temperature of 200 ° C. to 550 ° C. when nitriding or oxidizing with the high-density plasma.
前記ゲート電極の材料は、モリブデン、タングステン、クロム、タンタル、アルミニウムまたはシリコンであることを特徴とする半導体装置の作製方法。
In any one of Claims 1 thru | or 7 ,
A method for manufacturing a semiconductor device, wherein a material of the gate electrode is molybdenum, tungsten, chromium, tantalum, aluminum, or silicon.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006104784A JP5386058B2 (en) | 2005-04-28 | 2006-04-06 | Method for manufacturing semiconductor device |
Applications Claiming Priority (3)
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JP2005133688 | 2005-04-28 | ||
JP2005133688 | 2005-04-28 | ||
JP2006104784A JP5386058B2 (en) | 2005-04-28 | 2006-04-06 | Method for manufacturing semiconductor device |
Related Child Applications (1)
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JP2013154804A Division JP5690885B2 (en) | 2005-04-28 | 2013-07-25 | Manufacturing method of semiconductor device and semiconductor device |
Publications (3)
Publication Number | Publication Date |
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JP2006332604A JP2006332604A (en) | 2006-12-07 |
JP2006332604A5 true JP2006332604A5 (en) | 2009-05-21 |
JP5386058B2 JP5386058B2 (en) | 2014-01-15 |
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JP2006104784A Expired - Fee Related JP5386058B2 (en) | 2005-04-28 | 2006-04-06 | Method for manufacturing semiconductor device |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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JP7263470B2 (en) | 2007-03-26 | 2023-04-24 | 株式会社半導体エネルギー研究所 | semiconductor equipment |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
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KR100859113B1 (en) * | 2007-02-13 | 2008-09-18 | 홍익대학교부설과학기술연구소 | Organic Thin Film Transistor with a Controlled threshold Voltage and Preparing the Same |
JP5608347B2 (en) * | 2008-08-08 | 2014-10-15 | 株式会社半導体エネルギー研究所 | Semiconductor device and manufacturing method of semiconductor device |
JP5452343B2 (en) * | 2010-04-27 | 2014-03-26 | 株式会社ジャパンディスプレイ | Display device and manufacturing method thereof |
WO2011158704A1 (en) * | 2010-06-18 | 2011-12-22 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
KR101830170B1 (en) | 2011-05-17 | 2018-02-21 | 삼성디스플레이 주식회사 | Oxide semiconductor device, method of forming an oxide semiconductor device, and display device having an oxide semiconductor device, method of manufacturing a display device having an oxide semiconductor device |
JP6761276B2 (en) * | 2015-05-28 | 2020-09-23 | 株式会社半導体エネルギー研究所 | How to make a display device and how to make an electronic device |
CN110313057A (en) * | 2017-02-28 | 2019-10-08 | 夏普株式会社 | The manufacturing method of active-matrix substrate and the manufacturing method of organic EL display device |
US20190363172A1 (en) * | 2017-03-07 | 2019-11-28 | Sharp Kabushiki Kaisha | Method for manufacturing active matrix substrate, method for manufacturing organic el display device, and active matrix substrate |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH05150259A (en) * | 1991-11-27 | 1993-06-18 | Fujitsu Ltd | Liquid crystal display device and production thereof |
JP2895700B2 (en) * | 1993-01-20 | 1999-05-24 | シャープ株式会社 | Active matrix display device |
JPH0964034A (en) * | 1995-08-18 | 1997-03-07 | Toshiba Corp | Semiconductor device and manufacture thereof |
JP2000306860A (en) * | 1999-04-20 | 2000-11-02 | Nec Corp | Manufacture of semiconductor device |
JP4766724B2 (en) * | 1999-06-22 | 2011-09-07 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
TWI225668B (en) * | 2002-05-13 | 2004-12-21 | Tokyo Electron Ltd | Substrate processing method |
JP2004047549A (en) * | 2002-07-09 | 2004-02-12 | Seiko Instruments Inc | Method of manufacturing semiconductor device |
JP4358503B2 (en) * | 2002-12-12 | 2009-11-04 | 忠弘 大見 | Method for manufacturing nonvolatile semiconductor memory device |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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JP7263470B2 (en) | 2007-03-26 | 2023-04-24 | 株式会社半導体エネルギー研究所 | semiconductor equipment |
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