JP2006332097A - Semiconductor device and method for driving same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can transfer electrons with high precision, can operate at higher temperature and can be manufactured more easily. <P>SOLUTION: The semiconductor device comprises: a semiconductor layer 101; a p-type region 102 formed from the surface of the semiconductor layer 101; an n-type region 103 formed from the surface of the semiconductor layer 101 while spaced apart from the p-type region 102; a gate insulating layer 104 formed on the surface of the semiconductor layer 101; and a gate 105 formed on the gate insulating layer 104 between the p-type region 102 and the n-type region 103. In addition, one impurity 106 is introduced into a region within 30 nm from the surface of the semiconductor layer 101 between the p-type region 102 and the n-type region 103. The impurity 106 is introduced into a channel region between the p-type region 102 and the n-type region 103. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device for transferring electrons and a driving method thereof.

  A device (element) that transfers a single electron is called a single-electron device, and the most basic device is a three-terminal element called a single-electron transistor. As schematically shown in FIG. 5, the single electron transistor includes a source 501, a drain 502, a gate 503, and a single electron island 504 which is a core part. The single electron island 504 is a fine structure of a conductor also called a quantum dot or an artificial atom. If the single-electron island 504 is sufficiently small, when one electron enters the single-electron island 504 from the source 501, the potential energy of the single-electron island 504 increases greatly, and more electrons may enter the single-electron island 504. become unable.

  In other words, the single electron island 504 is largely negatively charged due to the entry of one electron, and new electrons cannot enter the single electron island 504 due to the electrostatic repulsive force due to the charging. This increase in potential energy is called charging energy. When the electrons that have entered the single-electron island 504 escape to the drain 502, the electrostatic repulsion is lost and new electrons enter the single-electron island 504. Thus, after the first electron passes through the single electron island 504, the next second electron can pass through the single electron island 504. In the single electron transistor, one electron passes through the single electron island 504. It becomes one by one.

  However, the above operation is not guaranteed unless the single electron island 504 is sufficiently small or the temperature is not sufficiently low. If the single-electron island 504 is not sufficiently small, the amount of increase in electrostatic energy (charging energy) is also small and the electrostatic repulsive force does not function well. Therefore, due to the thermal energy of the electrons, the repulsive force is overcome and the electrons mistakenly enter the single-electron island 504, which becomes a malfunction. This problem can be avoided by lowering the temperature to lower the thermal energy of the electrons, but this means device operation at a low temperature and is not practically preferable. For this reason, it is known that the single electron island 504 must be very small, and the diameter of the single electron island 504 must be 10 nm or less in order to guarantee an operation close to room temperature. .

  A single-electron transistor having a fine single-electron island 504 having a diameter of 10 nm or less has been prototyped at the research level, but has not yet been put into practical use. In addition, since the characteristics of the single-electron transistor depend sensitively on the size and shape of the single-electron island 504, in order to integrate the single-electron transistors, a technique for manufacturing the fine single-electron island 504 with high reproducibility is required. There is no such technology yet.

  In addition, it is known that the single-electron transistor having the above structure does not increase the accuracy of single-electron transfer in principle. In a single electron transistor, electrons are transferred one by one, but the time intervals of each electron transfer vary. For example, the transfer time cannot be divided and 10 electrons cannot be accurately transferred from the source to the drain. In order to increase the transfer accuracy, a more complicated structure than the single electron transistor is required. These are called single-electron transfer devices, and single-electron turn styles and single-electron pumps have been devised and demonstrated (see Non-Patent Document 1).

  As an example, FIG. 6 shows a single-electron turn style configuration. The element shown in FIG. 6 includes a source 601, a drain 602, a gate 603, and three single electron islands 641, 642, 643 connected in series. In this turn style, the gate 603 is coupled (capacitively coupled) to the central single-electron island 641, and when a clock voltage is applied to the gate 603, exactly one electron is generated at each rising and falling of the voltage. Can be transferred. For example, when 10 electrons are to be transferred, a clock voltage that rises and falls 10 times may be applied to the gate 603. Moreover, what is necessary is just to repeat ON / OFF of the element shown in FIG. 6 10 times.

L.J.Geerligs, et al., "Frequency-Locked Turnstile Device for Single Electron", Physical Review Letters, Vol.64, No.22, pp.2691-2694, 1990.

  As described above, according to the element shown in Non-Patent Document 1, it is possible to transfer electrons with high accuracy, but it is necessary to form three fine single-electron islands in series. Thus, it is more difficult to manufacture compared to a single electron transistor. As described above, conventionally, it has not been easy to realize a single-electron element using a fine single-electron island that can transfer electrons with high accuracy and can operate at a higher temperature.

  The present invention has been made to solve the above problems, and provides a semiconductor device that can transfer electrons with high accuracy, can operate at a higher temperature, and can be manufactured more easily. Objective.

  A semiconductor device according to the present invention includes a p-type region made of a semiconductor doped with p-type impurities, an n-type region made of a semiconductor doped with n-type impurities, a p-type region and an n-type in the first direction. A channel region made of a semiconductor disposed between the region, a gate electrode disposed on a second direction side perpendicular to the first direction of the channel region, and a channel region of 30 nm from an interface of the channel region on the gate electrode side And a known number of impurity atoms introduced into the range, the impurity atoms having an ionization energy of 0.1 eV or more and forming an impurity level in the channel region. For example, one impurity atom is introduced into the channel region. Therefore, when a gate voltage is applied to the gate electrode and an electron channel is formed from the n-type region, one (known number) of electrons in the formed electron channel is one (known number). Captured by impurity atoms.

  The semiconductor device may include a gate insulating layer disposed between the gate electrode and the channel region. This gate insulating layer may be made of a semiconductor having a wider band gap than the semiconductor constituting the channel region. When the channel region is made of silicon, the impurity atom may be at least one of indium and thallium.

  The semiconductor device further includes another gate electrode arranged opposite to the gate electrode in the channel region, and the channel region has a layer thickness in the second direction of 60 nm at most. You may make it. In this case as well, another gate insulating layer disposed between another gate electrode and the channel region may be provided, and the other gate insulating layer has a wider band gap than the semiconductor constituting the channel region. You may be comprised from the semiconductor.

  A method for driving a semiconductor device according to the present invention is a method for driving a semiconductor device having the above-described configuration, which is equal to or higher than a threshold at which an electron channel is formed by electrons supplied from an n-type region in a gate electrode. The first gate voltage and the second gate voltage below the threshold value at which a hole channel is formed by holes supplied from the p-type region are alternately applied.

  In addition, a driving method of a semiconductor device according to the present invention is a method of driving a semiconductor device having the above-described structure, in which a potential difference at two interfaces between a gate electrode side of a channel region and another gate electrode side causes the channel region to A first gate voltage is applied to the other gate electrode so as not to exceed the band gap of the constituent semiconductor, and the gate electrode is applied to the gate electrode from the n-type region in a state where the first gate voltage is applied to the other gate electrode. A second gate voltage equal to or higher than a threshold value at which an electron channel is formed by the supplied electrons, and a third gate voltage equal to or lower than a threshold value at which a hole channel is formed from holes supplied from the p-type region. They are applied alternately.

  As described above, according to the present invention, one impurity atom introduced in a range of 30 nm from the interface on the gate electrode side of the channel region is provided, and the impurity atom has an ionization energy of 0.1 eV or more. Since the impurity level is formed in the channel region, a semiconductor device capable of transferring electrons with high accuracy and operating at a higher temperature can be manufactured more easily. can get.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a configuration diagram illustrating a configuration example of a semiconductor device according to an embodiment of the present invention. Here, a single electronic device will be described as an example. 1 includes a semiconductor layer 101 made of, for example, silicon, a p-type region 102 formed in the semiconductor layer 101, and an n-type region 103 formed in the semiconductor layer 101 apart from the p-type region 102. And a gate insulating layer 104 formed on the main surface of the semiconductor layer 101, and a gate electrode 105 formed on the semiconductor layer 101 between the p-type region 102 and the n-type region 103. In the single electronic device shown in FIG. 1, the gate electrode 105 is formed on the main surface of the semiconductor layer 101 with the gate insulating layer 104 interposed therebetween.

  In addition, the single-electron device shown in FIG. 1 is introduced 1 into a region within 30 nm from the main surface of the semiconductor layer 101 sandwiched between the p-type region 102 and the n-type region 103, that is, the surface on the gate electrode 105 side. An impurity (impurity atom) 106 is provided. The impurity 106 is introduced into a channel region sandwiched between the p-type region 102 and the n-type region 103 to form an impurity level. Note that the gate electrode 105 is coupled (capacitively coupled) to the channel region into which the impurity 106 is introduced.

  For example, the semiconductor layer 101 is a silicon substrate (wafer), and a p-type region 102 can be formed by introducing a well-known p-type impurity into the predetermined region by a known ion implantation method or the like. The n-type region 103 can be formed by introducing a well-known n-type impurity. Here, in the single-electron device shown in FIG. 1, the p-type region 102 and the n-type region 103 are arranged so as to sandwich the semiconductor (channel region), and the gate is formed on the channel region in the direction perpendicular to the arrangement direction. In this configuration, the electrode 105 is disposed. Therefore, a p-type semiconductor and an n-type semiconductor may be arranged so as to sandwich a channel region made of a predetermined semiconductor, and the above structure may be adopted. In this case, the channel region, the p-type semiconductor, and the n-type semiconductor need not be made of the same semiconductor.

  Further, the gate insulating layer 104 can be formed by thermally oxidizing the surface of the silicon substrate (semiconductor layer 101) to form an oxide film. Note that the gate insulating layer 104 may be formed by a deposition method such as chemical vapor deposition, or may be formed of another semiconductor material having a wider band gap than the semiconductor layer 101 (channel region). Here, the “interface” described below indicates the interface between the gate insulating layer and the semiconductor layer. Alternatively, a gate electrode that is Schottky connected to the semiconductor layer may be used. In this case, the “interface” described below indicates the interface between the semiconductor layer and the gate electrode. On the other hand, the impurity 106 may be activated by implanting single ions into the semiconductor layer 101 (channel region) using a single ion implantation technique and performing an annealing process after the implantation. The introduction of the impurity 106 is performed before the gate electrode 105 is formed.

Next, an example of the operation (driving method) of the above-described single electronic element will be described. 2A to 2E, (a ′) to (e ′) indicate the surface of the semiconductor layer 101 (with the insulating layer 104) in the semiconductor layer 101 (channel region) sandwiched between the p-type region 102 and the n-type region 103. It is a potential diagram showing the potential in the vicinity of the interface). First, as shown in FIGS. 2A and 2A ′, in the initial state, the gate electrode 105 has, for example, about 0 V, an electron channel threshold V _th-n, and a hole channel threshold. It is assumed that a gate voltage having an intermediate value between the value V _th-p is applied. Note that V _th-n > V _th-p . In this state, neither the electron channel nor the hole channel is open, and the impurity 106 is not trapped at all.

Next to the initial state, as shown in FIGS. 2B and 2B ′, a gate voltage having a magnitude exceeding the threshold V _th-n of the electron channel is applied to the gate electrode 105. . By application of this gate voltage, electrons are supplied from the n-type region 103 to the channel region under the gate electrode 105 to form the electron channel 131. The electron channel 131 is formed in the conduction band of the semiconductor constituting the semiconductor layer 101. At this time, one electron is trapped in the impurity 106 from the formed electron channel 131. After one electron is trapped in the impurity 106 in this way, when the gate voltage similar to the initial state is applied to the gate electrode 105, the electron supplied as the electron channel 131 (in the conductor) Electrons) are collected in the n-type region 103. However, as shown in FIGS. 2C and 2C ′, the electrons trapped in the impurity 106 are trapped in the impurity 106 without returning to the n-type region 103 due to finite ionization energy. It will be in a state as it is.

In this manner, the gate voltage having a value lower than the threshold value V _th-p of the hole channel is applied to the gate electrode 105 in a state where electrons are trapped in the impurity 106. By applying this gate voltage, holes are supplied from the p-type region 102 to the channel region below the gate electrode 105 to form a hole channel 121 as shown in FIG. The hole channel 121 is formed in the valence band of the semiconductor constituting the semiconductor layer 101. By the formation of the hole channel 121, the electrons trapped in the impurity 106 are recombined with the supplied holes. In other words, the electrons trapped in the impurity 106 move to the valence band.

  As described above, after the electrons trapped in the impurity 106 are moved to the valence band and then the gate voltage similar to the initial state is applied to the gate electrode 105, the hole channel 121 is closed. The holes in the valence band are recovered in the p-type region 102. As a result, as shown in FIGS. 2E and 2E ′, the impurity 106 is not trapped at all, and one electron is transferred from the n-type region 103 to the p-type region 102. It has flowed (transferred). Note that in the above-described operation, the voltages in the n-type region 103 and the p-type region 102 may both be about 0V. In addition, a voltage of about ± 0.1 V may be applied between the n-type region 103 and the p-type region 102.

  Hereinafter, the impurity 106 will be described in more detail. In the transfer operation described with reference to FIG. 2, in order to transfer electrons with higher accuracy, the impurity 106 needs to have a high capture cross section for both electrons and holes. In other words, the electronic state of the impurity 106 must be well coupled with both the conduction band and valence band electronic states. For this purpose, an impurity having a deeper level is suitable.

  For example, when the semiconductor layer 101 is made of silicon, phosphorus and boron are a donor and an acceptor having shallow levels, respectively. Among them, phosphorus has a level at a position of about 45 meV below the silicon conduction band. In this case, the electronic state of the phosphorus donor can be well described by superposition of the electronic states of the conduction band. For this reason, it is possible to easily capture conduction electrons. On the other hand, a phosphorus donor has a very small hole cross-sectional area in the valence band. An acceptor having a shallow level such as boron with respect to such phosphorus has a large valence band hole capture cross section, but a small conduction band electron capture cross section and a small conduction band electron capture probability. .

  In contrast to the above-described impurity having a shallow level, the electronic state of the impurity 106 having a deep level is described using both the conduction band and valence band states, and therefore, both electron and hole trapping are interrupted. Large area. In this way, single-electron transfer can be performed with higher accuracy by using impurities having deep levels. In order to realize single-electron transfer, the ionization energy (level of the ground state) of the impurity 106 is 0.1 eV or more. is necessary.

  In the case of a donor having a shallow level, even if a conduction band electron is trapped, there is a probability that the trapped electron is re-emitted due to thermal noise when the electron channel is closed and the electron is collected in the n-type electrode. Get higher. For this reason, in a shallow level donor, transfer accuracy deteriorates. Similarly, in the case of an acceptor having a shallow level, there is a high probability that holes will be re-emitted due to thermal noise, resulting in poor transfer accuracy. On the other hand, the deeper level the impurity 106 is, the more suitable for high temperature operation. For stable operation, ionization energy of about four times the thermal energy is necessary. To realize operation at room temperature, the ionization energy (ground state level) of the impurity 106 is still 0. 1 eV or more is required.

  In addition, the position of the impurity 106 atoms in the semiconductor (semiconductor layer 101) is limited only in the depth direction, and the distance from the semiconductor interface (the surface of the semiconductor layer 101 on the gate electrode 105 side) is within 30 nm. There must be. This is because an overlap between the channel electron or hole and the electron wave function of the impurity 106 is required to capture electrons or holes between the channel formed at the interface. It is. The spread of the wave function of electrons trapped in the impurity 106 is about 10 nm, and the spread of the wave function of electrons and holes in the channel is about 5 nm. If the distance is less than about twice the sum of these, sufficient trapping is possible. Does not happen. Note that the spread of the wave function of an impurity having an ionization energy of 0.1 eV or more strongly reflects the nature of the impurity itself, and does not depend much on the nature of the semiconductor serving as a base material. In addition, the spread of the wave functions of channel electrons and holes does not depend strongly on the type of semiconductor. For this reason, the above-mentioned conditions for the distance from the interface (surface) of 30 nm are not related to the type of semiconductor.

  On the other hand, as long as it is a region under the gate electrode 105 where the channel is formed, it is disposed at any position on a plane perpendicular to the depth direction (direction from the p-type region 102 to the n-type region 103). I do not care. For example, the impurity 106 may be located near the p-type region 102, located near the n-type region 103, or in the center. This makes it very easy to manufacture the device. Note that if the distance between the p-type region 102 and the n-type region 103 is large, a longer time is required due to the return of the electron channel and hole channel formed during operation, resulting in a decrease in operation speed. On the other hand, if the distance between the p-type region 102 and the n-type region 103 is much smaller than 30 nm from the viewpoint of the spread of the wave function of the impurity 106 described above, the operation of the element may be affected.

  According to the single electron device shown in FIG. 1, a single impurity atom in the channel region under the gate electrode corresponds to a single electron island in the conventional single electron transfer device. In the conventional single-electron device, the size and shape of the single-electron island dominate the characteristics of the element, and these controls have been a big problem. On the other hand, according to the single electron device shown in FIG. 1, the size and shape of the portion corresponding to the single electron island constituted by the impurity atoms are defined by the spread and shape of the wave function of the electrons trapped by the impurities, The ionization energy corresponds to the charging energy. Needless to say, these quantities are uniquely determined by the inherent properties of the impurity atoms and need not be controlled. Therefore, according to the single electronic device shown in FIG. 1, it can be easily manufactured, and the variation in characteristics due to the manufacturing is very small, and large-scale integration is possible.

  Next, another semiconductor device according to the embodiment of the present invention will be described. FIG. 3 is a configuration diagram showing a configuration example of another semiconductor device according to the embodiment of the present invention. Here, a single electronic device will be described as an example. 3 includes, for example, a semiconductor layer 301 made of silicon, a p-type region 302 formed in the semiconductor layer 301, and an n-type region 303 formed in the semiconductor layer 301 so as to be separated from the p-type region 302. A gate insulating layer 304 formed on one surface of the semiconductor layer 301, and a first gate electrode 305 formed on the gate insulating layer 304 between the p-type region 302 and the n-type region 303. Prepare.

  3 is formed on the gate insulating layer 307 formed on the other surface of the semiconductor layer 301 and the gate insulating layer 307 between the p-type region 302 and the n-type region 303. The second gate electrode 308 is provided, and two gate electrodes are provided. In addition, the single-electron element shown in FIG. 3 also includes one impurity 306 introduced into a region within 30 nm from both surfaces of the semiconductor layer 301 sandwiched between the p-type region 302 and the n-type region 303. Yes. The impurity 306 is introduced into a channel region sandwiched between the p-type region 302 and the n-type region 303. In the single-electron device shown in FIG. 3, the gate insulating layer 304 and the gate insulating layer 307 may be made of another semiconductor material having a wider band gap than the semiconductor layer 301 (channel region), for example.

Hereinafter, an operation example (an example of a driving method) of the single electronic element shown in FIG. 3 will be described with reference to FIG. FIG. 4 is a distribution diagram showing the potential distribution in the film thickness direction in the semiconductor layer 301. First, in the initial state, the gate voltage applied to the first gate electrode 305 includes an electron channel threshold V _th-n and a hole channel threshold V _th-p (V _th-n > V _{th- p} ) Set to an intermediate value. In such a driving state, as shown in FIG. 4A, neither the electron channel nor the hole channel is open, and no electrons are trapped in the impurity 306. Further, an offset voltage is applied to the second gate electrode 307 in this initial state. The magnitude of this offset voltage is set so that the potential difference between the two interfaces does not exceed the band gap of the semiconductor constituting the semiconductor layer 301. The value of the offset voltage that satisfies such conditions can be easily calculated.

For example, in the single electronic device shown in FIG. 3, the electric field strength in the semiconductor layer 301 is E _s , the band gap of the semiconductor layer 301 is E _g , the thickness of the semiconductor layer 301 is t _s , and the dielectric constant of the semiconductor layer 301 is ε _s , where the dielectric constant of the gate insulating layer 304 and the gate insulating layer 307 is ε _D , the thickness of the gate insulating layer 304 is t _D1 , and the thickness of the gate insulating layer 307 is t _D2 , the gate insulating layer 304 and the gate insulating layer field strength E _D 307, using the field strength E _D of the semiconductor, so is represented as _{(ε s / ε D) E} s, the offset voltage V _{G2, "V G2 = E s t s +} (ε _{s / εD) E s (t} D1 + t D2) = [t s + (ε s / ε D) (t D1 + t D2)] is expressed as E _s ". Therefore, the allowable maximum value V _G2-max of the offset voltage applied to the second gate electrode 307 is “[t _s + (ε _s / ε _D ) (t _D1 + t _D2 )] E _g / t _s ”. . The offset voltage may be positive or negative. When the offset voltage is set to be negative, the allowable minimum value V _G2-min is “− [t _s + (ε _s / ε _D ) (t _D1 + t _D2 )] E _g / t _s ”. The above is the initial voltage setting. Hereinafter, a case where the offset voltage is negative will be described.

As described above, a positive voltage is applied to the first gate electrode 305 after the initial state in which each gate voltage is applied. This positive voltage has a magnitude exceeding the threshold value V _th-n of the electron channel. By this voltage application, as shown in FIG. 4B, an electron channel 331 is formed at the interface on the first gate electrode 305 side (the surface of the semiconductor layer 301), and electrons are supplied from the n-type region 303. At this time, one electron is trapped in the impurity 306 from the electron channel 331. Thereafter, when the gate voltage applied to the first gate electrode 305 is returned to the initial state, the electron channel 331 is closed, and electrons in the semiconductor conductor are collected in the n-type region 303, but trapped in the impurity 306. The emitted electrons cannot return to the n-type region 303 due to the finite ionization energy (FIG. 4C).

Next, a negative voltage is applied to the first gate electrode 305. This negative gate voltage is set to a value lower than the threshold value V _th-p of the hole channel. By applying this gate voltage, a hole channel 321 is formed at the interface (the surface of the semiconductor layer 301) on the second gate electrode 308 side, and holes are supplied from the p-type region 302, as shown in FIG. The supplied holes recombine with the trapped electrons. In other words, the electrons trapped in the impurity 306 move to the valence band of the semiconductor.

  Thereafter, when the gate voltage applied to the first gate electrode 305 is returned to the initial state again, the hole channel 321 is closed, and holes in the valence band of the semiconductor are collected in the p-type region 302 (FIG. 4). (E)). Thus, one transfer cycle is completed, and one electron flows (transferred) from the n-type region 303 to the p-type region 302 from the state shown in FIG. Note that during the above-described operation procedure, the voltages of the n-type region 303 and the p-type region 302 may both be set to 0V. Alternatively, a voltage of about ± 0.1 V may be applied between the n-type region 303 and the p-type region 302.

  In the above cycle (one cycle), the location where the electron channel and the hole channel are formed is different. Therefore, the interface state localized at the interface (the surface of the semiconductor layer 301) contributes to the transfer of electrons. Can not do it. For example, an interface state present at the interface on the first gate electrode 305 side can trap electrons, but these trapped electrons are holes formed at the interface on the opposite side (second gate electrode 307 side). It cannot recombine with the holes in the channel 321. Only the impurity levels present in the semiconductor can contribute to the transfer. As described above, according to the single-electron device shown in FIG. 3, the single-electron transfer accuracy is not affected by the interface state that may be introduced in the device creation stage, and higher transfer accuracy is achieved. It will be obtained.

The offset voltage to be applied in the initial state, the electric field strength in the semiconductor exceeds E _g / t _s, in other words, when the potential difference at both interfaces exceeds a band gap of the semiconductor, in the operation described above, the hole And there will be a state where both channels of electrons and electrons are opened simultaneously. In this case, a DC leakage current flows between the two channels via the impurity level, and the accuracy of single-electron transfer is deteriorated. For this reason, as described above, there is an upper limit value for the absolute value of the offset voltage.

  In order to perform single-electron transfer with high accuracy using impurity levels, the wave function of electrons trapped in the levels must overlap in both channels. For this reason, the impurities must be located within 30 nm from either interface. This condition simultaneously defines the thickness of the semiconductor (semiconductor layer 301), and the thickness of the semiconductor layer 301 needs to be at most 60 nm (60 nm or less).

  Next, impurities that trap electrons will be described in more detail. Impurities having a deep level of ionization energy of 0.1 eV or more include, for example, silicon as a semiconductor, a group III deep acceptor such as indium and thallium, and transitions such as manganese, iron, copper, and nickel Broadly divided into deep levels of metals. In silicon, there is no deep V group donor whose ionization energy exceeds 0.1 eV.

  First, when indium and thallium are introduced as impurities, they form a single level in the band gap of silicon, and there are two kinds of charged states of 0 and -1. For this reason, in the semiconductor device (single-electron element) shown in FIG. 1 using indium and thallium as the impurities 106, single-electron transfer is accurately performed if the driving conditions described with reference to FIG. 2 are satisfied. Can do.

  On the other hand, transition metals have a plurality of levels when introduced into silicon as impurities. For example, manganese in silicon has three levels and has four types of charge states of -1, 0, +1, and +2. For this reason, the number of electrons transferred at one time varies from 1 to a maximum of 3 depending on the sweep time of the gate voltage. If the sweep time is sufficiently long, three electrons are transferred, and the number of transferred electrons decreases as the time becomes shorter. For this reason, when manganese is used as the impurity 106, it is necessary to adjust the sweep time for accurate single electron transfer.

  Thus, the use of indium and thallium as impurities makes the gate voltage less dependent on the sweep time or less dependent on the frequency of the AC gate voltage, and enables stable operation. Indium and thallium (group III acceptor) have a diffusion coefficient in silicon that is significantly smaller than that of transition metals. For this reason, the diffusion distance by the heat treatment after ion implantation can be kept small, and the depth control of impurities can be easily performed.

  In the above description, the single-electron element is described as an example, but the present invention is not limited to this. For example, when two (or n) electrons are to be transferred in one cycle, two impurities or n impurities may be introduced into the semiconductor (channel region). The designed number of impurities may be introduced into the channel region, and the number of impurities introduced into the channel region may be in a known state. A reference current value is obtained by the semiconductor device shown in FIG. 1 by repeating the driving cycle described with reference to FIG. 2 in a state where a known number (specified number) of impurities are introduced into the channel region. Can be obtained. In this case, the type of each impurity may be the same or different. Moreover, the mutual positional relationship may or may not be correlated. Alternatively, they may be close or far from each other.

It is a block diagram which shows the structural example of the semiconductor device in embodiment of this invention. FIG. 2 is an explanatory diagram illustrating an example of operation (driving method) of the semiconductor device illustrated in FIG. 1. It is a block diagram which shows the structural example of the other semiconductor device in embodiment of this invention. FIG. 4 is a distribution diagram showing a potential distribution in a film thickness direction in a semiconductor layer 301 for explaining an example of an operation (driving method) of the semiconductor device shown in FIG. 3. It is a block diagram which shows simply the structure of the conventional single electronic element. It is a block diagram which shows the structure of a single electron turn style simply.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 ... Semiconductor layer, 102 ... P-type area | region, 103 ... N-type area | region, 104 ... Gate insulating layer, 105 ... Gate electrode.

Claims (10)

a p-type region made of a semiconductor doped with a p-type impurity;
an n-type region made of a semiconductor doped with an n-type impurity;
A channel region made of a semiconductor disposed between the p-type region and the n-type region in a first direction;
A gate electrode disposed on a second direction side perpendicular to the first direction of the channel region;
At least a known number of impurity atoms introduced in a range of 30 nm from the interface of the channel region on the gate electrode side,
The impurity atom has an ionization energy of 0.1 eV or more, and forms an impurity level in the channel region. The semiconductor device according to claim 1,
One of the impurity atoms is introduced into the channel region. A semiconductor device, wherein: The semiconductor device according to claim 1 or 2,
A semiconductor device comprising a gate insulating layer arranged between the gate electrode and the channel region. The semiconductor device according to claim 3.
The gate insulating layer is made of a semiconductor having a wider band gap than the semiconductor constituting the channel region. The semiconductor device according to any one of claims 1 to 4,
The channel region is made of silicon;
The semiconductor device, wherein the impurity atom is at least one of indium and thallium. The semiconductor device according to any one of claims 1 to 5,
Another gate electrode disposed opposite to the gate electrode on the opposite side of the channel region from the gate electrode;
A layer thickness of the channel region in the second direction is formed to be 60 nm at most. The semiconductor device according to claim 6.
A semiconductor device comprising: another gate insulating layer disposed between the other gate electrode and the channel region. The semiconductor device according to claim 7.
The other gate insulating layer is made of a semiconductor having a wider band gap than the semiconductor constituting the channel region. A method for driving a semiconductor device according to claim 1,
The gate electrode;
A first gate voltage equal to or higher than a threshold at which an electron channel is formed by electrons supplied from the n-type region;
A method for driving a semiconductor device, comprising: alternately applying a second gate voltage lower than a threshold value at which a hole channel is formed by holes supplied from the p-type region. A method for driving a semiconductor device according to claim 6, wherein:
A first gate voltage is set so that a potential difference at two interfaces between the gate electrode side and the other gate electrode side of the channel region does not exceed a band gap of a semiconductor constituting the channel region. Applied to
With the first gate voltage applied to the other gate electrode,
The gate electrode;
A second gate voltage equal to or higher than a threshold at which an electron channel is formed by electrons supplied from the n-type region;
A method for driving a semiconductor device, comprising: alternately applying a third gate voltage lower than a threshold value at which a hole channel is formed by holes supplied from the p-type region.

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