JP2006330564A - Image display controller and image display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To lighten a burden of a CPU by constituting processing for displaying a video image read from a memory to a window of the optional shape with hardware. <P>SOLUTION: A display pixel position detection part 1 detects whether or not pixels of the video image displayed on a display device 12 is present in the respective rectangle areas set according to a plurality of window patterns WP (pattern) ("1" at the time of presence). An AND gate part 4 individually outputs AND between each output of the display pixel position detection part 1 and data (binary) of the plurality of patterns read from a window pattern memory 2. A read window number determination part 6 determines a window number provided to a pattern whose AND output is "1" according to priority of patterns. An address selector 8 selects one of a plurality of reading addresses corresponding to the respective window numbers generated by a reading address generation part 7 in order to read the video image from a video memory 9 by the window numbers. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an image display control apparatus and an image display apparatus that display an input image on a window having a specific pattern.

  2. Description of the Related Art Conventionally, some display devices that display a video signal input from the outside have a function of displaying an input image in an arbitrary window. According to such a function, the input image is partially displayed in the area in the window, and the visual fun can be expressed.

For example, Patent Document 1 discloses a configuration in which a window design is automatically changed in the same manner as a bitmap design stored in a memory. Further, Patent Document 2 discloses a configuration for displaying a screen displayed on a mobile phone in an arbitrary shape. Patent Document 3 discloses a configuration using a trimming window that displays a trimmed image in an arbitrary form.
JP 2001-242975 A (published on September 7, 2001) Japanese Patent Laid-Open No. 2001-14133 (published on January 19, 2001) JP 2001-14479 A (published January 19, 2001)

  However, in any of the above methods, since processing for displaying an image in a window having an arbitrary shape is performed by software, a moving image cannot be displayed as an input image when a low-performance CPU is used. If a high-speed and expensive CPU is used, a moving image can be displayed as an input image, but the load of display processing on the CPU is large, and the processing speed of the entire system is reduced.

  The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to configure the image display processing by software by configuring the processing for displaying the video image read from the memory in an arbitrary-shaped window with hardware. This is to avoid the above-mentioned inconvenience caused by the wear.

  An image display control device according to the present invention is an image display control device that reads an image stored in an image memory for display on the display device, and constitutes an image to be read from the image memory and displayed on the display device. A display pixel position determination circuit for determining whether or not a display position of pixel data to be present exists within a specific rectangular area, and a window image represented by binary data of a preset shape (pattern) A window image memory for storing the image, a logical product circuit for outputting a logical product of the output of the display pixel position determination circuit and the data of the window image read from the window image memory, and reading the image from the image memory A read address generating circuit for generating a read address for designating a storage area of pixel data to be read, and the output of the AND circuit is "1" It is characterized by comprising an address output control circuit for outputting the read address in a period of time.

  In the above configuration, the display pixel position determination circuit determines whether or not the pixel of the image to be displayed on the display device exists in each rectangular area set in accordance with the plurality of window images (when present, “1”). "). Then, the logical product outputs the logical product of the output of the display pixel position determination circuit and the window image data (binary data) read from the window image memory. Then, the address output control circuit outputs the read address from the read address generation circuit during the period when the output of the AND circuit is “1”. As a result, for the image read from the image memory, only the pixel data existing in the period during which the output of the AND circuit is “1”, that is, in the rectangular area and in the window image is read.

  In this way, by performing the process of reading an image in the shape of the window image with hardware, the burden on the CPU can be reduced.

  In the image display control device, the window image memory stores a plurality of window images, and the display pixel position detecting means performs pixel data for a plurality of rectangular areas set corresponding to the window images, respectively. For each window image, the logical product circuit determines, for each window image, the output of the display pixel position determination circuit and the window read from the window image memory. A logical product with the image data is output, and the read address generation circuit generates a read address for each window image, and the image display control device outputs each window image according to the priority assigned to each window image. A window image for determining a window image in which each output from the AND circuit for “1” is “1” Comprises a constant circuit, said address output control circuit preferably outputs the read address output corresponding to the determined window image with a "1" from the AND circuit.

  In this configuration, since a plurality of window images are prepared, it is necessary to determine which window image is used to display an image. For this reason, the display pixel position detecting means, the logical product circuit, the read address generating circuit, and the read address control circuit are configured as described above. The image display control device uses the window image determination circuit for the above determination. It has.

  First, the display pixel position determination circuit determines whether or not a pixel of a video image displayed on the display device is present in each rectangular area set in accordance with a plurality of window images. The logical product circuit individually outputs the logical product of each output of the display pixel position determination circuit and a plurality of window image data read from the window image memory. Then, the window image determination circuit determines a window image whose output from the AND circuit is “1” according to the priority order of the window images. When a read address corresponding to the window image determined as described above is selected from the read addresses corresponding to the window images generated by the read address generation circuit by the read address output, the image memory is used with the read address. The image is read out from.

  Thereby, an image is displayed using the highest priority window image in which the pixel which should be displayed exists in a rectangular area and a window image among several different window images. Thus, the image can be displayed in a desired shape by appropriately setting the priority order of the window images.

  The image display device of the present invention includes the display device and the image display control device, so that an image from the image memory can be displayed in an area specified by an arbitrary window image with a hardware configuration. Therefore, the burden on the CPU in the image display apparatus can be reduced.

  The image display control device according to the present invention, as described above, determines whether or not the display position of the pixel data constituting the image that is read from the image memory and displayed on the display device exists within a specific rectangular area. A display pixel position determination circuit for determining whether or not by binary, a window image memory for storing a window image represented by binary data having a preset shape, an output of the display pixel position determination circuit, and the window image memory A logical product circuit that outputs a logical product of the window image data read from the image memory, and a read address generation circuit that generates a read address that specifies a storage area of pixel data to be read for reading the image from the image memory; An address output control circuit that outputs the read address during a period when the output of the logical product circuit is “1”. Display processing of displaying the video image in the region specified by the window image having Jo is implemented in hardware. Therefore, the burden on the CPU can be greatly reduced, and a low-speed CPU can be used. Therefore, it is possible to reduce the cost of the image display control device and the image display device including the image display control device.

  An embodiment of the present invention will be described with reference to FIGS. 1 to 3 as follows.

  The image display apparatus according to the present embodiment is configured to display an input video image in a plurality of patterns of windows prepared in advance. As shown in FIG. 1, this image display device includes a display pixel position detection unit 1, a window pattern memory 2, a read control unit 3, an AND gate unit 4, a window priority register 5, a read window number determination unit 6, a read address generator. Unit 7, an address selector 8, a video memory 9, a memory controller 10, a display timing generator 11, and a display device 12. In the present image display device, the display pixel position detection unit 1, the window pattern memory 2, the read control unit 3, the AND gate unit 4, the window priority register 5, the read window number determination unit 6, the read address generation unit 7, the address selector 8. The memory controller 10 and the display timing generator 11 constitute an image display control device 101.

  The display pixel position detection unit 1 as a display pixel position determination circuit is a position (pixel) of pixel data of a video image when the video image read from the video memory 9 is displayed on the display device 12 in a specific rectangular area. Position) is detected in the display order of the pixel data.

  The display pixel position detection unit 1 has a pixel position counter SPC.

  The pixel position counter SPC includes a horizontal position counter HSPC and a vertical position counter VSPC.

  The horizontal position counter HSPC counts the pixel clock PCLK from the display timing generator 11 synchronized with the input timing of the pixel data of the video image displayed on the display device 12 in order to detect the horizontal position of the pixel. Thus, the current horizontal pixel position in the display video image is detected with the count value (the upper left corner of the screen is used as a reference (scanning start position)) and is output as horizontal pixel position data. Further, the horizontal position counter HSPC outputs a carry (carry) signal when the counting of the pixel clock PCLK is completed for all pixels in one line, and is reset by the horizontal synchronization signal HSYNC. The horizontal position counter HSPC starts counting by receiving the frame start signal FRS (“H” level) output from the display timing generator 11 at the enable terminal ENB as a count enable signal.

  The vertical position counter VSPC counts the carry signal from the horizontal position counter HSPC and outputs the count value as vertical pixel position data in order to detect the vertical position of the pixel. The vertical position counter VSPC is reset by the vertical synchronization signal VSYNC.

As the pixel position data increases, the pixel display position is positioned on the right side of the display screen for the horizontal position, and the pixel display position is positioned on the lower side of the display screen for the vertical position.
The display pixel position detection unit 1 detects a pixel position corresponding to n window patterns WP0 to WPn-1 (window images) of each window (window number) stored in the window pattern memory 2. Have. There are n window patterns WP0 to WPn-1 including a window pattern WP0 that is displayed as a base screen, such as wallpaper displayed on a full screen on a personal computer, that is, a base window (window number 0).

  For example, the display pixel position detection unit 1 corresponds to the window pattern WP1 of window number 1 and corresponds to the horizontal start point register HSPR1, the vertical start point register VSPR1, the horizontal end point register HEPR1, the vertical end point register VEPR1, the horizontal start point comparator HSCM1, and the vertical start point comparator. It has VSCMP1, horizontal end point comparator HECMP1, vertical end point comparator VECMP1, and AND gate G1. Further, the display pixel position detection unit 1 corresponds to the window pattern WPn-2 of the window number n-2, the horizontal start point register HSPRn-2, the vertical start point register VSPRn-2, the horizontal end point register HEPRn-2, and the vertical end point register. VEPRn-2, horizontal start point comparator HSCMPn-2, vertical start point comparator VSCMPn-2, horizontal end point comparator HECMn-2, vertical end point comparator VECMPn-2, and AND gate Gn-2. Further, the display pixel position detection unit 1 corresponds to the window pattern WPn-1 of the window number n-1, corresponding to the horizontal start point register HSPRn-1, the vertical start point register VSPRn-1, the horizontal end point register HEPRn-1, and the vertical end point register. It has a VEPRn-1, a horizontal start point comparator HSCMPn-1, a vertical start point comparator VSCMPn-1, a horizontal end point comparator HECMn-1, a vertical end point comparator VECMPn-1, and an AND gate Gn-1.

  Although not shown, the display pixel position detection unit 1 has a portion for detecting similar pixel positions for the window patterns WP2 to WPn-3 of the window numbers 2 to n-3.

  Here, since the pixel position detection portion corresponding to each of the window patterns WP1 to WPn-1 is configured in the same manner, a window number is not specified (a symbol of 1,... N-2, n-1 is not added). The pixel position detection portion corresponding to the pattern WP will be described.

  The horizontal start point register HSPR is image horizontal start position data located at the upper left end of a desired rectangular area R (R1 to Rn) on the display screen S (see FIGS. 2A to 2C) displayed on the display device 12. HSP (10 bits) is stored. The vertical start point register VSPR stores image vertical start position data VSP (10 bits) located at the upper left end of the rectangular area. The horizontal end point register HEPR stores image horizontal end position data HEP (10 bits) located at the lower right end of the rectangular area. The vertical end point register VEPR1 stores image vertical end position data VEP (10 bits) located at the upper left end of the rectangular area.

  For example, for window number 1, as shown in FIG. 2A, for rectangular area R1, horizontal start position data HSP1 and vertical start position data VSP1 are set at the upper left corner, and horizontal end position data at the lower right corner. HEP1 and vertical end position data VEP1 are set. For window number n-1, as shown in FIG. 2B, horizontal start position data HSPn-2 and vertical start position data VSPn-2 are set at the upper left corner of rectangular area Rn-2. In the lower right corner, horizontal end position data HEPn-2 and vertical end position data VEPn-2 are set. For window number n-1, as shown in FIG. 2C, horizontal start position data HSPn-1 and vertical start position data VSPn-1 are set at the upper left corner of rectangular area Rn-1. In the lower right corner, horizontal end position data HEPn-1 and vertical end position data VEPn-1 are set.

  The horizontal start point comparator HSCMP sequentially compares the image horizontal start position data HSP (A input) output from the horizontal start point register HSPR and the horizontal pixel position data (B input) output from the horizontal position counter HSPC. The horizontal start point comparator HSCMP sets the output to “1” when the B input becomes equal to or higher than the A input (B> = A).

  The vertical start point comparator VSCMP sequentially compares the image vertical start position data VSP (A input) output from the vertical start point register VSPR and the vertical pixel position data (B input) output from the vertical position counter VSPC. The vertical start point comparator VSCMP sets the output to “1” when the B input becomes equal to or higher than the A input (B> = A).

  The horizontal end point comparator HECMP sequentially compares the image horizontal end position data HEP (A input) output from the horizontal end point register HEPR and the horizontal pixel position data (B input) output from the horizontal position counter HSPC. The horizontal end point comparator HECMP sets the output to “1” when the B input becomes equal to or lower than the A input (B <= A).

  The vertical end point comparator VECMP sequentially compares the image vertical end position data VEP (A input) output from the vertical end point register VEPR and the vertical pixel position data (B input) output from the vertical position counter VSPC. The vertical end point comparator VECMP sets the output to “1” when the B input becomes equal to or lower than the A input (B <= A).

  The AND gate G outputs a logical product of the outputs of the horizontal start point comparator HSCMP, the vertical start point comparator VSCMP, the horizontal end point comparator HECMP, and the vertical end point comparator VECMP.

  The pixel position detection portion corresponding to each window pattern WP configured as described above is provided with each comparator when the current pixel position of the display video image displayed on the display screen S exists in the rectangular region R. Since “1” is output from the CMP, the AND gate G outputs “1”. In addition, the pixel position detection portion outputs “0” in any one of the comparators CMP when the current pixel position of the display video image displayed on the display screen S does not exist in the rectangular region R. Therefore, the AND gate G outputs “0”. As a result, while the positions of continuously displayed pixels continue to exist in the rectangular region R, the output of “1” is maintained from the pixel position detection portion.

  The window pattern memory 2 as the window image memory stores at least data of arbitrary-shaped window patterns WP1 to WPn-1 assigned with window numbers 1 to n-1. The data of each of the window patterns WP1 to WPn-1 is formed in a bitmap format (binary). Since the window pattern memory 2 needs to correspond to the display timing of the display device 12, the window pattern memory 2 is configured by an SRAM or the like that can read window pattern data at high speed.

  The read control unit 3 includes read start position registers RSPR1 to RSPRn-1 and read position counters RPC1 to RPCn-1 in order to control reading of each window pattern data from the window pattern memory 2. Hereinafter, when the reading start position registers RSPR1 to RSPRn-1 and the reading position counters RPC1 to RPCn-1 are described as representatives, they are referred to as a reading start position register RSPR and a reading position counter RPC.

  The read start position register RSPR includes a horizontal read start position register HRSPR (HRSPR1 to HRSPRn-1) and a vertical read start position register VRSPR (VRSPR1 to VRSPRn-1). The horizontal reading start position register HRSPR stores horizontal pixel position data (horizontal reading start position data HRS) at which reading of the window pattern data is started, and this data is received from the upper left end that is the starting point of the window pattern WP. It is expressed as the number of pixels in the horizontal direction. The vertical read start position register VRSPR stores vertical pixel position data (vertical read start position data VRS) at which reading of the window pattern data is started, and this data is the vertical pixel from the upper left end. Expressed as a number.

  The reading position counter RPC includes a horizontal reading position counter HRPC (HRPC1 to HRPCn-1) and a vertical reading position counter VRPC (VRPC1 to VRPCn-1).

  The horizontal readout position counter HRPC loads the horizontal readout start position data HRS from the horizontal readout start position register HRSPR by the frame start signal FRS output from the display timing generator 11, and determines the value from the value of the horizontal readout start position data HRS. The pixel clock PCLK is counted. Further, the horizontal readout position counter HRPC outputs a carry (carry) signal when the counting of the pixel clock PCLK for one line of pixels is completed, and is reset by the horizontal synchronization signal HSYNC.

  The vertical read position counter VRPC loads the vertical read start position data VRS from the vertical read start position register VRSPR by the frame start signal FRS, and the above carry from the horizontal read position counter HRPC from the value of the vertical read start position data VRS. Count the signal.

  The read address for reading the corresponding window pattern data from the window pattern memory 2 is composed of a combination of a count value output from the horizontal read position counter HRPC and a count value output from the vertical read position counter VRAC.

  The AND gate unit 4 outputs from the AND gates G1 to Gn-1 (logical product circuit) of the display pixel position detection unit 1 and the pixels of the window patterns WP1 to WPn-1 read from the window pattern memory 2. It consists of AND gates AG1 to AGn-1 that output logical products with data (window pattern data) in units of pixels. “1” output from the AND gates AG1 to AGn−1 indicates pixel data of a pattern portion (value of “1”) of the window pattern data existing in each of the rectangular regions R1 to Rn−1. It can also be said that the outputs (AND gate outputs) of the AND gates AG1 to AGn-1 indicate pixel data (binary) to be displayed on the display screen S. That is, when the AND gate output is “1”, there is pixel data to be displayed, and when the AND gate output is “0”, there is no pixel data to be displayed.

The window priority register 5 determines the priority order of the window pattern WP used as a window for displaying a video image on the display screen S of the display device 12, and the window patterns WP1 to WPn− except for the base window (window pattern WP0). There are as many storage areas as one. In each storage area, window numbers are stored according to priority. Specifically, the window number with the highest priority is stored in the leftmost storage area in the figure, and the window number with the lower priority is stored in the storage area closer to the right end. The window number data stored in each storage area is represented by k bits that can represent n ( ^k satisfies 2 ^k ≧ n> 2 ^k−1 ). For example, when n = 8, the window number data is represented by 3 bits. In the case of 3 bits, window numbers “1” to “7” are represented as “001” to “111”, respectively, and the window number “0” of the base window is represented as “000”.

  The read window number determination unit 6 as the window image determination unit includes outputs from the AND gates AG1 to AGn-1 of the AND gate unit 4 and window numbers stored in the respective storage areas of the window priority register 5 according to priority. The window number of the window pattern WP to be read out is output based on the data. Here, details of the readout window number determination unit 6 will be described with reference to FIG. FIG. 3 shows the configuration of the readout window number determination unit 6 when n = 8.

  As shown in FIG. 3, the read window number determination unit 6 includes selectors SEL1 to SEL7, AND gates RG1 to RG7, a plurality of inverters INV, and an OR gate OG.

  The selectors SEL1 to SEL7 have data input terminals D1 to D7 to which outputs from the AND gates AG1 to AG7 are input, respectively, and a data select terminal DS to which window number data from the window priority register 5 is individually input. is doing. Window number data with higher priority is input to each data select terminal DS in the order of selectors SEL1 to SEL7. In the selectors SEL1 to SEL7, the data input terminals D1 to D7 correspond to the window numbers 1 to 7, respectively, and one corresponding to the window number data input to the data select terminal DS from the outputs of the AND gates AG1 to AG7. Select to output.

  The AND gate RG1 outputs a logical product of the AND gate output selected and output from the output terminal OUT of the selector SEL1 and the window number data (3 bits) input to the selector SEL1. The AND gate RG2 performs a logical product of the inverted output of the AND gate output from the selector SEL1 by the inverter INV, the AND gate output selected and output from the output terminal OUT of the selector SEL2, and the window number data input to the selector SEL2. Output. Further, the AND gate RG7 outputs the inverted outputs (six) of the AND gate outputs from the selectors SEL1 to SEL6 by the individual inverter INV, the AND gate output selected from the output terminal OUT of the selector SEL7, and the selector SEL7. The logical product with the input window number data is output. As described above, the AND gates RG2 to RG7 have AND gate outputs from the corresponding selectors SEL2 to SEL7, window number data input to the selectors SEL2 to SEL7, and selectors SEL2 to SEL7 corresponding to the AND gates RG2 to RG7. A logical product of AND gate outputs from all selectors SEL (SEL1, SEL1,..., SEL1 to SEL6) in the preceding stage and an inverted output by the inverter INV is output.

  In the readout window determination unit 6 configured as described above, first, one corresponding to the window number with the highest priority is output from the outputs of the AND gates AG1 to AG7 by the selector SEL1. When the AND gate output from the selector SEL1 is “1”, the window number data is output from the AND gate RG1, and further output as the selected window number WN via the OR gate OG. When the AND gate output from the selector SEL1 is “0”, the window number data is not output from the AND gate RG1, and the inverted output “1” of the AND gate output from the selector SEL1 is input to the AND gate RG2. At this time, if the AND gate output from the selector SEL2 is “1”, the window number data input to the selector SEL2 is output from the AND gate RG2, and further output as the selected window number WN via the OR gate OG. .

  Similarly, when the AND gate outputs from the selectors SEL1 to SEL6 are all “0”, all the inverted outputs “1” of the AND gate outputs from the selectors SEL1 to SEL6 are input to the AND gate RG7. At this time, if the AND gate output from the selector SEL7 is “1”, the window number data input to the selector SEL7 is output from the AND gate RG7 during the period in which the AND gate output is “1”, and further the OR gate. The selected window number WN is output via OG. Conversely, when the AND gate output from the selector SEL7 is “0”, the window number data input to the selector SEL7 is not output from the AND gate RG7, so that the OR gate OG indicates “0” indicating the base window. (“000” in 3 bits) is output as the selected window number WN.

  As described above, the readout window determination unit 6 sequentially selects and outputs the outputs from the AND gates AG1 to AG7 in descending order of selection by the selectors SEL1 to SEL7, and outputs an AND gate output that is “1”. Only the window number data input to the selector SEL to be output is output. As a result, the window number data of the highest priority window pattern WP in which pixel data to be displayed exists is output.

  Read address generator 7 serving as a read address generating circuit generates read addresses corresponding to the respective window pattern data, corresponding to window numbers 0 to n-1, and read start address registers RSAR0 to RSARn-1. Read address counters RAC0 to RACn-1.

  The read start address registers RSAR0 to RSARn-1 are read start addresses (first to start reading video images from the video memory 9 when displaying video images on the display device 12 with the corresponding window patterns WP0 to WPn-1, respectively. The address for designating the area storing the pixel data of the video image to be read is stored. The read address counters RAC0 to RACn-1 read pixel data of a video image one by one from the video memory 9 by counting the pixel clock PCLK from the read start addresses from the corresponding read start address registers RSAR0 to RSARn-1. The read address for output is output.

  The address selector 8 serving as an address output control circuit receives data input terminals D0 to Dn-1 to which read addresses from the read address counters RAC0 to RACn-1 are respectively input, and window number data from the read window determination unit 6. It has a data select terminal DS to be input. The address selector 8 is a period in which the window number data is input as one read address corresponding to the window number data input to the data select terminal DS among the read addresses from the read address counters RAC0 to RACn−1 ( The AND gate output for which the selection window number WN has been determined remains “1”) and is output from the output terminal OUT.

  The video memory 9 as an image memory has video image data (pixel data) displayed on the display screen S of the display device 12, and is constituted by a DRAM, for example. In the video memory 9, a video image (moving image) is written by software under the control of a CPU (not shown).

  The memory controller 10 controls the writing of the video image as described above, and controls the pixel data of the video image stored in the video memory 9 one by one with the read address output from the address selector 8. In addition, the memory controller 10 writes the input video image between reading of the video image.

  The display timing generator 11 generates timing signals necessary for display such as a horizontal synchronization signal HSYNC and a vertical synchronization signal VSYNC necessary for display. The display timing signal 11 also generates the pixel clock PCLK and the frame start signal FRS described above.

  Next, a video image display operation by the display device configured as described above will be described.

  First, the display pixel position detection unit 1 determines whether or not a pixel of a video image to be displayed on the display device 12 exists in each rectangular area (R1 to Rn-1) set according to each window. To detect. When the pixel exists in each rectangular area, “1” is output from each AND gate G1 to Gn−1. When the pixel does not exist in each rectangular area, “0” is output from each AND gate G1 to Gn−1. Is output. On the other hand, each window pattern data (binary data) is read from the window pattern memory 2 based on the read address from the read control unit 3. In the window pattern data, the pattern internal area of the window pattern WP is represented by “1”, and the external area of the window pattern WP is represented by “0”.

  In the AND gate unit 4, each AND gate AG <b> 1 to AGn−1 outputs a logical product of each output (detection result) of the display pixel position detection unit 1 and each window pattern data read from the window pattern memory 2. Is done. This logical product output is “1” only when the displayed pixel exists in each rectangular area and the pattern internal area of each window pattern WP.

  Subsequently, the readout window number determination unit 6 determines the window number of the window pattern WP whose logical product output is “1” in order from the highest priority of the window number data stored in the window priority register 5. The window number data selected as a result is output as the selected window number WN.

  In the address selector 8, an AND gate output in which one read address determines the selected window number WN from the read address corresponding to each window pattern WP generated by the read address generating unit 7 based on the selected window number WN is “ It is selected and output during the period in which 1 ″ is maintained. The video image data written in the video memory 9 is read by the memory controller 10 at the pixel designated by the read address. Then, the read pixel data is displayed on the display device 12. Here, the above read address is output from the address selector 8 during the above period, so that a pixel corresponding to the internal area of the window pattern WP of the selected window number WN is read out from the video memory 9. ing. Thereby, the video image is displayed on the display device 12 only in the internal area of the selected window pattern WP. Thus, by appropriately setting the priority order of the window numbers in the window priority register 5, a video image can be displayed using a desired window pattern WP.

  For example, when the window number n-1 is selected, a video image existing in the rectangular area Rn-1 shown in FIG. 2B is displayed. At this time, if the window pattern WPn-1 of the window number n-1 is heart-shaped, the video is displayed in the heart-shaped area on the display screen S displayed on the display device 12, as shown in FIG. An image will be displayed.

  As described above, the image display apparatus according to the present embodiment detects the display pixel position that detects whether the pixel of the video image displayed on the display device 12 exists in each rectangular area set in accordance with a plurality of windows. Part 1, a window pattern memory 2 for storing a plurality of window pattern data (binary data), each output of the display pixel position detection unit 1, and a plurality of window pattern data read from the window pattern memory 2 An AND gate unit 4 that individually outputs products, a read window number determination unit 6 that determines a window number of a window pattern WP whose logical product output is “1” according to the priority order of the window pattern WP, and the window number Read address corresponding to each window pattern WP generated by the read address generator 7 An address selector 8 to select a, and a memory controller 10 to read out the video image from the video memory 9 by the read address. Thereby, a video image can be displayed on a window having an arbitrary pattern (shape). In addition, since the above display process is realized by hardware, the burden on the CPU can be greatly reduced as compared with the case where the same process is realized by software. Therefore, the circuit for performing the processing can be made into a chip and can be handled by a low-speed CPU, so that the cost of the image display apparatus can be reduced.

  The rectangular area set in advance by the display pixel position detection unit 1 is displayed by appropriately setting data stored in the horizontal start point register HSPR, vertical start point register VSPR, horizontal end point register HEPR, and vertical end point register VEPR. The area can be set as desired. In addition, by appropriately changing the data stored in the read start position register RSPR in the read control unit 3, only a part of the window pattern for displaying the video image can be displayed. For example, if the data stored in the read start position register RSPR is set so that the window pattern WP is read from the pixels in the latter half, it is possible to display only the lower half of the heart shape shown in FIG. is there.

  In the present embodiment, a configuration for displaying a video image on the display device 12 has been described. However, a configuration for displaying a still image on the display device 12 is also included in the present invention.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope shown in the claims. That is, embodiments obtained by combining technical means appropriately modified within the scope of the claims are also included in the technical scope of the present invention.

  The image display control apparatus according to the present invention reduces the burden on the CPU by performing a process of reading and displaying a video image stored in a memory in a window having a predetermined pattern, so that the window of various patterns can be reduced. Therefore, the present invention can be suitably used for displaying video images in various forms.

It is a block diagram which shows the structure of the image display apparatus which shows one Embodiment of this invention. (A) thru | or (c) is a figure which shows the rectangular area designated on the display screen by the display pixel position detection part in the said image display apparatus, (d) shows the state which displayed the video image on the selected window. FIG. It is a logic circuit diagram showing a configuration of a readout window number determination unit in the image display device.

Explanation of symbols

1 Display pixel position detector (display pixel position determination circuit)
2 Window pattern memory (window image memory)
3 Reading control section 4 AND gate section 5 Window priority register 6 Reading window number determination section (window image determination circuit)
7 Read address generator (read address generator)
8 Address selector (address output control circuit)
9 Video memory (image memory)
10 Memory Controller 11 Display Timing Generator 12 Display Device (Display Device)
101 Image display control devices AG1 to AGn-1 AND gate (logical product circuit)
WP0 to WPn-1 Window pattern (window image)

Claims (3)

In an image display control device that reads an image stored in an image memory for display on a display device,
A display pixel position determination circuit that binaryly determines whether or not a display position of pixel data constituting an image to be read from the image memory and displayed on a display device exists in a specific rectangular area;
A window image memory for storing a window image represented by binary data having a preset shape;
A logical product circuit that outputs a logical product of the output of the display pixel position determination circuit and the data of the window image read from the window image memory;
A read address generating circuit for generating a read address for designating a storage area of pixel data to be read for reading the image from the image memory;
An image display control apparatus comprising: an address output control circuit that outputs the read address during a period in which the output of the logical product circuit is “1”. The window image memory stores a plurality of window images,
The display pixel position detecting means determines whether or not the display position of the pixel data exists in a specific rectangular area for a plurality of rectangular areas set corresponding to each of the window images,
The logical product circuit outputs, for each window image, a logical product of the output of the display pixel position determination circuit and the window image data read from the window image memory,
The read address generation circuit generates a read address for each window image,
The image display control device includes a window image determination circuit that determines a window image in which each output from the AND circuit for each window image is “1” in accordance with the priority order given to each window image,
2. The image display control apparatus according to claim 1, wherein the address output control circuit outputs the read address corresponding to a window image determined to have an output from the AND circuit of “1”. The display device;
An image display device comprising the image display control device according to claim 1.

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