JP2006324882A - Phase synchronization loop circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a phase synchronization loop circuit with high frequency resolution, superior phase noise property, and restricted output spurious with respect to the phase synchronization loop circuit used as a wave source of microwave in a microwave transceiver device, such as a radio communication system, and radar. <P>SOLUTION: A reference signal is formed by M multiplication (M is integer) of a source signal from an oscillator 1 in a multiplicator 2, and is fed to a phase comparator 6. Part of the output of a voltage control oscillator 3 is taken from a coupler 4, and entered to a frequency divider 5 and subjected to N discrimination (N is fraction). The output signal divided by the frequency divider 5 is entered in the phase comparator 6. In the phase comparator 6, the signal from the frequency divider 5 and a reference signal from a multiplicator 2 are compared and a phase error or a frequency error is detected to generate an error voltage. The error voltage generated from the phase comparator 6 is filtered through a loop filter 7 and entered in a voltage control oscillator 3. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a phase-locked loop circuit used for a microwave wave source in a microwave transmission / reception apparatus such as a radio communication apparatus and a radar.

  For example, Japanese Patent Laid-Open No. 2001-24547 discloses a conventional phase locked loop circuit. This conventional phase-locked loop circuit divides the output signal of the voltage controlled oscillator by the variable divider, divides the signal from the reference oscillator by the variable divider, and phase-divides each of these divided signals. The comparison is made by a comparator. These variable frequency dividers are initially set to a small frequency division number and phase synchronization is confirmed, and then a large frequency division number is set to perform phase synchronization. Thus, by changing the frequency division number, the time to reach phase synchronization is shortened.

JP2001-24547

  In the conventional phase-locked loop circuit, in order to increase the frequency resolution of the signal to be generated, in principle, it is necessary to increase the frequency dividing number to divide the feedback signal from the voltage controlled oscillator. There was a problem that the phase noise due to the noise floor deteriorated. In particular, when a ΔΣ type fractional N type frequency divider is used, there is a problem that spurious components are generated. Further, the conventional phase-locked loop circuit has a problem that the circuit scale increases because it has a variable frequency divider that can set a plurality of frequency division numbers.

  The present invention has been made to solve the above-described problems, and provides a phase-locked loop circuit that has high frequency resolution, good phase noise characteristics, and can suppress output spurious. With the goal.

  A phase-locked loop circuit according to a first aspect of the present invention includes a voltage controlled oscillator, a frequency dividing circuit that divides an output signal of the voltage controlled oscillator, and a phase error between a signal divided by the frequency dividing circuit and a reference signal Alternatively, a phase comparator that detects an error error and outputs an error voltage, a loop filter that filters an error voltage output from the phase comparator and outputs the error voltage, and a reference signal that is multiplied by a source signal And a multiplier for generating.

  A phase-locked loop circuit according to a second aspect of the present invention includes a voltage-controlled oscillator, a first power distributor that distributes an output signal of the voltage-controlled oscillator, and one distribution signal that is distributed by the first power distributor. A first frequency dividing circuit for frequency dividing, a second frequency dividing circuit for frequency dividing the other one distributed signal distributed by the first power distributor, and a reference signal by multiplying the source signal A frequency divider, a second power distributor that distributes a reference signal generated by the multiplier, a third frequency divider that divides one reference signal distributed by the second power distributor, The fourth frequency dividing circuit that divides the other one reference signal distributed by the second power divider, the signal divided by the first frequency dividing circuit, and the third frequency dividing circuit A first error signal is output by detecting a phase error or a frequency error with respect to the reference signal that has been rotated. A phase comparator, a second error signal is output by detecting a phase error or a frequency error between the signal frequency-divided by the second frequency divider circuit and the reference signal frequency-divided by the fourth frequency divider circuit. A phase comparator; and a mixer that mixes error signals of the first phase comparator and the second phase comparator through a loop filter and outputs the mixed signal to the voltage controlled oscillator.

  According to the first aspect of the present invention, the output of the frequency dividing circuit that divides the output signal of the voltage controlled oscillator and the reference signal generated by multiplying the source signal by the multiplier are compared by the phase comparator. Thus, a phase-locked loop with high frequency resolution and good phase noise characteristics can be obtained.

  According to the second aspect of the present invention, the first output signal distributed by the first power divider and the other one output signal are divided by the first frequency dividing circuit and the second frequency dividing circuit. The reference signal generated by multiplying the source signal by the multiplier is distributed by the second power distributor, and one reference signal and the other reference signal distributed by the second power distributor are distributed to the third distribution. Frequency division is performed by the frequency divider circuit and the fourth frequency divider circuit, the phase of the output of the first frequency divider circuit and the output of the third frequency divider circuit is compared, and the second frequency divider circuit and the fourth frequency divider circuit The output voltage of the phase-locked loop circuit is reduced and the error voltage obtained by these phase comparisons is mixed by the mixer through the loop filter and input to the voltage controlled oscillator. it can.

Embodiment 1

  A phase-locked loop circuit according to Embodiment 1 of the present invention will be described with reference to FIG. 1 is a block diagram showing a configuration of a phase-locked loop circuit according to Embodiment 1 of the present invention. In FIG. 1, 1 is a highly stable oscillator such as a crystal oscillator that generates a source signal of a phase locked loop circuit, and 2 is a multiplier that multiplies the source signal from the oscillator 1 to generate a reference signal. Reference numeral 3 is a voltage controlled oscillator, and 4 is a coupler that combines and outputs the output signals of the voltage controlled oscillator 3. 5 is a ΔΣ type fractional-N frequency divider, and 6 is a phase comparator that detects a phase error or a frequency error between the signal from the frequency divider 5 and the reference signal from the multiplier 2 and outputs an error voltage. A loop filter 7 filters the error voltage signal output from the phase detector 6. The output of the loop filter 7 is input to the voltage controlled oscillator 3 to form a phase locked loop circuit. The response characteristic of the phase locked loop is determined by the filter characteristic of the loop filter 7.

  Next, the operation of the phase locked loop circuit will be described. In the phase-locked loop circuit shown in FIG. 1, the source signal from the oscillator 1 is multiplied by M (M is an integer) by a multiplier 2 to generate a reference signal, and this reference signal is input to the phase comparator 6. A part of the output signal of the voltage controlled oscillator 3 is taken out by the coupler 4 and is input to the frequency divider 5 to divide by N (N is a fraction). The output signal divided by the frequency divider 5 is input to the phase comparator 6. The phase comparator 6 compares the signal from the frequency divider 5 with the reference signal from the multiplier 2, detects a phase error or a frequency error, and outputs an error voltage. The error voltage output from the phase comparator 6 is filtered by the loop filter 7 and input to the voltage controlled oscillator 3.

  Here, when the frequency of the source signal output from the oscillator 1 is f1, the output frequency of the voltage controlled oscillator 3 is f2, and the ratio thereof is k, the relationship is f2 = k × f1, k = N × M. . In this phase locked loop circuit, the noise floor of the output of the phase locked loop circuit (voltage controlled oscillator 3 output) is Lp, and the component Lp1 due to noise from the oscillator 1 side in the noise floor Lp is the noise of the oscillator 1 If Lr is Lr, then Lp1 = Lr + 20 Log (k). When the value of the ratio k between f2 and f1 is set, this Lp1 does not depend on the value of M, but the noise level is determined.

  On the other hand, the component Lp2 due to noise from the phase detector 6 in the noise floor Lp is Lp2 = Lpd + 20 Log (N), where Lpd is the noise floor of the phase comparator 6. This Lp2 changes depending on the value of M when the value of the ratio k between f2 and f1 is set. That is, since N = k / M, when the value of M is increased, the value of N is decreased correspondingly and the noise floor Lp2 is decreased.

  Therefore, in the phase-locked loop circuit shown in FIG. 1, by setting the value of k in advance and setting the value of M to an integer larger than 1, Lp2 decreases (Lp1 is constant), and the output noise floor Lp (= Lp1 + Lp2) can be reduced.

  The frequency divider 5 is a ΔΣ type frequency divider, and a fraction is set as the frequency division number N. The frequency resolution of the phase locked loop circuit is determined by the number of digits that can be set. For example, when the frequency f1 of the source signal generated by the oscillator 1 is 10 MHz, the multiplier M of the multiplier 2 is 10, and the output frequency of the phase-locked loop circuit is 2300 MHz (2295 MHz to 2305 MHz, 200 kHz step), the frequency divider 5 The frequency division number N to be set to N = 22.950 to 23.050 is set in 0.002 steps. FIG. 1 shows an example of this numerical value. Thus, the frequency resolution of the phase-locked loop circuit can be increased by setting the frequency division number N as a fraction and changing it in a predetermined step.

Embodiment 2

  A phase locked loop circuit according to a second embodiment of the present invention will be described with reference to FIG. FIG. 2 is a block diagram showing a configuration of a phase-locked loop circuit according to Embodiment 2 of the present invention. In FIG. 2, reference numeral 8 denotes a first power distributor that distributes the output signal of the voltage controlled oscillator 3, and the output signal of the voltage controlled oscillator 3 is coupled by a coupler 4 and input to the power distributor 8. Reference numeral 9 denotes a first frequency dividing circuit that divides one distribution signal output from the power distributor 8, and reference numeral 10 denotes a second frequency division that divides another one distribution signal output from the power distributor 8. The frequency dividing circuit 9 and the frequency dividing circuit 10 are constituted by a frequency dividing circuit that performs fractional frequency division by a ΔΣ type fractional N type so that the frequency resolution of the phase locked loop circuit is high. Reference numeral 11 denotes a direct digital synthesizer (hereinafter referred to as “DDS”) that converts the frequency of the reference signal. The source signal output from the oscillator 1 is multiplied by the multiplier 2 and input to the DDS 11. The DDS 11 is used for step-changing the frequency of the reference signal with high accuracy, but it may not be used. Reference numeral 12 denotes a second power distributor that distributes the reference signal from the DDS 11 or from the multiplier 2 when the DDS 11 is not used. Reference numeral 13 denotes a third frequency dividing circuit that divides one reference signal distributed by the power distributor 12. Reference numeral 14 denotes a fourth frequency dividing circuit that divides the other one reference signal distributed by the power distributor 12. This is a frequency divider circuit. The frequency dividing circuit 13 and the frequency dividing circuit 14 may be a frequency dividing circuit that divides an integer, or may be a ΔΣ type fractional N type frequency dividing circuit that performs frequency division. Reference numeral 15 denotes a first phase comparator that detects a phase error or a frequency error between the signal divided by the frequency dividing circuit 9 and the reference signal divided by the frequency dividing circuit 13, and outputs an error signal. This is a phase comparator that detects a phase error or a frequency error between the signal divided by the frequency dividing circuit 10 and the reference signal frequency divided by the frequency dividing circuit 14 and outputs an error signal. Reference numeral 17 denotes a loop filter for filtering the error voltage signal output from the phase comparator 15, and reference numeral 18 denotes a loop filter for filtering the error voltage signal output from the phase comparator 16, and the phase synchronization is performed according to the filter characteristics of these loop filters. The response characteristics of the loop are determined. Reference numeral 19 denotes a mixer for mixing the output of the loop filter 17 and the output of the loop filter 18. The output of the mixer 19 is input to the voltage controlled oscillator 3 to form a phase locked loop.

Next, the operation of the phase locked loop circuit according to the second embodiment will be described. In the phase-locked loop circuit shown in FIG. 2, a source signal from the oscillator 1 is multiplied by M (M is an integer) by a multiplier 2 to generate a reference signal, and this reference signal is input to the DDS 11. The DDS 11 is used for step-changing the frequency of the reference signal after M multiplication with high accuracy, but it can be omitted. The reference signal output from the DDS 11 is distributed by the power distributor 12 and input to the frequency dividing circuit 13 and the frequency dividing circuit 14. Here, the power distributor 12 distributes to a plurality of reference signals, and the plurality of distributed reference signals are respectively input to the frequency dividing circuit. Here, the power divider 12 X-divides the reference signal, inputs the distributed reference signals to X frequency dividers, and sets the frequency division number of each frequency divider R _i (i = 1, 2, ... X). Dividing number of the frequency divider circuit 13 is R _1, the frequency division number of the frequency dividing circuit 14 is R _X.

On the other hand, a part of the output signal of the voltage controlled oscillator 3 is extracted by the coupler 4 and input to the power distributor 8. Here, the power distributor 8 distributes the output signal of the voltage controlled oscillator 3 into X signals, inputs these signals to X frequency dividing circuits, and sets the frequency division number of each frequency dividing circuit to N _i. (I = 1, 2,... X). Dividing number of the frequency dividing circuit 9 is N _1, the frequency division number of the frequency dividing circuit 10 is N _X. The phase comparator 15 compares the phase of the signal divided by N ₁ by the frequency divider 9 and the reference signal divided by R ₁ by the frequency divider 13 and outputs an error voltage. Further, the signal dividing circuit 14 which is N _X division by the divider circuit 10 and a reference signal R _X division by phase comparison by the phase comparator 16 outputs an error voltage. The error voltage outputs of the phase comparator 15 and the phase comparator 16 are mixed by the mixer 19 via the loop filter 17 and the loop filter 18, respectively, and the output of the mixer 19 is input to the voltage controlled oscillator 3.

Here, the frequency of the source signal oscillator 1 outputs f1, the output frequency of the voltage controlled oscillator 3 f2, and these ratios and k, regardless of the ratio between N _i and R _i to the value of the constant (i Assuming that it is constant, the relationship of f2 = k × f1, k = (N _i / R _i ) × M is obtained. That is, by setting the values of N _i and R _i so that the ratio of N _i and R _i is constant, the voltage having a frequency multiplied by k with respect to the frequency of the source signal output from the oscillator 1. A controlled oscillator output can be obtained.

Now, the configuration composed of the frequency dividing circuit 9, the frequency dividing circuit 13, the phase comparator 15 and the loop filter 17 is made into one loop system, and consists of the frequency dividing circuit 10, the frequency dividing circuit 14, the phase comparator 16 and the loop filter 18. Looking at the configuration as another loop system, if the ratio of N _i and R _i is constant and the value of N _i is set to be different (that is, the values of N ₁ and N _X are different). If set, the spurious frequency generated in each loop system can be set to a different value. Because the frequency of spurious generated in each loop system is different, spurious generated in the error voltage mixed by the mixer 19 is mixed at a low level at a plurality of frequencies without being accumulated at a specific frequency. By inputting the mixed error voltage signal to the voltage controlled oscillator 3, spurious generated at the output of the voltage controlled oscillator 3 can be suppressed to a low level without being accumulated at a specific frequency.

Noise floor of the phase locked loop circuit according to the second embodiment, and M multiplied source signal by the multiplier 2, the N _i division in divider circuit 9 and frequency dividing circuit 10, as in the first embodiment, As a whole phase-locked loop circuit, the output noise floor Lp (= Lp1 + Lp2) can be reduced.

The frequency resolution of the phase-locked loop circuit according to the second embodiment is determined by the frequency step by the DDS 11 when the frequency dividing numbers N _i and R _i of the frequency dividing circuit are fixed values. The DDS 11 is provided with a frequency setting function so that a necessary frequency step can be taken. Alternatively, the output of the multiplier 2 may be input to the power distributor 12 without using the DDS 11. In this case, the set value of the ratio of N _i and R _i is set to k for all i values, and the frequency f2 (k) of the output of the phase locked loop circuit (that is, the output of the voltage controlled oscillator 4) is obtained. When the output frequency is changed, the output of the phase-locked loop circuit (ie, the output of the voltage controlled oscillator 4) is obtained by changing the set value of the ratio of N _i and R _i to k + Δk for all i values. Frequency f2 (k + Δk) is obtained.

1 is a block diagram showing a configuration of a phase locked loop circuit according to a first embodiment of the present invention. It is a block diagram which shows the structure of the phase locked loop circuit based on Embodiment 2 of this invention.

Explanation of symbols

2 Multiplier 3 Voltage controlled oscillator 5 Frequency divider 6 Phase comparator 7 Loop filter 8 First power divider 9 First frequency divider 10 Second frequency divider 11 Direct digital synthesizer 12 Second power divider 13 Third frequency divider 14 Fourth frequency divider 15 First phase comparator 16 Second phase comparator 17, 18 Loop filter 19 Mixer

Claims (2)

A voltage controlled oscillator, a frequency dividing circuit that divides the output signal of the voltage controlled oscillator, and a phase that outputs an error voltage by detecting a phase error or a frequency error between the signal divided by the frequency dividing circuit and a reference signal A comparator, a loop filter that filters an error voltage output from the phase comparator and outputs the error voltage to the voltage controlled oscillator, and a multiplier that multiplies a source signal to generate the reference signal. A phase-locked loop circuit. A voltage controlled oscillator; a first power distributor that distributes an output signal of the voltage controlled oscillator; a first frequency divider that divides one distributed signal distributed by the first power distributor; A second frequency dividing circuit for frequency-dividing the other one distributed signal distributed by the first power divider; a multiplier for multiplying the source signal to generate a reference signal; and a reference signal generated by the multiplier , A third frequency dividing circuit that divides one reference signal distributed by the second power divider, and another one distributed by the second power distributor. Detects a phase error or a frequency error between a fourth frequency dividing circuit that divides the reference signal, a signal divided by the first frequency dividing circuit, and a reference signal divided by the third frequency dividing circuit Frequency division by the first phase comparator that outputs an error signal and the second frequency divider circuit. A second phase comparator for detecting a phase error or a frequency error between the received signal and the reference signal divided by the fourth frequency dividing circuit and outputting an error signal; the first phase comparator; A phase-locked loop circuit comprising: a mixer for mixing error signals of the two phase comparators through a loop filter and outputting the mixed signal to the voltage controlled oscillator.

Images