JP2006324526A - Wiring board and its manufacturing method - Google Patents

Wiring board and its manufacturing method Download PDF

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JP2006324526A
JP2006324526A JP2005147257A JP2005147257A JP2006324526A JP 2006324526 A JP2006324526 A JP 2006324526A JP 2005147257 A JP2005147257 A JP 2005147257A JP 2005147257 A JP2005147257 A JP 2005147257A JP 2006324526 A JP2006324526 A JP 2006324526A
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substrate
hole
conductive member
recess
wiring board
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JP4622672B2 (en
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Narimasa Iwamoto
成正 岩本
Hirofumi Motokawa
裕文 元川
Yoshiharu Nakamura
芳春 中村
Ryoji Imai
良治 今井
Tomohiro Nakatani
友洋 中谷
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Panasonic Electric Works Co Ltd
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Matsushita Electric Works Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board having via holes without occurrences of an exfoliation at an interface between the board and a conductive member, and also without a trouble caused by a thermal stress of the board crack or the like, and also to provide its manufacturing method. <P>SOLUTION: The wiring board has a via hole 4 formed through between one surface 1a and the other surface 1b of the board 1 comprising a hourglass-shaped through hole 2 with its inside diameter at the central part in a thickness direction of the board 1 smaller than the diameter of the openings at the surfaces 1a, 1b; and a layer of a conductive member 3 covering whole inside face of the through hole 2 with its ends of the both end openings of the through hole 2 exposed and with the central part of the through hole 2 blocked up. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、シリコンウェハーやガラスウェハーからなる基板の両表面間で電気導通を取り且つ密閉されたビアホールを有する配線基板及びその製造方法に関するものである。   The present invention relates to a wiring board having a via hole which is electrically conductive between both surfaces of a substrate made of a silicon wafer or a glass wafer and has a sealed via hole, and a method for manufacturing the wiring board.

近年、シリコンウェハーやガラスウェハー内部の貫通孔に、密閉性確保と電気通電用の導通配線を形成するための研究が盛んに為されている。例えば、図5に示すように基板1の両側表面に貫通させた貫通孔2内に銅等の導電性部材3をメッキにより充填して形成したビアホール4を有する配線基板が提供されている(例えば特許文献1)。
特開2002−185140公報(図1、段落番号0014)
2. Description of the Related Art In recent years, research has been actively conducted to ensure sealing performance and form conductive wiring for electrical conduction in a through-hole inside a silicon wafer or glass wafer. For example, as shown in FIG. 5, there is provided a wiring board having via holes 4 formed by filling a through-hole 2 penetrating both side surfaces of the board 1 with a conductive member 3 such as copper by plating (for example, Patent Document 1).
JP 2002-185140 A (FIG. 1, paragraph number 0014)

ところで特許文献1に示されるようなビアホール構造では、基板1となるシリコンウェハやガラスウェハと、銅などの導電性部材3の間の熱膨張率が大幅に異なるため、熱ストレスにより基板1と導電性部材3との面での剥離や、基板クラックなどのトラブルが発生するという問題があった。   By the way, in the via hole structure as shown in Patent Document 1, the coefficient of thermal expansion between the silicon wafer or glass wafer to be the substrate 1 and the conductive member 3 such as copper is significantly different. There is a problem that troubles such as peeling on the surface of the conductive member 3 and substrate cracks occur.

一方このような熱ストレストラブルを解決するため、孔径を小さくすることが検討されているが、孔形成が困難であり且つ、孔の導電部材の充填もまた困難であるなど、十分な効果をあげることができていないのが現状である。   On the other hand, in order to solve such heat stress troubles, it has been studied to reduce the hole diameter, but it has sufficient effects such as difficulty in forming the hole and filling the conductive member in the hole. The current situation is that it is not possible.

本発明は、上述の点に感が見えて為されたもので、その目的とするところは基板と導電性部材との界面での剥離や、基板クラックなどの熱ストレスによるトラブルの発生をなくしたビアホールを有する配線基板及びその製造方法を提供することにある。   The present invention has been made in view of the above-mentioned points, and its purpose is to eliminate the occurrence of troubles due to thermal stress such as peeling at the interface between the substrate and the conductive member and substrate cracks. An object of the present invention is to provide a wiring board having a via hole and a manufacturing method thereof.

上述の目的を達成するために、請求項1の配線基板の発明では、基板の一の表面と他の表面の間に、前記基板の厚さ方向の中央部が一の表面側及び他の表面側より狭くなる貫通孔と、前記貫通孔の内面に沿うように形成されて、前記貫通孔の両端開口に両端部を露出させ、且つ前記貫通孔の中央部のみを閉塞した導電性部材層とからなるビアホールを有することを特徴とする。   In order to achieve the above-mentioned object, in the invention of the wiring board according to claim 1, the central portion in the thickness direction of the substrate is located on the one surface side and the other surface between one surface and the other surface of the substrate. A through-hole that is narrower than the side, and a conductive member layer that is formed along the inner surface of the through-hole, exposes both end portions at both end openings of the through-hole, and closes only the central portion of the through-hole. It has the via hole which consists of.

請求項1の配線基板の発明によれば、熱ストレスのもっとも大きな貫通孔の両端部の内面に形成された導電性部材層が薄くなり、そのため熱膨張差により発生する熱ストレスが小さく、そのため貫通孔との界面剥離や、基板クラックなどを防ぐことができ、また貫通孔の中央部が狭くなっているために、熱膨張差により発生する熱ストレスを小さくできる上に、仮にこの中央部での界面の剥離や、基板クラックが発生したとしても、貫通孔の内部であるため、導通や気密性などのトラブル発生を緩和することができる。   According to the invention of the wiring board of claim 1, the conductive member layers formed on the inner surfaces of both end portions of the through-hole having the greatest thermal stress are thinned, so that the thermal stress generated due to the difference in thermal expansion is small, and therefore the through-hole It is possible to prevent interfacial delamination from the hole, substrate cracking, and the like, and since the central part of the through hole is narrow, the thermal stress generated by the difference in thermal expansion can be reduced. Even if interface peeling or substrate cracking occurs, troubles such as conduction and airtightness can be mitigated because it is inside the through hole.

請求項2の配線基板の製造方法の発明では、請求項1の配線基板の製造方法であって、基板の一の表面から基板の厚さ方向の中央部に向けて狭くなるテーパー状の第1の凹部を形成する工程と、前記第1の凹部の内面に導電性部材層をメッキ形成する工程と、前記基板の他の表面から前記第1の凹部の底部に達し且つ該底部方向に狭くなるテーパー状の第2の凹部を形成する工程と、前記第1の凹部の内面に導電性部材層をメッキする工程とからなることを特徴とする。   The wiring board manufacturing method according to claim 2 is the wiring board manufacturing method according to claim 1, wherein the taper-shaped first narrows from one surface of the substrate toward a central portion in the thickness direction of the substrate. Forming a concave portion of the first concave portion, plating a conductive member layer on the inner surface of the first concave portion, reaching the bottom of the first concave portion from the other surface of the substrate, and narrowing toward the bottom. The method includes a step of forming a tapered second recess, and a step of plating a conductive member layer on the inner surface of the first recess.

請求項2の配線基板の製造方法の発明によれば、簡便に、請求項1の発明での配線基板を製造することができる。   According to the invention of the method for manufacturing a wiring board of claim 2, the wiring board of the invention of claim 1 can be easily manufactured.

請求項3の配線基板の製造方法の発明では、請求項1の配線基板の製造方法であって、基板の一の表面から該基板の厚さ方向の中央部に向けて狭くなるテーパー状の第1の凹部を形成する工程と、前記基板の他の表面から前記第1の凹部の底部に連通し且つ該底部方向に狭くなるテーパー状の第2の凹部を形成する工程と、前記基板の一の表面側、他の表面側の各々から、前記第1の凹部の内面、第2の凹部の内面に導電性部材層をメッキ形成するとともに両凹部の連通部を前記導電性部材層で閉塞する工程とからなることを特徴とする。   According to a third aspect of the present invention, there is provided a method of manufacturing a wiring board according to the first aspect, in which the taper-shaped first narrows from one surface of the board toward the center in the thickness direction of the board. Forming a first recess, forming a tapered second recess that communicates from the other surface of the substrate to the bottom of the first recess and narrows toward the bottom, and A conductive member layer is formed by plating on the inner surface of the first recess and the inner surface of the second recess from each of the front surface side and the other surface side, and the communicating portion of both recesses is closed with the conductive member layer. It consists of a process.

請求項3の配線基板の製造方法の発明によれば、メッキ加工のプロセスを一回に簡略化し且つ、凹部形成時の導電部材の破損を軽減して、簡便に請求項1の発明での配線基板を製造することができる。   According to the invention of the method for manufacturing a wiring board of claim 3, the wiring process according to the invention of claim 1 can be simplified by simplifying the plating process once and reducing the breakage of the conductive member when forming the recess. A substrate can be manufactured.

請求項4の配線基板の製造方法の発明では、請求項3又は4の発明において、前記第1の凹部の内面若しくは第2の凹部の内面への導電性部材層のメッキ形成を、前記基板の一の表面若しくは他の表面に配線パターンをメッキ形成する工程と同時に行うことを特徴とする。   According to a fourth aspect of the present invention, there is provided a method for manufacturing a wiring board according to the third or fourth aspect, wherein the conductive member layer is plated on the inner surface of the first recess or the inner surface of the second recess. It is characterized in that it is performed simultaneously with the step of plating the wiring pattern on one surface or the other surface.

請求項4の配線基板の製造方法の発明によれば、改めて配線パターンをメッキ形成する必要がない。   According to the invention of the method for manufacturing a wiring board according to claim 4, it is not necessary to newly form the wiring pattern by plating.

本発明によれば、熱ストレスのもっとも大きな貫通孔の両端部の内面に形成された導電性部材層が薄くなり、そのため熱膨張差により発生する熱ストレスが小さく、そのため貫通孔との界面剥離や、基板クラックなどを防ぐことができ、また貫通孔の中央部が狭くなっているために、熱膨張差により発生する熱ストレスを小さくできる上に、仮にこの中央部での界面の剥離や、基板クラックが発生したとしても、貫通孔の内部であるため、導通や気密性などのトラブル発生を緩和することができる配線基板が提供でき、また該配線基板を簡便に製造できるという効果がある。   According to the present invention, the conductive member layers formed on the inner surfaces of both end portions of the through-hole having the largest thermal stress are thinned, so that the thermal stress generated due to the difference in thermal expansion is small, so that the interface peeling from the through-hole or In addition, since the central part of the through-hole can be narrowed, the thermal stress generated due to the difference in thermal expansion can be reduced, and the interface peeling at the central part and the substrate can be prevented. Even if a crack occurs, since it is inside the through-hole, it is possible to provide a wiring board that can alleviate troubles such as conduction and airtightness, and to produce the wiring board easily.

以下本発明を一実施形態により説明する。   The present invention will be described below with reference to an embodiment.

図1は、本実施形態の配線基板の要部の断面を示しており、基板1の一の表面1aと他の表面1bの間にビアホール4を貫通形成している。このビアホール4は、基板1の厚さ方向の中央部の内径が表面1a、1bにおける開口部の径より小さくなった鼓状の貫通孔2と、貫通孔2の内面全体を覆って貫通孔2の両端開口に端部が露出し、且つ貫通孔2の中央部を閉塞した導電性部材3の層とからなる。   FIG. 1 shows a cross section of the main part of the wiring board of the present embodiment, and a via hole 4 is formed between one surface 1a and the other surface 1b of the substrate 1. The via hole 4 includes a drum-shaped through hole 2 in which the inner diameter of the central portion in the thickness direction of the substrate 1 is smaller than the diameter of the opening in the surfaces 1 a and 1 b, and the entire inner surface of the through hole 2. It is composed of a layer of the conductive member 3 whose end portions are exposed at both end openings and the central portion of the through hole 2 is closed.

ここで、本実施形態では、基板1として、厚み300〜1000μm程度のシリコンウェハー、ガラスウェハー、アルミナ基板等を用い、貫通孔2は、断面が円形で両端開口部の内径が50〜500μm、中央部の内径が10〜100μm程度の寸法により形成している。ここで基板1の厚さとの関係により貫通孔2の内径寸法が上述の寸法以上よりも大きくなると、熱ストレスが増大し、逆に上述の形状寸法よりも小さくなると、孔加工及びその後の導電性部材3による孔閉塞が困難となる。   Here, in this embodiment, a silicon wafer having a thickness of about 300 to 1000 μm, a glass wafer, an alumina substrate, or the like is used as the substrate 1, and the through hole 2 has a circular cross section and an inner diameter of both end openings of 50 to 500 μm. The inner diameter of the part is formed with a dimension of about 10 to 100 μm. Here, when the inner diameter dimension of the through hole 2 is larger than the above-mentioned dimension due to the relationship with the thickness of the substrate 1, the thermal stress increases. It becomes difficult to close the hole by the member 3.

貫通孔2の形成方法は、特に限定はされないが、薬剤によるウエットエッチング、ドライエッチング、レーザー加工、ドリル加工、サンドブラスト加工等の方法を用いる。貫通孔2内面に形成される導電性部材3の層の厚みは、貫通孔2の両端部では3〜20μm程度としてある。つまりこれ以上厚くなると熱ストレスが増大して基板1への影響が大きくなる。また中央部を閉塞している層の厚みは10〜100μm程度としている。つまりこの厚みよりも薄くなると、気密性が不足し、逆に厚くなると、熱応力が増大する。   A method for forming the through-hole 2 is not particularly limited, but a method such as wet etching with chemicals, dry etching, laser processing, drilling, or sandblasting is used. The thickness of the layer of the conductive member 3 formed on the inner surface of the through hole 2 is about 3 to 20 μm at both ends of the through hole 2. That is, when the thickness is increased, the thermal stress increases and the influence on the substrate 1 increases. The thickness of the layer closing the central portion is about 10 to 100 μm. That is, if the thickness is less than this, the airtightness is insufficient, and conversely, if the thickness is increased, the thermal stress increases.

尚導電性部材3の形成方法は、特に限定されないが、導電性のペーストや、電解メッキなどが一般に用いられる方法を用いれば良い。   The method for forming the conductive member 3 is not particularly limited, but a method in which conductive paste, electrolytic plating, or the like is generally used may be used.

電解メッキでは、貫通孔2の内部に形成される通電のための導電性シード層として、スパッタ膜、無電解メッキ膜、CVD膜が用いられる。   In electrolytic plating, a sputtered film, an electroless plated film, or a CVD film is used as a conductive seed layer for energization formed inside the through hole 2.

次に本実施形態の配線基板の製造方法の実施例を説明する。   Next, an example of the method for manufacturing the wiring board according to the present embodiment will be described.

実施例1
本実施例の製造方法の工程を図2により説明する。
Example 1
The steps of the manufacturing method of this embodiment will be described with reference to FIG.

先ず上述の所定厚みの基板1を準備し(図2(a))、第1工程(図2(b))では、基板1の一の表面1a側にザグリ孔加工により、基板1の厚み方向の中央部に向けて内径が狭くなったテーパー状の第1の凹部2aを形成する。ここでのザグリ孔加工方法としては特に限定されないが、上述したようにウエットエッチング、ドライエッチング、レーザー加工、ドリル加工、サンドブラスト加工など適宜な方法を用いる。   First, the substrate 1 having the above-mentioned predetermined thickness is prepared (FIG. 2A), and in the first step (FIG. 2B), the thickness direction of the substrate 1 is formed by counterbored holes on one surface 1a side of the substrate 1. A tapered first concave portion 2a having an inner diameter narrowing toward the central portion is formed. The counterbore hole processing method here is not particularly limited, but as described above, an appropriate method such as wet etching, dry etching, laser processing, drilling, or sandblasting is used.

この第1工程の終了後、第2工程(図2(c))において、凹部2aの内面全体及び基板1表面に導電性シード薄膜を形成する。この導電性シード薄膜は通常0.05〜0.2μm厚みで、スパッタリング、無電解メッキ、CVD等を用いて形成する。この膜形成に用いる、金属種は、銅、金、ニッケル、クロム、チタン等を用い、複数の金属で多層としても良い。この導電性シード薄膜形後に、電解メッキによって、凹部2aの内面全体に亘るように導電性金属膜を形成する。この金属膜の金属種は、特に限定されないが銅、金、ニッケル等の導電率の高い金属を用いる。つまり導電性金属膜(導電性シード薄膜を含む)により導電性部材3が構成することになる。   After the completion of the first step, a conductive seed thin film is formed on the entire inner surface of the recess 2a and the surface of the substrate 1 in the second step (FIG. 2C). This conductive seed thin film is usually 0.05 to 0.2 μm thick and is formed by sputtering, electroless plating, CVD, or the like. The metal species used for the film formation may be copper, gold, nickel, chromium, titanium, or the like, and a plurality of metals may be used as a multilayer. After the conductive seed thin film is formed, a conductive metal film is formed over the entire inner surface of the recess 2a by electrolytic plating. Although the metal seed | species of this metal film is not specifically limited, A metal with high electrical conductivity, such as copper, gold | metal | money, nickel, is used. That is, the conductive member 3 is composed of a conductive metal film (including a conductive seed thin film).

さて第2工程終了後、次の第3工程(図2(d))で再度、基板1の他の表面1b側から、凹部2aの底部の導電性部材3の層に到達する深さで、凹部2aと同様なテーパー状の第2の凹部2bをザグリ加工により形成する。この形成方法は、第1工程と同じであるが、加工時に、凹部2aの底部の導電性部材3の層を破損しないように、注意深く精度良く加工する。この凹部2bと凹部2aの形成により中央部が導電性部材3の層で閉塞された貫通孔2が構成されることになる。   Now, after the end of the second step, in the next third step (FIG. 2 (d)), the depth reaches the layer of the conductive member 3 at the bottom of the recess 2a from the other surface 1b side of the substrate 1 again. A tapered second recess 2b similar to the recess 2a is formed by counterboring. This forming method is the same as the first step, but is carefully and accurately processed so that the layer of the conductive member 3 at the bottom of the recess 2a is not damaged during the processing. By forming the recess 2b and the recess 2a, the through hole 2 whose center is closed with the layer of the conductive member 3 is formed.

この第2の凹部2bの形成後、次の第4工程(図2(e))では、第2工法と同様に、導電性シード薄膜の形成後、電解メッキによって凹部2bの内面全体に導電性部材3の層を形成する。これにより凹部2a、2bの内面の導電性部材3が一体となって、貫通孔2の両端開口部に露出した導電性部材3の端部間の電気導通が取れることなる。   After the formation of the second recess 2b, in the next fourth step (FIG. 2 (e)), the conductive seed thin film is formed and the entire inner surface of the recess 2b is made conductive by electrolytic plating after the formation of the conductive seed thin film. The layer of member 3 is formed. As a result, the conductive members 3 on the inner surfaces of the recesses 2a and 2b are integrated, and electrical conduction between the end portions of the conductive member 3 exposed at the opening portions at both ends of the through hole 2 can be obtained.

さてその後、必要に応じて、基板1の両表面1a、1b側に形成された不要な導電性部材3の層を研磨或いはエッチングにより除去することで、図2(f)に示すように所望の配線基板の得られることになる。   Then, if necessary, the unnecessary layer of the conductive member 3 formed on both surfaces 1a and 1b of the substrate 1 is removed by polishing or etching, as shown in FIG. 2 (f). A wiring board is obtained.

実施例2
上記実施例1では基板1の一の表面1aに凹部2aの形成した後凹部2aへのメッキ加工を行い、その後他の表面1bに凹部2bを形成した後凹部2bへのメッキ加工を行っていたが、本実施例では、図3に示す工程により配線基板を製造する。
Example 2
In the first embodiment, the concave portion 2a is formed on one surface 1a of the substrate 1 and then the concave portion 2a is plated. Thereafter, the concave portion 2b is formed on the other surface 1b and then the concave portion 2b is plated. However, in this embodiment, a wiring board is manufactured by the process shown in FIG.

先ず図3(a)の基板準備、図3(b)での基板1への凹部2aのザグリ加工による孔形成までは実施例1と同じであるが、本実施例では凹部2aの形成後、第2工程で基板1の他の表面1bからの凹部2bの形成を同様にザグリ加工を行い、図3(c)に示すように基板1の両側表面1a、1bに貫通する貫通孔2を凹部2a、2bにより形成する。このとき、基板1の厚さ方向の貫通孔2の中央部の内径はできるだけ小さい径で形成することが望ましい、つまり大きな径になるとその後の電解メッキ工程で閉塞することが困難となる。   First, the substrate preparation in FIG. 3 (a) and the hole formation by counterboring the recess 2a in the substrate 1 in FIG. 3 (b) are the same as in Example 1, but in this example, after the formation of the recess 2a, In the second step, the recesses 2b are formed from the other surface 1b of the substrate 1 in the same manner, and the through holes 2 penetrating the side surfaces 1a and 1b of the substrate 1 are recessed as shown in FIG. 2a and 2b. At this time, it is desirable to form the inner diameter of the central portion of the through hole 2 in the thickness direction of the substrate 1 as small as possible, that is, when the diameter becomes large, it becomes difficult to block in the subsequent electrolytic plating process.

次の第2工程(図3(d))では、基板1の両側表面1a、1bから実施例1と同様な方法で導電性シード層を先ず貫通孔2内面全体に形成し、その後実施例1と同様に電解メッキを基板1の両側表面1a、1bから貫通孔2内面全体に実施して、貫通孔2の内面全体に銅、金、ニッケル等の導電率の高い金属からなる導電性部材3の層を形成する。このとき、できるだけ、基板1の表面1a、1bに近い貫通孔2の両端開口部の内面の導電性部材3の層の厚みを薄く、貫通孔2の中央部を平成する導電性部材3の厚みを厚く形成するために、メッキ液、メッキ条件を最適化する。   In the next second step (FIG. 3D), a conductive seed layer is first formed on the entire inner surface of the through hole 2 from both side surfaces 1a and 1b of the substrate 1 in the same manner as in the first embodiment, and then the first embodiment. Similarly to the above, electrolytic plating is performed on the entire inner surface of the through-hole 2 from both side surfaces 1a and 1b of the substrate 1, and the entire inner surface of the through-hole 2 is made of a conductive member 3 made of a metal having a high conductivity such as copper, gold or nickel. Forming a layer. At this time, the thickness of the conductive member 3 on the inner surface of the opening portions at both ends of the through hole 2 close to the surfaces 1a and 1b of the substrate 1 is made as thin as possible, and the thickness of the conductive member 3 covering the center of the through hole 2 is reduced. In order to form a thick film, the plating solution and the plating conditions are optimized.

その後、必要に応じて、基板1の両表面1a、1b側に形成された不要な導電性部材3の層を研磨或いはエッチングにより除去することで、図3(e)に示すように所望の配線基板の得られることになる。導電性部材3する必要がある。   Thereafter, if necessary, the layer of unnecessary conductive member 3 formed on both surfaces 1a and 1b of substrate 1 is removed by polishing or etching, so that a desired wiring as shown in FIG. A substrate is obtained. It is necessary to make the conductive member 3.

実施例3
,本実施例は、貫通孔2の内面導電性部材3を電解メッキにより形成する工程において同時に配線パターンを形成する方法である。
Example 3
In this embodiment, the wiring pattern is simultaneously formed in the step of forming the inner surface conductive member 3 of the through hole 2 by electrolytic plating.

図4は本実施例を実施例1において一の表面1a側に形成した凹部2aの内面に電解メッキを施す工程に採用した場合の細分化した工程を示す。   FIG. 4 shows a subdivided process in the case where this embodiment is adopted in the process of electrolytic plating the inner surface of the recess 2a formed on the one surface 1a side in the first embodiment.

先ず図4(a)に示すように基板1の表面1aに凹部2aを形成した後、先ず導電性シード層3aを凹部2aの内面及び基板1の表面1aに亘るように図4(b)に示すように形成し、その後図4(c)に示すように凹部2a及び配線パターン形成位置以外の導電性シード層3aの表面をレジスト6で覆い、その後電解メッキを施して貫通孔2の内面に導電性部材3を形成すると同時に導電性部材3と電気的に接続された配線パターン7を基板1の表面1aに配線パターン7も図4(d)に示すようにメッキ形成する。同様に基板1の他の表面1bに凹部2bを形成した後のメッキ工程にも図4(a)〜(d)と同様な過程を経て配線パターン7を形成する。   First, as shown in FIG. 4 (a), after forming a recess 2a on the surface 1a of the substrate 1, first, the conductive seed layer 3a is extended to the inner surface of the recess 2a and the surface 1a of the substrate 1 as shown in FIG. Then, as shown in FIG. 4C, the surface of the conductive seed layer 3a other than the recess 2a and the wiring pattern formation position is covered with a resist 6, and then electroplating is performed on the inner surface of the through hole 2 At the same time when the conductive member 3 is formed, the wiring pattern 7 electrically connected to the conductive member 3 is plated on the surface 1a of the substrate 1 as shown in FIG. Similarly, the wiring pattern 7 is formed through the same process as that shown in FIGS. 4A to 4D in the plating process after the recess 2b is formed on the other surface 1b of the substrate 1.

尚レジストは、シートレジスト、液状レジストを用い、配線パターン7の形成には、フォトリソグラフィー等によって形成する。   The resist is a sheet resist or a liquid resist, and the wiring pattern 7 is formed by photolithography or the like.

尚電解メッキによる配線パターン7の形成後は、図4(e)に示すようにレジスト6を剥離除去し、導電性シード層をエッチングなどで除去する。   After the formation of the wiring pattern 7 by electrolytic plating, the resist 6 is peeled off as shown in FIG. 4E, and the conductive seed layer is removed by etching or the like.

図4は、実施例1におけるメッキ工程に本実施例を採用した場合の流れを示しているが、実施例2のように両側表面1a、1bに貫通する貫通孔2を先に形成した後、基板1の両側表面1a、1bから同時に電解メッキを施す場合には、両側において図4(a)〜(d)の過程を同時に進行させれば良い。   FIG. 4 shows the flow when the present embodiment is adopted in the plating process in the first embodiment. After forming the through holes 2 penetrating the both side surfaces 1a and 1b as in the second embodiment, When electrolytic plating is performed simultaneously from both side surfaces 1a and 1b of the substrate 1, the processes shown in FIGS. 4A to 4D may be performed simultaneously on both sides.

一実施形態の配線基板の要部の断面図である。It is sectional drawing of the principal part of the wiring board of one Embodiment. 一実施形態の配線基板を製造する方法の実施例1の工程説明図である。It is process explanatory drawing of Example 1 of the method of manufacturing the wiring board of one Embodiment. 一実施形態の配線基板を製造する方法の実施例2の工程説明図である。It is process explanatory drawing of Example 2 of the method of manufacturing the wiring board of one Embodiment. 一実施形態の配線基板を製造する方法の実施例4のメッキ工程の説明図である。It is explanatory drawing of the plating process of Example 4 of the method of manufacturing the wiring board of one Embodiment. 従来例の配線基板の要部の断面図である。It is sectional drawing of the principal part of the wiring board of a prior art example.

符号の説明Explanation of symbols

1 基板
1a、1b 表面
2 貫通孔
3 導電性部材
4 ビアホール
DESCRIPTION OF SYMBOLS 1 Board | substrate 1a, 1b Surface 2 Through-hole 3 Conductive member 4 Via hole

Claims (4)

基板の一の表面と他の表面の間に、前記基板の厚さ方向の中央部が一の表面側及び他の表面側より狭くなる貫通孔と、前記貫通孔の内面に沿うように形成されて、前記貫通孔の両端開口に両端部を露出させ、且つ前記貫通孔の中央部のみを閉塞した導電性部材層とからなるビアホールを有することを特徴とする配線基板。 Between the one surface and the other surface of the substrate, a central portion in the thickness direction of the substrate is formed so as to be along the inner surface of the through hole and the through hole in which the central portion is narrower than the one surface side and the other surface side. And a via hole comprising a conductive member layer having both end portions exposed at both end openings of the through hole and having only the center portion of the through hole closed. 請求項1の配線基板の製造方法であって、基板の一の表面から基板の厚さ方向の中央部に向けて狭くなるテーパー状の第1の凹部を形成する工程と、前記第1の凹部の内面に導電性部材層をメッキ形成する工程と、前記基板の他の表面から前記第1の凹部の底部に達し且つ該底部方向に狭くなるテーパー状の第2の凹部を形成する工程と、前記第1の凹部の内面に導電性部材層をメッキする工程とからなることを特徴とする配線基板の製造方法。 2. The method of manufacturing a wiring board according to claim 1, wherein a step of forming a tapered first concave portion that narrows from one surface of the substrate toward a central portion in the thickness direction of the substrate, and the first concave portion. Forming a conductive member layer on the inner surface of the substrate, forming a tapered second recess that reaches the bottom of the first recess from the other surface of the substrate and narrows in the bottom direction; and And a step of plating a conductive member layer on the inner surface of the first recess. 請求項1の配線基板の製造方法であって、基板の一の表面から該基板の厚さ方向の中央部に向けて狭くなるテーパー状の第1の凹部を形成する工程と、前記基板の他の表面から前記第1の凹部の底部に連通し且つ該底部方向に狭くなるテーパー状の第2の凹部を形成する工程と、前記基板の一の表面側、他の表面側の各々から、前記第1の凹部の内面、第2の凹部の内面に導電性部材層をメッキ形成するとともに両凹部の連通部を前記導電性部材層で閉塞する工程とからなることを特徴とする配線基板の製造方法。 2. The method of manufacturing a wiring board according to claim 1, wherein a step of forming a tapered first concave portion that narrows from one surface of the substrate toward a central portion in the thickness direction of the substrate; Forming a tapered second recess that communicates with the bottom of the first recess from the surface of the substrate and narrows in the direction of the bottom, and from each of the one surface side and the other surface side of the substrate, And a step of forming a conductive member layer on the inner surface of the first concave portion and the inner surface of the second concave portion, and closing the communicating portion of both concave portions with the conductive member layer. Method. 前記第1の凹部の内面若しくは第2の凹部の内面への導電性部材層のメッキ形成を、前記基板の一の表面若しくは他の表面に配線パターンをメッキ形成する工程と同時に行うことを特徴とする請求項2又は3の配線基板の製造方法。 The plating of the conductive member layer on the inner surface of the first recess or the inner surface of the second recess is performed simultaneously with the step of plating the wiring pattern on one surface or the other surface of the substrate. A method for manufacturing a wiring board according to claim 2 or 3.
JP2005147257A 2005-05-19 2005-05-19 Wiring board manufacturing method Expired - Fee Related JP4622672B2 (en)

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JP2012104819A (en) * 2010-11-09 2012-05-31 Samsung Electro-Mechanics Co Ltd Printed circuit board and filling method for via hole thereof
KR101232889B1 (en) 2011-08-03 2013-02-13 (주) 이피웍스 A semiconductor substrate having through via and a method of manufacturing thereof
CN111511103A (en) * 2019-01-31 2020-08-07 奥特斯奥地利科技与系统技术有限公司 Low overhang component carrier with through holes having different front and rear window sizes
DE102020102362B4 (en) 2019-01-31 2021-12-30 At & S Austria Technologie & Systemtechnik Aktiengesellschaft Component carrier with bridge structure in a through hole that meets the design rule for the minimum clearance

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JP2005093934A (en) * 2003-09-19 2005-04-07 Shinko Electric Ind Co Ltd Filling method into through-hole
JP2006041463A (en) * 2004-07-27 2006-02-09 Kinko Denshi Kofun Yugenkoshi Conductive column manufacturing method and circuit board having conductive column

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JPH02133988A (en) * 1988-11-15 1990-05-23 Shindo Denshi Kogyo Kk Formation of through hole of both-side plastic film circuit board
JPH05315744A (en) * 1992-05-14 1993-11-26 Sharp Corp Manufacture of film board
JPH11243267A (en) * 1998-02-25 1999-09-07 Kyocera Corp Wiring board
JP2003046248A (en) * 2001-08-02 2003-02-14 Ibiden Co Ltd Lamination wiring board and its manufacturing method
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012104819A (en) * 2010-11-09 2012-05-31 Samsung Electro-Mechanics Co Ltd Printed circuit board and filling method for via hole thereof
CN102573334A (en) * 2010-11-09 2012-07-11 三星电机株式会社 Printed circuit board and method for filling via hole thereof
KR101232889B1 (en) 2011-08-03 2013-02-13 (주) 이피웍스 A semiconductor substrate having through via and a method of manufacturing thereof
CN111511103A (en) * 2019-01-31 2020-08-07 奥特斯奥地利科技与系统技术有限公司 Low overhang component carrier with through holes having different front and rear window sizes
DE102020102362B4 (en) 2019-01-31 2021-12-30 At & S Austria Technologie & Systemtechnik Aktiengesellschaft Component carrier with bridge structure in a through hole that meets the design rule for the minimum clearance
US11546990B2 (en) 2019-01-31 2023-01-03 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Component carrier with bridge structure in through hole fulfilling minimum distance design rule

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