JP2006319446A - Frequency-dividing circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a frequency-dividing circuit for stably generating a pulse signal for generating a sawtooth wave signal having a frequency of one third of the frequency of an input signal. <P>SOLUTION: A T-flip-flop 21 inverts an output state in synchronization with the rising edge of a pulse signal B generated by an oscillator 10. A T-flip-flop 22 inverts an output state in synchronization with the rising edge of a logical signal C outputted from a Q_terminal of the T-flip-flop 21. An OR circuit 26 outputs the OR of the logical signal C and the logical signal D outputted from the Q_terminal of the T-flip-flop 22. A delay circuit 27 generates a delay signal E by delaying the rising edge of an output signal of the OR circuit 26. An AND circuit 28 resets the T-flip-flop 21 by utilizing the delay signal E. The pulse signal obtained by inverting the logic of the delay signal E is given to a sawtooth wave generation circuit 30. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a frequency dividing circuit that divides an input signal by 1/3, and more particularly to a frequency dividing circuit for generating a sawtooth signal having a frequency that is 1/3 of the input signal.

Conventionally, sawtooth signals have been used in various electric circuits. In some cases, sawtooth signals of various frequencies are required.
FIG. 3 is a diagram showing a configuration of a conventional signal generation circuit that generates a sawtooth signal having a desired frequency. Assume that the signal generation circuit 100 shown in FIG. 3 generates a sawtooth signal having a frequency that is 1/3 of the input rectangular wave signal.

  The frequency dividing circuit 101 is a frequency dividing circuit that divides the input signal a by 1/3, and is described in Patent Document 1, for example. The 1/3 frequency divider circuit described in Patent Document 1 is composed of an exclusive OR gate and two flip-flops, and divides the input rectangular wave signal by 1/3 to obtain a 50% duty rectangular wave signal. Is generated.

  The frequency-divided signal b output from the frequency dividing circuit 101 is given to the input terminal A of the exclusive OR circuit 102. Further, the delay circuit 103 generates a delay signal c by delaying the frequency-divided signal b, and supplies the delayed signal c to the input terminal B of the exclusive OR circuit 102. Note that the delay circuit 103 delays only the rising edge of the divided signal b. Then, the sawtooth signal generation circuit 110 generates the sawtooth signal e using the pulse signal d output from the exclusive OR circuit 102. The sawtooth signal generation circuit 110 includes a current source 111, a capacitor C that charges a current generated by the current source 111, and an nMOS transistor that discharges the capacitor C according to a pulse signal d.

  FIG. 4 is a timing chart for explaining the operation of the signal generation circuit 100 shown in FIG. In FIG. 4, the frequency-divided signal b is 1/3 of the frequency of the input signal a, and its duty is 50%. Note that the 1/3 frequency dividing circuit described in Patent Document 1 generates a 50% duty frequency divided signal.

  The delay signal c is a rectangular wave signal obtained by delaying only the rising edge of the divided signal b. Therefore, the pulse signal d generated by the exclusive OR circuit 102 becomes H level only during the period from the rising edge of the divided signal b to the rising edge of the delay signal c. Thereby, a pulse signal d in which a narrow pulse is repeated at a predetermined period is obtained. The pulse signal d is applied to the gate of the nMOS transistor included in the sawtooth signal generation circuit 110.

  The nMOS transistor is in the off state during the period when the L level is applied to the gate. During this period, the capacitor C is charged and the output voltage rises linearly over time. Subsequently, when an H level is applied to the gate, the nMOS transistor is turned on and the capacitor C is discharged. As a result, the output voltage decreases rapidly. Then, the sawtooth signal e is generated by repeating this operation in accordance with the pulse signal d. As described above, in order to generate the sawtooth signal, a pulse signal having a narrow pulse width and a predetermined frequency is required.

  Here, in the signal generation circuit 100 shown in FIG. 3, the pulse signal d is generated from the frequency-divided signal b and the delayed signal c input to the exclusive OR circuit 102. The frequency-divided signal b and the delayed signal c It is difficult to make the timings of the falling edges completely coincide with each other. If the timings of the falling edges of the frequency-divided signal b and the delayed signal c do not coincide with each other, a pulse x is generated in accordance with the timing difference as shown by a broken line in FIG. Then, the nMOS transistor is turned on by this pulse x, the capacitor C is discharged, and the voltage drops, so that the waveform of the sawtooth signal is deformed. That is, a stable sawtooth signal cannot be obtained.

As described above, in the conventional technique, it is difficult to generate a pulse signal having a narrow pulse width for generating a sawtooth signal having a frequency of 1/3 of the input signal. For this reason, a stable sawtooth signal having a frequency 1/3 of the input signal could not be obtained.
Japanese Patent Laid-Open No. 5-48432 (FIGS. 1 and 2, paragraphs 0010 to 0016 of the specification)

  An object of the present invention is to provide a frequency dividing circuit for generating a stable sawtooth signal having a frequency 1/3 of an input signal or a pulse signal for generating a sawtooth signal having a frequency 1/3 of an input signal. Is to provide.

  The frequency dividing circuit of the present invention outputs a first flip-flop whose output state is inverted in synchronization with one of a rising edge and a falling edge of an input signal having a predetermined frequency, and the first flip-flop. A second flip-flop whose output state is inverted in synchronization with one of a rising edge and a falling edge of the signal, an output signal of the first flip-flop, and an output signal of the second flip-flop; The signal output when the first flip-flop is reset and the inverted signal are output from the first flip-flop, and either the inverted signal or the non-inverted signal is output from the second flip-flop. A logic circuit that outputs a logic signal that sometimes inverts the state of the output, and resets the first flip-flop based on the logic signal A set circuit, a.

  In the frequency dividing circuit, when the first edge (one of the rising edge and the falling edge) of the input signal is given when the first and second flip-flops are in a predetermined initial state, The output of the flip-flop is inverted. Subsequently, when the output of the first flip-flop is inverted by the second edge, the output of the second flip-flop is also inverted. Further, when the output of the first flip-flop is inverted by the third edge, the output of the logic circuit changes and the first flip-flop is reset. Then, the output of the first flip-flop is inverted to return to the initial state, and the output of the second flip-flop is also inverted again to return to the initial state. As a result, the output of the logic circuit also returns to the original state. In this way, one pulse is generated at the output of the logic circuit for three edges of the input signal. That is, 1/3 frequency division is realized.

  Since the width (time) of the pulse output from the logic circuit corresponds to the time required to reset the first flip-flop, it becomes narrower (shorter). Therefore, a pulse signal having a narrow pulse width suitable for generating a stable sawtooth signal can be obtained by using a delay circuit in combination as necessary.

  One set of inputs to the OR circuit is the output signals of the first and second flip-flops. Here, since the second flip-flop operates in accordance with the output signal of the first flip-flop, the timings of the output signals of the first and second flip-flops are not shifted from each other. For this reason, unnecessary pulses are not generated at the output of the OR circuit. Therefore, if a sawtooth signal is generated using this signal, a stable sawtooth signal can be obtained.

  The frequency dividing circuit further includes a delay circuit that delays one of a rising edge and a falling edge of the logic signal, and the reset circuit resets the first flip-flop according to an output of the delay circuit. May be. According to this configuration, the first flip-flop can be reliably reset.

  In the frequency divider circuit, the input signal may be a pulse signal obtained when generating a sawtooth signal. In this case, as an example, a first current source that generates a constant current, a first capacitor that is charged by the first current source, a voltage of the first capacitor, and a reference voltage are compared. A comparator and a first switch for discharging the first capacitor when the voltage of the first capacitor becomes higher than the reference voltage are further provided. The output of the comparator is used as an input signal to the first flip-flop. According to this configuration, a signal having a frequency 1/3 of the sawtooth signal can be generated.

  Further, the frequency dividing circuit is charged by a delay circuit that delays one of the rising edge and the falling edge of the logic signal, a second current source that generates a constant current, and the second current source. You may make it further have a 2nd switch which discharges the said 2nd capacitor according to the output of the said 2nd capacitor | condenser and the said delay circuit. According to this configuration, a stable sawtooth signal having a frequency 1/3 of the input signal is generated.

  According to the present invention, it is possible to stably generate a sawtooth signal having a frequency of 1/3 of an input signal or a pulse signal for generating a sawtooth signal having a frequency of 1/3 of an input signal.

FIG. 1 is a diagram illustrating a configuration of a frequency divider circuit according to an embodiment of the present invention. The frequency divider 1 of the embodiment shown in FIG. 1 includes an oscillator 10, a frequency divider 20, and a sawtooth signal generation circuit 30.
The oscillator 10 includes a current source (first current source) 11, a capacitor (first capacitor) C1, a comparator 12, and an nMOS transistor (first switch) M1, and includes a sawtooth signal A and a pulse signal having a predetermined frequency. B is generated. The current source 11 generates a constant current. The capacitor C1 is provided between the current source 11 and the ground (ground), and is charged by the current generated by the current source 11. Therefore, during the period when the nMOS transistor M1 is in the OFF state, the voltage Vc1 across the capacitor C1 rises linearly with time. The comparator 12 compares the voltage Vc1 with a preset reference voltage Vref. If the reference voltage Vref is higher than the voltage Vc1, “L” is output, and if the voltage Vc1 is higher than the reference voltage Vref, “H” is output.

  The drain of the nMOS transistor M1 is connected to the positive terminal of the capacitor C1, and its source is grounded. Further, the output signal of the comparator 12 is given to the gate of the nMOS transistor M1. When the nMOS transistor M1 is controlled to be in an ON state, the charge charged in the capacitor C1 is discharged through the nMOS transistor M1.

In the oscillator 10 configured as described above, the voltage Vc1 is output as the sawtooth signal A. The output of the comparator 12 is output as a pulse signal B synchronized with the sawtooth signal A.
The frequency divider 20 includes T flip-flops 21 and 22, inverting circuits 23, 24 and 25, an OR circuit 26 (logic circuit), a delay circuit 27, and an AND circuit 28. The T flip-flop is a circuit element whose output state (H level / L level) is inverted by an input edge (rising edge or falling edge). Further, when an L level signal is applied to the reset terminal (R_) of the T flip-flop, the Q output and the Q_ output are forcibly set to “L” and “H”, respectively. That is, at reset, the Q output becomes “L” and the Q_ output becomes “H”.

  The pulse signal B generated by the oscillator 10 is given to the T input of the T flip-flop 21. The pulse signal B is applied to the T_ input of the T flip-flop 21 after the logic is inverted by the inverting circuit 23. Then, the Q_ output of the T flip-flop 21 is given to the T input of the T flip-flop 22 as the logic signal C. The logic signal C is applied to the T_ input of the T flip-flop 22 after the logic is inverted by the inverting circuit 24.

  The Q_ output of the T flip-flop 22 is given to one input terminal of the OR circuit 26 as a logic signal D. A logic signal C is supplied to the other input terminal of the OR circuit 26. That is, in the OR circuit 26, the logic signal C which is the Q_ output of the T flip-flop 21 becomes a signal (L level) obtained by inverting the signal (H level) output at the time of reset, and the T flip-flop 22 When the Q_ output becomes an L level that is one of an inverted signal and a non-inverted signal, a logic signal for inverting the output state from the H level to the L level is output.

  The delay circuit 27 generates a delay signal E by delaying the output of the OR circuit 26. Here, the delay circuit 27 delays only the rising edge of the output signal of the OR circuit 26. Further, the inverting circuit 25 generates the pulse signal F by inverting the logic of the delay signal E.

  An H level signal is fixedly given to one input terminal of the AND circuit (reset circuit) 28, and a delay signal E is given to the other input terminal. The output of the AND circuit 28 is given to the reset terminal R_ of the T flip-flop 21 as a reset signal.

  The sawtooth signal generation circuit 30 generates a sawtooth signal G using the pulse signal F output from the frequency divider 20. Here, the current source (second current source) 31 generates a constant current. The capacitor (second capacitor) C2 is provided between the current source 31 and the ground (ground), and is charged by the current generated by the current source 31. The drain of the nMOS transistor (second switch) M2 is connected to the positive terminal of the capacitor C2, and its source is grounded. Further, a pulse signal F is given to the gate of the nMOS transistor M2. When the nMOS transistor M2 is controlled to be turned on by the pulse signal F, the charge charged in the capacitor C2 is discharged.

Next, the operation of the frequency dividing circuit 1 of the embodiment will be described. First, the operation of the oscillator 10 is as follows.
When the voltage Vc1 is lower than the reference voltage Vref, the output of the comparator 12 is L level, and the nMOS transistor M1 is in the off state. Therefore, the capacitor C1 is charged by the current source 11, and the voltage Vc1 (that is, the potential of the sawtooth signal A) increases linearly with time. When the voltage Vc1 exceeds the reference voltage Vref, the output of the comparator 12 changes from the L level to the H level, and the nMOS transistor M1 is controlled to be on. Then, the capacitor C1 is rapidly discharged, and the voltage Vc1 is instantaneously lowered to the ground potential. As a result, since the voltage Vc1 becomes lower than the reference voltage Vref, the nMOS transistor M1 is turned off again, and the voltage Vc1 increases.

  The sawtooth signal A is generated by repeating the above operation. Here, the frequency of the sawtooth signal A is determined by the current generated by the current source 11, the capacitance of the capacitor C1, and the reference voltage Vref. Further, the output of the comparator 12 is output as a pulse signal B. That is, the pulse signal B is obtained when generating the sawtooth signal A and has the same frequency as the sawtooth signal A.

  Next, the operation of the frequency divider circuit 1 of the embodiment will be described with reference to the timing chart shown in FIG. Prior to time T1, it is assumed that the Q_outputs of the T flip-flops 21 and 22 are both at the H level.

  At time T1, the rising edge of pulse signal B is applied to the T input of T flip-flop 21 (the falling edge of pulse signal B is applied to the T_ input of T flip-flop 21). Then, the Q_ output (logic signal C) of the T flip-flop 21 changes from the H level to the L level. In this case, since the falling edge is given to the T input of the T flip-flop 22, the Q_ output (logic signal D) is kept at the H level without changing. At this time, the Q_ output of the T flip-flop 21 becomes a signal (L level) obtained by inverting the signal (H level) output at the time of resetting, but the Q_ output of the T flip-flop 22 is at the H level. The output of 26 maintains the H level.

  When the next rising edge of the pulse signal B is applied to the T input of the T flip-flop 21 at time T2, the Q_ output (logic signal C) of the T flip-flop 21 changes from the L level to the H level. In this case, since a rising edge is given to the T input of the T flip-flop 22, the Q_ output (logic signal D) changes from the H level to the L level.

  When the next rising edge of the pulse signal B is applied to the T input of the T flip-flop 21 at time T3, the Q_ output (logic signal C) of the T flip-flop 21 changes from the H level to the L level. That is, the Q_ output of the T flip-flop 21 becomes a signal (L level) obtained by inverting the signal (H level) output at reset. At this time, the Q_ output (logic signal D) of the T flip-flop 22 is at the L level. Therefore, the output of the OR circuit 26 changes from H level to L level, and the output of the delay circuit 27 (delay signal E) also becomes L level. Then, the output of the AND circuit 28 becomes L level, and the T flip-flop 21 is reset.

  When the T flip-flop 21 is reset, its Q_ output (logic signal C) is forcibly fixed to the H level. Then, since a rising edge is given to the T input of the T flip-flop 22, the Q_output (logic signal D) of the T flip-flop 22 changes from the L level to the H level. As a result, the output of the OR circuit 26 changes from L level to H level, and the output of the delay circuit 27 (delay signal E) also becomes H level. That is, the T flip-flop 21 is released from the reset state. As a result, the T flip-flops 21 and 22 return to the state before time T1.

  The pulse signal F is obtained by inverting the logic of the output of the delay circuit 27 (delay signal E). That is, the pulse signal F has a pulse at time T3. Here, the pulse width of this pulse (the time during which the pulse signal F is at the H level) corresponds to the delay time of the delay circuit 27, and is the time that can sufficiently discharge the capacitor C2 of the sawtooth signal generation circuit 30. is there.

  Thereafter, the above-described operation is repeated. As a result, only one pulse of the pulse signal F is generated for the three pulses of the pulse signal B. In other words, 1/3 frequency division is realized in the frequency divider 20. Since the signal is output to the AND circuit 28 via the delay circuit 27, the output of the AND circuit 28 is maintained at the L level for the delay time of the delay circuit 27, and the reset time of the T flip-flop 21 is long. Even if it can be reset reliably.

  The sawtooth signal generation circuit 30 generates a sawtooth signal G using the pulse signal F. First, during a period in which the pulse signal F is at the L level, the nMOS transistor M2 is in an off state, and the capacitor C2 is charged by the current source 31. That is, the potential of the capacitor C2 increases linearly with time. When a pulse of the pulse signal F is given, the nMOS transistor M2 is turned on and the capacitor C2 is rapidly discharged. As a result, the potential of the capacitor C2 instantaneously drops to the ground level. Thereafter, the sawtooth signal G is generated by repeating this operation. That is, the sawtooth signal G is generated without generating a PWM signal divided by 1/3.

As described above, according to the frequency dividing circuit 1 of the embodiment, a stable sawtooth signal G having a frequency of 1/3 of the pulse signal B is generated.
Further, the reset terminal R_ of the T flip-flop 22 is not reset and operates depending only on the output of the T flip-flop 21. Therefore, the circuit configuration does not become complicated, and it is not necessary to consider the output in the reset state of the T flip-flop 22, and the design is easy.

  As described above, the frequency divider 20 includes the logical sum circuit 26 that calculates the logical sum of the logical signals C and D. For this reason, for example, if the falling edge of the logic signal D occurs before the rising edge of the logic signal C in the vicinity of the time T2, for example, the pulse signal F instantaneously becomes H level, and the sawtooth signal G The waveform will collapse. However, actually, since the falling edge of the logic signal D is caused by the rising edge of the logic signal C, the falling edge of the logic signal D cannot occur before the rising edge of the logic signal C. . Therefore, the pulse signal F does not include unnecessary pulses other than the pulse obtained by dividing the pulse signal B by 1/3, and the waveform of the sawtooth signal G is stabilized.

  Further, the sawtooth signals A and G in the above-described embodiment are waveforms that rapidly drop to the ground level when the nMOS transistors M1 and M2 are turned on, but are not limited thereto. That is, the sawtooth signals A and G may be, for example, waveforms that alternately repeat a section that rises linearly and a section that falls linearly over time. Such a waveform is realized by providing a resistor between the nMOS transistors M1 and M2 and the ground.

  In the above-described embodiment, the outputs of both the T flip-flops 21 and 22 are inverted in synchronization with the rising edge. However, the outputs may be synchronized with the falling edge. The downlink edges may be synchronized separately.

  In the above-described embodiment, the pulse signal B is input to the frequency divider 20 as an input signal. However, a PWM signal having an arbitrary duty may be used. Any signal can be used as long as the first flip-flop can recognize the rising edge or the falling edge at a predetermined frequency.

  Further, in the above-described embodiment, the logical sum circuit 26 is such that the logical signal C that is the Q_ output of the T flip-flop 21 becomes a signal (L level) obtained by inverting the signal (H level) output at the time of resetting. When the Q_ output of the T flip-flop 22 becomes an L level that is one of an inverted signal and a non-inverted signal, a logic signal that inverts the output state from the H level to the L level is output. For example, the OR circuit 26 may output a logic signal that inverts the output state from the H level to the L level when the Q_ output of the T flip-flop 22 becomes the H level that is the other of the inverted signal and the non-inverted signal. .

  Furthermore, in the above-described embodiment, two T flip-flops are provided, but an equivalent function may be realized by another circuit (for example, a JK flip-flop).

It is a figure which shows the structure of the frequency divider circuit of embodiment of this invention. It is a timing chart explaining operation | movement of the frequency divider circuit of embodiment. It is a figure which shows the structure of the conventional signal generation circuit which produces | generates the sawtooth signal of a desired frequency. 4 is a timing chart for explaining the operation of the signal generation circuit shown in FIG. 3.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Frequency dividing circuit 10 Oscillator 11 Current source 12 Comparator 20 Frequency divider 21, 22 T flip-flop 23-25 Inverting circuit 26 OR circuit 27 Delay circuit 28 AND circuit 30 Saw-wave signal generation circuit 31 Current source

Claims (5)

A first flip-flop whose output state is inverted in synchronization with one of a rising edge and a falling edge of an input signal having a predetermined frequency;
A second flip-flop whose output state is inverted in synchronization with one of a rising edge and a falling edge of a signal output from the first flip-flop;
The output signal of the first flip-flop and the output signal of the second flip-flop are input, and the signal output when the first flip-flop is reset and the inverted signal are output from the first flip-flop. And a logic circuit that outputs a logic signal that inverts the output state when either the inverted signal or the non-inverted signal is output from the second flip-flop;
A reset circuit for resetting the first flip-flop based on the logic signal;
A frequency divider circuit.   2. The delay circuit for delaying one of a rising edge and a falling edge of the logic signal, and the reset circuit resets the first flip-flop according to an output of the delay circuit. A frequency divider circuit according to 1. The frequency dividing circuit according to claim 1, wherein the input signal is a pulse signal obtained when a sawtooth signal is generated. A first current source that generates a constant current;
A first capacitor charged by the first current source;
A comparator that compares the voltage of the first capacitor with a reference voltage;
A first switch for discharging the first capacitor when the voltage of the first capacitor becomes higher than the reference voltage;
The frequency dividing circuit according to claim 1, wherein an output of the comparator is an input signal to the first flip-flop. A delay circuit for delaying one of the rising edge and the falling edge of the logic signal;
A second current source that generates a constant current;
A second capacitor charged by the second current source;
A second switch for discharging the second capacitor according to the output of the delay circuit;
The frequency dividing circuit according to claim 1, further comprising:

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