JP2006318967A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress the deterioration of clock jitter, and to suppress malfunction in a semiconductor integrated circuit caused by deteriorating the clock jitter while a clock signal is propagated inside the semiconductor integrated circuit. <P>SOLUTION: A power line 112 for data circuits supplies a supply voltage to a data circuit 111. A power line 122 for clock circuits supplies a power voltage to a clock circuit 121. The power lines 112, 122 are connected to a power line provided on a line layer (for example, an upper layer as compared with the power line 112 for data circuits and that 122 for clock ones) that differs from the line layer of at least one of the power line 112 for data circuits and that 122 for clock ones through a via, thus reducing power noise generated by the data circuit 111, and suppressing the deterioration of the clock jitter. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit having a data circuit for performing signal processing on an input signal and a clock circuit for supplying a clock signal to the data circuit. In particular, the present invention relates to a clock jitter generated in the semiconductor integrated circuit. It relates to the technology to suppress.

  Circuits included in the semiconductor integrated circuit are classified into two types: a data circuit that performs signal processing on an input signal and a clock circuit that supplies a clock signal to the data circuit. A clock signal input from a PLL circuit or a clock input terminal in the semiconductor integrated circuit propagates through the clock circuit and is input to the data circuit, and the data circuit operates in synchronization with the input clock signal.

  A conventional semiconductor integrated circuit that performs digital signal processing in synchronization with an input signal input from the outside is configured, for example, as shown in FIG.

  The semiconductor integrated circuit 600 includes a clock input terminal 610, a data circuit 620, a clock circuit 630, a power supply terminal 640, and a standard cell power supply wiring 650.

  A clock signal is input to the clock input terminal 610 from the outside of the semiconductor integrated circuit 600.

  The data circuit 620 includes a buffer, a logic gate, or a flip-flop, and performs signal processing on an input signal.

  The clock circuit 630 is configured by a buffer, a logic gate, a flip-flop, or the like, and supplies a clock signal input via the clock input terminal 610 to the data circuit 620.

  A power supply voltage is supplied from the outside of the semiconductor integrated circuit 600 to the power supply terminal 640.

  The standard cell power supply wiring 650 supplies the power supply voltage input from the power supply terminal 640 to the data circuit 620 and the clock circuit 630.

That is, in the above configuration, power used by the data circuit 620 and the clock circuit 630 is supplied from the common standard cell power supply wiring 650, and the data circuit 620 and the clock circuit 630 are clearly defined inside the semiconductor integrated circuit 600. (See, for example, Non-Patent Document 1).
“Design and Prototyping of Digital Integrated Circuits” Baifukan VDEC Supervision Kunihiro Asada, Section 125, Figure 7.23

  However, when power is consumed by the data circuit 620 operating in synchronization with the input clock signal, the power supply potential of the data circuit 620 changes and power supply noise occurs. The power supply noise generated in the data circuit 620 propagates to the clock circuit 630 in the vicinity of the data circuit 620 via the standard cell power supply wiring 650.

  For this reason, the power supply potential of the clock circuit 630 varies by substantially the same amount as the amount of change in the power supply potential of the data circuit 620. At this time, if the change time of the power supply potential of the clock circuit 630 and the time when the clock signal input from the PLL circuit or the clock input terminal 610 reaches the clock circuit 630 are overlapped, the clock circuit 630 is used. The delay time of the transistor varies.

  All the transistors constituting the data circuit 620 do not always operate in synchronization with the clock signal, and different transistors operate in each clock cycle. For this reason, the fluctuation amount of the power supply potential of the clock circuit 630 is different every clock cycle. As a result, the amount of delay time variation of the transistors in the clock circuit 630 is different in each clock cycle, which causes a deterioration in clock jitter.

  When jitter occurs in the clock signal, in the data circuit 620 to which the clock signal is input, the timing margin becomes narrower according to the amount of jitter, and for example, the probability that data mis-latch due to deterioration of the clock jitter increases, The malfunction probability of the semiconductor integrated circuit is increased.

  The present invention has been made paying attention to the above-described problem, and is caused by the deterioration of the clock jitter while suppressing the deterioration of the clock jitter and the clock signal being propagated in the semiconductor integrated circuit. An object of the present invention is to provide a semiconductor integrated circuit capable of suppressing malfunction.

In order to solve the above problems, the invention of claim 1
A semiconductor integrated circuit having a data circuit that performs signal processing on an input signal and a clock circuit for supplying a clock signal to the data circuit,
A data circuit power supply wiring for supplying a power supply voltage to the data circuit;
A clock circuit power supply wiring for supplying a power supply voltage to the clock circuit;
A voltage drop portion provided between the power wiring for the data circuit and the power wiring for the clock circuit, and causing a voltage drop with respect to an alternating current component;
The data circuit and the power wiring for the data circuit are formed in the data cell region of the substrate divided into the data cell region and the clock cell region,
The clock circuit and the power supply wiring for the clock circuit are formed in the clock cell region.

The invention of claim 2
The semiconductor integrated circuit according to claim 1, comprising:
The voltage drop unit is
Another layer power supply wiring provided in a wiring layer different from the wiring layer of at least one of the power wiring for the data circuit and the power wiring for the clock circuit,
It has a via for connecting at least one of the power wiring for the data circuit and the power wiring for the clock circuit and the other layer power wiring.

The invention of claim 3
The semiconductor integrated circuit according to claim 1, comprising:
The voltage drop unit is a coil.

  As a result, even if power supply noise occurs in the data circuit, the noise can be reduced by the voltage drop unit. Therefore, the power supply potential fluctuation amount of the clock circuit can be suppressed and the delay time fluctuation of the clock circuit can be suppressed. This makes it possible to reduce the amount of jitter in the clock signal. In addition, when the amount of jitter of the clock signal is suppressed, the timing margin in the data circuit becomes wider, the probability of occurrence of data mislatch caused by clock jitter in the data circuit is reduced, and the malfunction probability of the semiconductor integrated circuit. Is reduced.

The invention of claim 4
The semiconductor integrated circuit according to claim 1, comprising:
A plurality of the clock cell regions are provided on the substrate,
When the clock circuit power supply wiring in each clock cell region is connected to the clock circuit power supply wiring in another clock cell region, it is connected via the voltage drop unit.

  As a result, even when the power supply wiring is connected between the clock cell regions, the power supply noise can be reduced, and the jitter generation amount of the clock signal can be reduced.

The invention of claim 5
The semiconductor integrated circuit according to claim 4, comprising:
The clock circuit in each clock cell region is configured to be supplied with only one clock signal different from the clock circuits in other clock cell regions.

  As a result, the clock signals in each clock cell area are not affected by the clock signals in the other clock cell areas, so that the amount of jitter generated due to power supply noise is reduced.

The invention of claim 6
The semiconductor integrated circuit according to claim 1, comprising:
A plurality of the data cell regions are provided on the substrate,
When the data circuit power supply wiring in each data cell region is connected to the data circuit power supply wiring in another data cell region, the data circuit power supply wiring is configured to be connected via the voltage drop unit. It is characterized by.

  As a result, even when the power supply wiring is connected between the data areas, the power supply noise can be reduced and the amount of jitter in the clock signal can be reduced.

The invention of claim 7
The semiconductor integrated circuit according to claim 1, comprising:
Furthermore, a capacitance element having a capacitance is provided between the power supply wiring having a potential different from that of the clock circuit power supply wiring and the clock circuit power supply wiring.

The invention of claim 8
The semiconductor integrated circuit according to claim 1, comprising:
Furthermore, a capacitance element having a capacitance is provided between a power supply wiring having a potential different from that of the data circuit power supply wiring and the data circuit power supply wiring.

  As a result, the power supply noise transmitted to the clock cell region is further reduced by the capacitance of the capacitive element, so that the amount of change in the power supply potential in the clock circuit is further reduced and the amount of jitter in the clock signal is further reduced. Is possible.

The invention of claim 9
The semiconductor integrated circuit according to claim 1, comprising:
A plurality of the data cell regions are provided on the substrate,
The clock cell region is provided between the data cell region and the data cell region,
The data signal wiring for transmitting a signal from the data circuit in each data cell region to the data circuit in the other data cell region is orthogonal to the clock signal wiring through which the clock circuit transmits a clock signal on the clock cell region. It is comprised so that it may do.

  As a result, it is possible to prevent the clock signal wiring from being affected by the crosstalk noise generated when the signal changes in the data signal wiring, and to reduce the amount of jitter of the clock signal generated due to the crosstalk noise. Is possible.

  According to the present invention, it is possible to suppress the deterioration of the clock jitter and to suppress the malfunction of the semiconductor integrated circuit caused by the deterioration of the clock jitter.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

Embodiment 1 of the Invention
FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit 100 according to Embodiment 1 of the present invention. As shown in the figure, the substrate of the semiconductor integrated circuit 100 includes a data cell region 110 and a clock cell region 120 as regions constituting the circuit.

  The data cell region 110 includes a data circuit 111 and a data circuit power supply wiring 112.

  The data circuit 111 is configured by a buffer, a logic gate, a flip-flop, or the like, and performs signal processing on an input signal.

  The data circuit power supply wiring 112 supplies a power supply voltage to the data circuit 111.

  The clock cell region 120 includes a clock circuit 121 and a clock circuit power supply wiring 122.

  The clock circuit 121 is configured by a buffer, a logic gate, a flip-flop, or the like, and supplies an input clock signal to the data cell region 110.

  The clock circuit power supply wiring 122 supplies a power supply voltage to the clock circuit 121.

  The semiconductor integrated circuit 100 also includes a clock input terminal 130, a power supply terminal 140, an upper layer power supply wiring 150, a ring power supply 160, and a via 170.

  A clock signal is input to the clock input terminal 130 from the outside of the semiconductor integrated circuit 100.

  The power supply terminal 140 is connected to the ring power supply 160, and a power supply voltage necessary for operating the semiconductor integrated circuit 100 is supplied from the outside of the semiconductor integrated circuit 100.

  The upper layer power supply wiring 150 is a power supply wiring constituted by at least one wiring layer higher than the data circuit power supply wiring 112 and the clock circuit power supply wiring 122.

  The ring power supply 160 is a power supply wiring configured in at least one higher wiring layer than the data circuit power supply wiring 112 and the clock circuit power supply wiring 122, and is connected to the upper power supply wiring 150.

  The via 170 connects the upper layer power supply wiring 150 and the data circuit power supply wiring 112, and further connects the upper layer power supply wiring 150 and the clock circuit power supply wiring 122.

  FIG. 2 is a cross-section (cross-section AA in FIG. 1) of the power supply wiring and via of the semiconductor integrated circuit 100 configured as described above. With this configuration, the clock circuit power supply wiring 122 and the data circuit power supply wiring 112 are connected by the upper layer power supply wiring 150 through the via 170.

  Next, the operation of the semiconductor integrated circuit 100 configured as described above will be described.

  The clock signal input from the clock input terminal 130 is input to the data circuit 111 in the data cell region 110 via the clock circuit 121 in the clock cell region 120.

  At this time, since the data circuit 111 operates in synchronization with the clock signal and consumes power, the power supply potential of the data circuit power supply wiring 112 changes, and power noise occurs in the data circuit 111. The power supply noise generated in one data circuit 111 tends to propagate to the clock circuit 121 and the other data circuit 111 via the data circuit power supply wiring 112.

  However, the via 170 and the upper layer power supply wiring 150 are included between the data cell region 110 and the clock cell region 120, and the power supply noise of the clock circuit 121 propagates without passing through the via 170 and the upper layer power supply wiring 150. Not.

  The via 170 existing in the semiconductor integrated circuit 100 is narrower than the clock circuit power supply wiring 122, the data circuit power supply wiring 112, the upper layer power supply wiring 150, or the like, or a different material is used. Generally, it is known that the resistance value increases. Therefore, the power supply noise generated in the data circuit 111 is reduced by the resistance value of the via 170 and transmitted to the clock circuit 121.

  Therefore, the amount of change in the power supply potential of the clock circuit 121 is smaller than the amount of change in the power supply potential of the data cell region 110, and fluctuations in the delay time of the clock circuit 121 can be suppressed. Therefore, the semiconductor integrated circuit 100 can reduce the amount of jitter in the clock signal.

  As described above, according to the present embodiment, the data circuit power supply wiring 112 and the clock circuit power supply wiring 122 are provided in different regions, and these are connected by vias having higher resistance values than the power supply wirings. The power supply noise generated in the data circuit 111 is reduced and the clock circuit 121 is not directly affected. Therefore, the amount of fluctuation in the power supply potential of the clock circuit 121 can be suppressed, the variation in delay time of the clock circuit 121 can be suppressed, and the amount of jitter in the clock signal can be reduced.

  In addition, when the amount of jitter in the clock signal is suppressed, the timing margin in the data circuit 111 becomes wider, and the probability of occurrence of data mislatch in the data circuit 111 due to clock jitter is reduced. The malfunction probability is reduced.

  In the present embodiment, the configuration in which the wiring layer of the upper layer power supply wiring 150 is different from both the clock circuit power supply wiring 122 in the clock cell region 120 and the data circuit power supply wiring 112 in the data cell region 110 has been described. The power supply wiring may be configured in a wiring layer different from at least one of the cell region 120 and the data cell region 110, and the clock cell region 120 and the data cell region 110 may be connected via the via 170. Similar effects can be obtained.

  Further, even if the clock cell region 120 and the data cell region 110 are connected not by the upper layer power supply wiring 150 and the via 170 but by a physical structure or circuit having an effect of reducing power supply noise similar to the via 170, the same effect can be obtained. can get. For example, the same effect can be obtained even if the wiring length of the upper power supply wiring 150 is extremely long and has an impedance. The same effect can be obtained when an impedance element is used instead of the upper power supply wiring 150 and the via 170.

<< Embodiment 2 of the Invention >>
FIG. 3 is a block diagram showing a configuration of the semiconductor integrated circuit 200 according to the second embodiment of the present invention. In the following embodiments, components having the same functions as those of the first embodiment are denoted by the same reference numerals and description thereof is omitted.

  The semiconductor integrated circuit 200 is different from the semiconductor integrated circuit 100 of the first embodiment in that the data circuit power supply wiring 112 and the clock circuit power supply wiring 122 are connected by the coil 270 instead of being connected by the via 170. Is different.

  The coil 270 is one of impedance elements, and has a characteristic that the resistance component is 0 and the reactance component has a finite value. In general, it is well known that the resistance component of the impedance element causes a voltage drop with respect to the direct current component of the current, whereas the reactance component causes a voltage drop with respect to the alternating current component of the current.

  The power supply noise generated in the data circuit 111 is generated in synchronization with the clock signal input from the clock input terminal 130. For this reason, the power supply potential of the data circuit power supply wiring 112 rapidly changes in a short time, and as a result, the power supply noise generated in the data circuit 111 has a high frequency component.

  In the present embodiment, since the coil 270 has a reactance component, power supply noise generated in the data circuit 111 is reduced by the coil 270 and transmitted to the clock cell region 120.

  Therefore, the change amount of the power supply potential in the clock circuit 121 existing in the clock cell region 120 is smaller than the change amount of the power supply potential in the data cell region 110, and the same effect as the semiconductor integrated circuit of the first embodiment can be obtained.

  In addition, the power supplied to the clock circuit 121 and the data circuit 111 has a feature that the power supply potential hardly changes in a short time and has a large direct current component. Therefore, the power supply voltage supplied from the power supply terminal 140 is supplied to the clock circuit 121 and the data circuit 111 without causing a voltage drop by the coil 270.

  On the other hand, in the semiconductor integrated circuit according to the first embodiment, since the upper layer power supply wiring 150 and the via 170 have a resistance component, the power supply voltage supplied from the power supply terminal 140 causes a voltage drop by the upper layer power supply wiring 150 and the via 170. And supplied to the clock circuit 121 and the data circuit 111.

  As described above, in the semiconductor integrated circuit according to the second embodiment, the coil 270 does not cause a voltage drop with respect to the direct current component, so that the power supply necessary for the operation of the clock circuit 121 and the data circuit 111 is caused to cause a voltage drop. There is an effect that it becomes possible to supply without.

  In this embodiment, the configuration in which the clock cell region 120 and the data cell region 110 are connected by the coil 270 has been described. However, the coil 270 having a resistance component of 0 and a reactance component having a finite value As long as they are connected by a physical structure or circuit having similar characteristics, they are not limited to coils.

<< Embodiment 3 of the Invention >>
FIG. 4 is a block diagram showing a configuration of a semiconductor integrated circuit 300 according to Embodiment 3 of the present invention. The semiconductor integrated circuit 300 has a data cell region 110, a first clock cell region 310, and a second clock cell region 320.

  The difference from the semiconductor integrated circuit of the first embodiment is that two clock signals are input to the semiconductor integrated circuit 300 via the first clock input terminal 330 and the second clock input terminal 340, and the first clock input terminal. The clock signal input from 330 is propagated by the clock circuit 121 included in the first clock cell region 310, input to the data circuit 111 in the data cell region 110, and input from the second clock input terminal 340. The clock signal is propagated by the clock circuit 121 included in the second clock cell region 320 and input to the data circuit 111 in the data cell region 110.

  Further, the first clock cell region 310 and the second clock cell region 320 are connected by the upper layer power supply wiring 150 and the via 170. For this reason, power supply noise generated in the clock circuit 121 in the first clock cell region 310 does not directly propagate to the second clock cell region 320. On the contrary, power supply noise generated in the clock circuit 121 included in the second clock cell region 320 does not directly propagate to the first clock cell region 310.

  As described above, the clock signal input from the first clock input terminal 330 is transmitted to the data circuit 111 in the data cell region 110 without being influenced by the clock signal input from the second clock input terminal 340. Therefore, the amount of jitter generated from the power supply noise in the clock signal input from the first clock input terminal 330 is reduced.

  Further, the clock signal input from the second clock input terminal 340 is transmitted to the data circuit 111 in the data cell region 110 without being affected by the clock signal input from the first clock input terminal 330. Therefore, the clock signal input from the second clock input terminal 340 has a small amount of jitter generated due to power supply noise.

  As described above, in the present embodiment, in addition to the same effects as in the first embodiment, the clock signal input from the first clock input terminal 330 and the clock signal input from the second clock input terminal 340 are: Since the signal propagates without being affected by the power supply noise generated in the mutual clock circuits 121, a clock signal with a small amount of jitter can be output to the data circuit 111.

  In the present embodiment, a configuration having two types of clock signals and two clock cell regions has been described. However, in a configuration having three or more types of clock signals, the same number of clock cell regions as the clock signals are provided, Each clock cell region may be configured to include only one type of clock circuit 121 in order to propagate the clock signal. As a result, it is possible to reduce the amount of jitter generated due to the influence of the fluctuation of the power supply potential caused by another clock signal.

<< Embodiment 4 of the Invention >>
FIG. 5 is a block diagram showing a configuration of a semiconductor integrated circuit 400 according to Embodiment 4 of the present invention. The semiconductor integrated circuit 400 is configured by further adding a capacitive element 470 to the semiconductor integrated circuit 100.

  The capacitor element 470 is connected between a power supply wiring having a higher or lower potential than the clock circuit power supply wiring 122 and the clock circuit power supply wiring 122. Specifically, in this embodiment, the clock circuit power supply wiring 122 and the ground power supply are connected.

  For this reason, the power supply noise that is reduced by the resistance value of the via 170 and transmitted to the clock cell region 120 is further reduced by the capacitance of the capacitor 470.

  Therefore, the amount of change in the power supply potential in the clock circuit 121 in the clock cell region 120 is further reduced, and the delay time fluctuation of the clock circuit 121 can be further suppressed. Therefore, in this embodiment, it is possible to further effectively reduce the amount of jitter of the clock signal.

  In this embodiment, the configuration in which the capacitor element 470 is included in the clock cell region 120 has been described. However, in the data cell region 110, the capacitor element 470 is provided between the data circuit power supply wiring 112 and the ground power supply. However, the same effect can be obtained.

<< Embodiment 5 of the Invention >>
FIG. 6 is a block diagram showing a configuration of a semiconductor integrated circuit 500 according to the fifth embodiment of the present invention. The semiconductor integrated circuit 500 has a plurality of data cell regions 110, and the clock cell region 120 is provided between the data cell regions 110 and 110.

  The clock cell region 120 includes a clock circuit 121, a clock signal wiring 580 that transmits a clock signal, and a data signal wiring 590 that transmits a signal output from the data circuit 111. The clock signal wiring 580 and the data signal wiring 590 are arranged so as to be orthogonal to each other.

  In the data cell region 110, a data circuit 111 and a data signal wiring 590 are included. Other configurations are the same as those of the semiconductor integrated circuit 100 of the first embodiment.

  In the semiconductor integrated circuit 500 configured as described above, the clock signal input from the clock input terminal 130 passes through the clock circuit 121 in the clock cell region 120 and the clock signal wiring 580, and the data in the data cell region 110. When input to the data circuit 111, the data circuit 111 operates in synchronization with the input clock signal, and outputs a signal to another data circuit 111 via the data signal wiring 590. At this time, the power supply noise generated in synchronization with the clock signal in the data circuit 111 is reduced by passing through the via 170 and the upper layer power supply wiring 150 and transmitted to the clock circuit 121.

  Therefore, it is possible to reduce the amount of jitter generated by the clock circuit 121 due to power supply noise, and the same effect as the circuit of the first embodiment can be obtained.

  In general, when the clock signal wiring 580 and the data signal wiring 590 are in a parallel relationship and the data signal wiring 590 changes in signal, the crosstalk proportional to the coupling capacitance value between the clock signal wiring 580 and the data signal wiring 590. It is well known that noise is generated and propagates to the clock signal wiring 580. When this noise occurrence time overlaps with the signal change time of the clock signal, the delay time of the clock signal varies. This variation in delay time appears as jitter in the clock signal.

  On the other hand, in this embodiment, the clock signal wiring 580 and the data signal wiring 590 are orthogonal to each other in the clock cell region 120, so that the coupling capacitance value between the clock signal wiring 580 and the data signal wiring 590 is high. Thus, the clock signal wiring 580 can be prevented from being affected by the crosstalk noise generated when the signal of the data signal wiring 590 changes. That is, according to the fifth embodiment, it is possible to reduce the amount of clock signal jitter generated due to the influence of crosstalk noise.

  In each of the semiconductor integrated circuits of the first to fourth embodiments described above, a configuration in which there is one clock cell region 120 and one data cell region 110 has been described. However, a configuration in which a plurality of clock cell regions 120 exist is provided. Alternatively, the same effect can be obtained even in a configuration in which a plurality of data cell regions 110 exist. In this case, in the third embodiment, the example in which the clock circuit power supply wirings 122 are connected via the vias 170 when connecting the clock circuit power supply lines 122 between the clock cell regions 120 is described. May be connected. As a result, it is possible to more effectively reduce power supply noise and reduce the amount of jitter in the clock signal.

  Further, when the data circuit power supply wirings 112 are connected to each other between the data cell regions 110, the power supply noise can be reduced more effectively in the same manner by connecting them through the impedance element.

  The semiconductor integrated circuit according to the present invention has an effect of suppressing the deterioration of clock jitter and suppressing the malfunction of the semiconductor integrated circuit caused by the deterioration of the clock jitter. It is useful as a semiconductor integrated circuit or the like having a data circuit for performing the above and a clock circuit for supplying a clock signal to the data circuit.

1 is a block diagram illustrating a configuration of a semiconductor integrated circuit according to a first embodiment of the present invention. It is sectional drawing of the power supply wiring part of the semiconductor integrated circuit which concerns on Embodiment 1 of this invention. It is a block diagram which shows the structure of the semiconductor integrated circuit which concerns on Embodiment 2 of this invention. It is a block diagram which shows the structure of the semiconductor integrated circuit which concerns on Embodiment 3 of this invention. It is a block diagram which shows the structure of the semiconductor integrated circuit which concerns on Embodiment 4 of this invention. It is a block diagram which shows the structure of the semiconductor integrated circuit which concerns on Embodiment 5 of this invention. It is a block diagram which shows the structure of the conventional semiconductor integrated circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Semiconductor integrated circuit 110 Data cell area 111 Data circuit 112 Data circuit power supply wiring 120 Clock cell area 121 Clock circuit 122 Clock circuit power supply wiring 130 Clock input terminal 140 Power supply terminal 150 Upper layer power supply wiring 160 Ring power supply 170 Via 200 Semiconductor integrated circuit 270 Coil 300 Semiconductor integrated circuit 310 First clock cell region 320 Second clock cell region 330 First clock input terminal 340 Second clock input terminal 400 Semiconductor integrated circuit 470 Capacitance element 500 Semiconductor integrated circuit 580 Clock signal wiring 590 Data signal wiring 600 Semiconductor integrated circuit 610 Clock input terminal 620 Data circuit 630 Clock circuit 640 Power supply terminal 650 Power supply wiring for standard cell

Claims (9)

A semiconductor integrated circuit having a data circuit that performs signal processing on an input signal and a clock circuit for supplying a clock signal to the data circuit,
A data circuit power supply wiring for supplying a power supply voltage to the data circuit;
A clock circuit power supply wiring for supplying a power supply voltage to the clock circuit;
A voltage drop portion provided between the power wiring for the data circuit and the power wiring for the clock circuit, and causing a voltage drop with respect to an alternating current component;
The data circuit and the power wiring for the data circuit are formed in the data cell region of the substrate divided into the data cell region and the clock cell region,
The clock integrated circuit and the clock circuit power supply wiring are formed in the clock cell region. The semiconductor integrated circuit according to claim 1, comprising:
The voltage drop unit is
Another layer power supply wiring provided in a wiring layer different from the wiring layer of at least one of the power wiring for the data circuit and the power wiring for the clock circuit,
A semiconductor integrated circuit comprising a via for connecting at least one of the power wiring for the data circuit and the power wiring for the clock circuit and the power wiring for the other layer. The semiconductor integrated circuit according to claim 1, comprising:
The semiconductor integrated circuit, wherein the voltage drop unit is a coil. The semiconductor integrated circuit according to claim 1, comprising:
A plurality of the clock cell regions are provided on the substrate,
A power supply wiring for a clock circuit in each clock cell region is connected via the voltage drop portion when connected to a power supply wiring for a clock circuit in another clock cell region. circuit. The semiconductor integrated circuit according to claim 4, comprising:
A semiconductor integrated circuit, wherein a clock circuit in each clock cell area is configured to be supplied with only one clock signal different from clock circuits in other clock cell areas. The semiconductor integrated circuit according to claim 1, comprising:
A plurality of the data cell regions are provided on the substrate,
When the data circuit power supply wiring in each data cell region is connected to the data circuit power supply wiring in another data cell region, the data circuit power supply wiring is configured to be connected via the voltage drop unit. A semiconductor integrated circuit. The semiconductor integrated circuit according to claim 1, comprising:
The semiconductor integrated circuit further comprises a capacitance element having a capacitance between a power supply wiring having a potential different from that of the clock circuit power supply wiring and the clock circuit power supply wiring. The semiconductor integrated circuit according to claim 1, comprising:
The semiconductor integrated circuit further comprises a capacitance element having a capacitance between a power supply wiring having a potential different from that of the data circuit power supply wiring and the data circuit power supply wiring. The semiconductor integrated circuit according to claim 1, comprising:
A plurality of the data cell regions are provided on the substrate,
The clock cell region is provided between the data cell region and the data cell region,
The data signal wiring for transmitting a signal from the data circuit in each data cell region to the data circuit in the other data cell region is orthogonal to the clock signal wiring through which the clock circuit transmits a clock signal on the clock cell region. A semiconductor integrated circuit characterized by being configured to do so.

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