JP2000101417A - Inverter circuit and inverter buffer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an inverter circuit with low power consumption and low noise level by realizing a high-speed operation with a small amplitude for a CMOS LSI with high performance operated at a high speed, and to provide the inverter buffer. SOLUTION: This inverter circuit, consisting of a 1st P-channel transistor(TR) and a 1st N-channel TR in series connection through their drains in a CMOS LSI has a 2nd P-channel TR connected to a source of the 1st P-channel TR, a 2nd N-channel TR connected to a source of the 1st N-channel TR and a feedback means that feeds back an output signal of the inverter circuit to gates of the 2nd P-channel TR and the 2nd N-channel TR. The feedback means feeds back directly the output signal of the inverter circuit to the gates of the 2nd P-channel TR and the 2nd N-channel TR or feeds back the output signal of the inverter circuit that is subject to voltage division to the gates of the 2nd P-channel TR and the 2nd N-channel TR.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an inverter circuit composed of a P-channel transistor and an N-channel transistor connected in series via a drain in a CMOS LSI, and more particularly to a self-feedback inverter circuit.

[0002]

2. Description of the Related Art FIG. 3 shows an example of a configuration for adjusting timing skew between macro blocks on an LSI as an example of an inverter buffer in which conventional inverter circuits are connected in series.

According to the figure, a clock from a clock generation circuit is supplied to a macro 1 and a macro 2, and each macro operates in synchronization. On the LSI chip, the wiring distance from the clock generation circuit to the macro 1 and the macro 2 will not be the same depending on the arrangement position of each macro block. The clock supplied to each macro generates a skew because the wiring resistance and the wiring capacitance are different due to the difference in the wiring distance and the path. In order to eliminate the skew of each macro, the timing is matched by inserting a delay circuit having a delay value corresponding to the skew into the clock line. Conventionally, this delay circuit uses an inverter circuit as shown in FIG. 6, and as shown in FIG. 3, an inverter buffer in which inverter circuits are connected in series adjusts a delay value according to the number of connected stages.

[0004] In recent years, as the speed of LSI systems has increased, the effects of the current consumption and noise of these inverter buffers cannot be ignored, and it is required to reduce them. As a countermeasure, the gate width and gate length of the transistor are changed, or the transistors are connected in at least two stages in series as shown in FIG. 7, so that the capability of the inverter circuit is reduced and the current consumption is reduced. . An inverter circuit in which two transistors are connected in series as shown in FIG. 7 operates according to the timing chart of FIG.

[0005]

However, if the LSI system becomes large-scale and the distance between the connection lines between the macros becomes long, the output waveform becomes dull in the method of lowering the capacity of the inverter circuit. It hinders operation. In addition, in an inverter circuit in which transistors are connected in series, the number of elements increases, which is disadvantageous for the layout area of the LSI. For this reason, if the capacity of the inverter circuit is increased, the current consumption will eventually increase, causing a problem of noise. In addition, under the current situation where miniaturization is progressing and the coupling capacitance between adjacent wirings cannot be ignored, there is a problem that signals propagate as noise. Thus, it is difficult to achieve both high-speed operation and low current consumption and low noise.

An object of the present invention is to provide a high-speed, high-performance CMOS.
An object of the present invention is to provide an inverter circuit and an inverter buffer which realize low amplitude, high speed operation, low power consumption and low noise in an LSI.

[0007]

An inverter circuit according to the present invention is an inverter circuit comprising a first P-channel transistor and a first N-channel transistor connected in series via a drain in a CMOS LSI. A second P-channel transistor connected to the source side of the channel transistor, a second N-channel transistor connected to the source side of the first N-channel transistor, and an output signal of the inverter circuit to the second P-channel transistor and the second P-channel transistor. And a feedback means for feeding back to the gates of the two N-channel transistors.

Further, the feedback means directly feeds back the output signal of the inverter circuit to the gates of the second P-channel transistor and the second N-channel transistor, or the second P-channel transistor and the second N-channel transistor. Feedback means for dividing and feeding back the output signal of the inverter circuit to the gate of the transistor.

The feedback means for dividing and feeding back the output signal of the inverter circuit is divided by a connection point of two resistive elements connected in series between the output signal of the inverter circuit and the source. Alternatively, there is provided an intermediate potential generating circuit which divides the output signal of the inverter circuit by a combination of a resistor and a transistor connected in series between the output signal of the inverter circuit and the source and feeds back the divided voltage.

Further, the second P-channel transistor and the second N-channel transistor may have feedback means for changing the ratio between the gate length and the gate width of the transistors and feeding back the output signal of the inverter circuit to the gate. Good.

Still further, the inverter circuit is connected in series to form an inverter buffer.

[0012] Specifically, the inverter circuit of the present invention comprises:
In an inverter circuit of a high-speed and high-performance CMOS LSI, an output signal is fed back to a source-side transistor of an inverter circuit connected in series, thereby suppressing input / output gain, realizing small-amplitude, high-speed operation, low power consumption, and low noise. It is characterized by operating on.

As shown in FIG. 1, in the most basic inverter circuit according to the present invention, an enhancement type transistor is provided on the source side of each of the P-channel transistor and N-channel transistor inverter circuits connected in series. . The output of the inverter is connected to the gate of the transistor added to the source side. The source side transistor of this inverter circuit is
It works to suppress the output level by the feedback of the output signal. Therefore, the output level operates with a small amplitude at the intermediate potential level without having an amplitude from 0 V to VDD.

Therefore, the effect that the noise propagation due to the coupling capacitance between the adjacent wirings can be reduced can be obtained.

[0015]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is the most basic direct feedback inverter circuit diagram according to the present invention, and FIG.
FIG. 3 is an inverter circuit diagram of voltage division feedback by the connection intermediate potential generation circuit of the present invention. FIG. 3 is a circuit diagram for adjusting timing skew between macro blocks on an LSI as an example of an inverter buffer in which inverter circuits are connected in series. FIG. 4 is a timing chart for explaining the operation of the inverter circuit of the present invention, and FIG. 5 is a timing chart for explaining the operation of the circuit for adjusting the timing skew between macro blocks of the present invention.

Referring to FIG. 1, there is shown an inverter circuit according to a first embodiment of the present invention. This inverter circuit has an output feedback transistor. The first P-channel transistor P1 and the first N-channel transistor N1 are connected via a drain, and the drain is connected to the output terminal "OUT". The gates of these first P-channel and first N-channel transistors are connected to the input terminal "IN". Second P-channel transistor P
2 has a source connected to the power supply VDD and a drain connected to the first P
Connect to the source of the channel transistor. The source of the second N-channel transistor N2 is grounded to a ground electrode (hereinafter referred to as ground), and the drain is connected to the source of the first N-channel transistor. The gates of the second P-channel and second N-channel transistors are connected to an output terminal “OUT”
Connected to.

The output signal of the inverter circuit is supplied to the gates of the second P-channel and the second N-channel transistors, and is fed back. When the input signal changes from the low level to the high level, the output signal attempts to transition from the high level to the low level. In response to this change, the second transistor provided according to the present invention is turned off when the output reaches a certain level, so that the output does not transition to the ground level and maintains a certain intermediate level. Similarly, when the output changes from the low level to the high level, the second transistor is turned off at a certain level, so that the output maintains the intermediate level without transitioning to the VDD level.

Thus, when a high-speed clock pulse is input to the inverter circuit, it is output as a small amplitude signal.

Next, the operation of the inverter circuit of this embodiment will be described with reference to the timing chart of FIG. Since the operation of the inverter circuit is performed, a signal inverted with respect to the input is output.

According to the figure, when the input "IN" is at the low level, the first P-channel transistor P1 is in the ON state,
The first N-channel transistor N1 is turned off, the second P-channel transistor P2 is turned off, the second N-channel transistor N2 is turned on, and the output “OU” is output.
T ″ is the threshold voltage V of the P-channel transistor from VDD
The intermediate potential H becomes lower by the potential of t.

When the input "IN" changes from the low level to the high level, the first P-channel transistor P1 is gradually turned off, the first N-channel transistor N1 is gradually turned on, and the output "OUT" is at the intermediate level. The potential changes from the potential H to a low level. At this time, the second P-channel transistor P2 is gradually turned on,
N-channel transistor N2 is gradually turned off. When the output “OUT” becomes equal to or lower than the threshold voltage Vt of the N-channel transistor, the second N-channel transistor N2 is completely turned off, and the output “OUT” holds the intermediate potential L at that time.

When the input "IN" is at a high level, the first P-channel transistor P1 is turned off, the first N-channel transistor N1 is turned on, the second P-channel transistor P2 is turned on, and the second N-channel transistor P2 is turned on. The channel transistor N2 is turned off, and the output “OUT” holds the intermediate potential L.

When the input "IN" changes from the high level to the low level, the first P-channel transistor P1 is gradually turned on, the first N-channel transistor N1 is gradually turned off, and the output "OUT" is intermediate. The potential changes from the potential L to a high level. At this time, the second P-channel transistor P2 is gradually turned off,
N-channel transistor N2 is gradually turned on. When the output “OUT” falls from VDD to the threshold voltage Vt of the P-channel transistor or lower, the second P-channel transistor P2 is completely turned off, and the output “OU”
T ″ holds the intermediate potential H at that time.

As described above, since the output is fed back to the gates of the second P-channel and N-channel transistors, when the output voltage becomes equal to or lower than the threshold voltage Vt of the second P-channel and N-channel transistors, Since the channel and the N-channel transistor are turned off, the output does not completely transition from 0 V to VDD, and the operation is repeated with a small amplitude between the intermediate potential H and the intermediate potential L.

As one embodiment using this inverter circuit, there is a delay circuit for adjusting timing skew between macros on an LSI as shown in FIG. This delay circuit operates according to the timing chart of FIG. That is, since each inverter constituting the delay circuit operates as described above, the outputs A and B having different phases output small amplitude signals at an intermediate potential between 0 V and VDD.

Next, as a second embodiment of the present invention, a feedback circuit for an output signal is further devised. FIG. 2 shows the inverter circuit. In the figure, the gates of the second P-channel and N-channel transistors are connected to an intermediate potential generation circuit composed of a combination of a resistance element and a transistor or a resistance voltage divider composed of two resistance elements. When this intermediate potential generating circuit is formed of a transistor, the resistance can be controlled by a gate bias when the transistor is on, and the second P
Arbitrarily controlled signal levels can be input to the gates of the channel and the N-channel transistor.

Therefore, the operation of the second transistor can be arbitrarily controlled, and the output level can be made variable. That is, variations due to manufacturing and variations due to environmental variations are absorbed, and an optimal operation state can be set.

Next, in the third embodiment of the present invention, the operating point is determined by the gate bias of the second P-channel and N-channel transistors.
The operating point and the level of the output amplitude can be adjusted by changing the ratio of the gate length to the gate width of the P-channel and N-channel transistors.

That is, by setting the ratio between the gate length and the gate width of each transistor to be switchable, the optimum ratio between the gate length and the gate width can be selected, and the output amplitude can be adjusted.

[0030]

Next, specific embodiments of the present invention will be described in detail with reference to the drawings and numerical values.

According to the present invention, the second P-channel transistor or the second N-channel transistor is turned off before the signal level transitions from the low level to the high level or from the high level to the low level.
The current path is cut, and the through current is reduced. FIG. 7 shows an example of a conventional inverter circuit in which transistors are connected in series. The transistor used is the same as that of the present invention, the gate of the second P-channel transistor is grounded, and
The gate of the second N-channel transistor is connected to VDD, and each transistor is on. Taking the delay circuit shown in FIG. 3 as an example, in the delay circuit using this inverter and the delay circuit using the inverter of the present invention, for example, the gate length L of the transistor of the inverter is L =
0.25 μm, gate width WP1 = WP2 = 8 μm, WN
When 1 = WN2 = 4 μm, the average current is 0.346 mA in the conventional circuit shown in FIG. 9 and is 0.246 mA in the present invention, which is about 29.7%, as shown in FIG. The peak current is 0.790 m in the conventional circuit as shown in FIG.
In contrast, A in the present invention is 0.397 mA as shown in FIG.
About 49.8%. As a result, the effect of reducing power consumption is obtained, and further, the effect of reducing noise is obtained because the current fluctuation is small.

As described above, the small-amplitude operation is enabled and the noise is reduced before the output transition ends.
This is because the P-channel or N-channel transistor is turned off, and the output level is reduced.
For example, the gate length of the inverter transistor L = 0.2
5 μm, gate width WP1 = WP2 = 8 μm, WN1 = W
When N2 = 4 μm and VDD = 2.5 V, the output of the conventional circuit operates at full amplitude in the range of 0 V to 2.5 V, whereas the output of the circuit of the present invention is between 0.6 V and 1.9 V. Operates at an amplitude in the range of potentials. When the inverter of the present invention is used in the delay circuit for adjusting the timing skew between macros on the LSI, since the output of the inverter is a small amplitude signal, the output of the adjacent signal wiring is smaller than that of the full amplitude operation of 0v-VDD. Potential fluctuations due to the coupling capacitance become relatively small, and the influence of noise is reduced. For example, it is assumed that there is an adjacent wiring having a capacitance of 0.1 pF with respect to the output of the inverter. In the conventional circuit, when the output changes periodically like a clock pulse, the adjacent signal is ±
While 0.2 V of noise is generated, the noise of the circuit of the present invention is as small as ± 0.1 V. If the output amplitude is further reduced, the influence of noise can be eliminated. Thus, the effect of reducing noise by the small amplitude operation can be obtained.

Since the present inverter circuit can be realized without lowering the capacity of the transistor, the speed is not inferior to an inverter in which transistors of the same size and number are connected in series. For example, the gate length L of the transistor of the inverter = 0.25 μm, the gate width WP1 = WP2 =
When 8 μm, WN1 = WN2 = 4 μm, and VDD = 2.5 V, taking the delay circuit shown in FIG. 3 as an example, the delay time from input A to output B when inverters are connected in two stages in series is While the circuit is 0.14 ns as shown in FIG. 9, the circuit of the present invention is 0.14 ns as shown in FIG.

Conventionally, the clock wiring and the wiring adjacent thereto are sufficiently separated to reduce the adjacent capacitance. However, this distance can be shortened to reduce the influence of noise due to the small amplitude operation. Area can be reduced. In particular, in places where signal wirings are densely arranged, wiring restrictions on signals adjacent to the clock signal are relaxed, which is very effective. For example, width 0.5 μm, length 1
It is assumed that there is a signal wiring of 00 μm. In the conventional circuit, signals adjacent to this are wired with an interval of 2 μm in order to reduce the influence of noise due to the coupling capacitance, so that a total of three wiring areas, one on each side, are ((0.5 μm × 3) + (2 μm
× 2)) × 100 μm = 550 μm ² . On the other hand, in the circuit according to the present invention, when the same level of noise as that of the related art is realized by the effect of reducing the influence of noise due to the capacitive coupling, the wiring interval can be reduced to 1 μm, and the wiring area becomes ((0 0.5 μm × 3) + (1 μm ×
2)) × 100 μm = 350 μm ² provides an effect of reducing the area by about 36%. Further, since the present invention can easily configure a circuit and does not increase the number of circuit elements, it is possible to realize a small layout area.

[0035]

As described above, the inverter circuit and the inverter buffer according to the present invention have the following effects.
The first effect is that the through current is reduced and low power consumption operation is possible. The second effect is that a small amplitude operation becomes possible and noise is reduced. A third effect is that high-speed operation is possible. The fourth effect is that the area can be reduced.

[Brief description of the drawings]

FIG. 1 is a most basic direct feedback inverter circuit diagram according to the present invention.

FIG. 2 is an inverter circuit diagram of voltage division feedback by a connection intermediate potential generation circuit of the present invention.

FIG. 3 is a circuit diagram for adjusting timing skew between macro blocks on an LSI as an example of an inverter buffer in which inverter circuits are connected in series;

FIG. 4 is a timing chart illustrating the operation of the inverter circuit of the present invention.

FIG. 5 is a timing chart for explaining the operation of a circuit for adjusting timing skew between macro blocks according to the present invention;

FIG. 6 is a conventional most basic inverter circuit diagram.

FIG. 7 is a circuit diagram of an inverter buffer in which conventional inverter circuits are connected in series.

FIG. 8 is a timing chart for explaining the operation of the most basic conventional inverter circuit.

FIG. 9 is a timing chart for explaining the operation of a conventional circuit for adjusting the timing skew between macro blocks.

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[Procedure amendment]

[Submission date] August 30, 1999 (1999.8.3)
0)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0007

[Correction method] Change

[Correction contents]

[0007]

An inverter circuit according to the present invention comprises a first N-channel transistor connected in series via a drain.
Composed of a transistor and a first P-channel transistor
P channel of CMOS LSI inverter circuit to be used
Second P channel connected to the source side of the
Source transistor and the source of the first N-channel transistor.
A second N-channel transistor connected to the source side;
The output signal of the inverter circuit to a second P-channel transistor
And the gate of the second N-channel transistor
An inverter circuit having feedback means;
Is connected in series between the output signal of the inverter circuit and the source.
The connection point of the two resistive elements
It has a resistive voltage divider that divides the force signal and returns it.
Sign.

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0008

[Correction method] Change

[Correction contents]

The feedback means for performing the partial pressure feedback is an invar.
Element connected in series between the output signal of the data circuit and the source
Output of the inverter circuit by the combination of
It has an intermediate potential generating circuit that divides the force signal and feeds back.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0009

[Correction method] Change

[Correction contents]

Further, the second P-channel transistor and the second P-channel transistor
Ratio of gate length and gate width of N-channel transistor 2
It is characterized by changing each rate.

[Procedure amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0010

[Correction method] Change

[Correction contents]

Further, an inverter circuit is connected in series to
An inverter buffer is formed.

[Procedure amendment 6]

[Document name to be amended] Statement

[Correction target item name] 0011

[Correction method] Deleted

[Procedure amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0013

[Correction method] Change

[Correction contents]

As shown in FIG. 1, the most basic feature of the present invention is shown.
In the inverter circuit, an enhancement-type transistor is provided on the source side of each transistor with respect to the inverter circuit of a P-channel transistor and an N-channel transistor connected in series. The output of the inverter is connected to the gate of the transistor added to the source side. The source-side transistor of this inverter circuit works to suppress the output level by feedback of the output signal.
Therefore, the output level operates with a small amplitude at the intermediate potential level without having an amplitude from 0 V to VDD.

[Procedure amendment 8]

[Document name to be amended] Statement

[Correction target item name] 0015

[Correction method] Change

[Correction contents]

[0015]

Embodiments of the present invention will now be described in detail with reference to the drawings. Figure 1 of the present invention
The most basic direct feedback inverter circuit diagram, FIG. 2 is a voltage division feedback inverter circuit diagram of the connection intermediate potential generating circuit of the present invention, and FIG. 3 is an example of an inverter buffer in which inverter circuits are connected in series. FIG. 4 is a circuit diagram for adjusting the timing skew between the macroblocks, FIG. 4 is a timing chart for explaining the operation of the inverter circuit of the present invention, and FIG. 5 is an operation of the circuit for adjusting the timing skew between the macroblocks of the present invention. FIG. 6 is a timing chart for explaining.

[Procedure amendment 9]

[Document name to be amended] Statement

[Correction target item name] 0016

[Correction method] Change

[Correction contents]

[0016] Referring to FIG. 1 Then, the inverter circuit,
It has an output feedback transistor. The first P-channel transistor P1 and the first N-channel transistor N1 are connected via a drain, and the drain is connected to the output terminal “OU”.
T ". The first P channel and the first P channel
The gate of the N-channel transistor is an input terminal "IN".
Connect to The source of the second P-channel transistor P2 is connected to the power supply VDD, and the drain is connected to the source of the first P-channel transistor. The source of the second N-channel transistor N2 is a ground electrode (hereinafter referred to as ground).
And the drain is connected to the source of the first N-channel transistor. The gates of the second P-channel and second N-channel transistors are connected to the output terminal “OUT”.

[Procedure amendment 10]

[Document name to be amended] Statement

[Correction target item name] 0026

[Correction method] Change

[Correction contents]

Next, as a first embodiment of the present invention, a feedback circuit for an output signal is further devised. FIG. 2 shows the inverter circuit. In the figure, the gates of the second P-channel and N-channel transistors are connected to an intermediate potential generation circuit composed of a combination of a resistance element and a transistor or a resistance voltage divider composed of two resistance elements. When this intermediate potential generating circuit is formed of a transistor, the resistance can be controlled by a gate bias when the transistor is on, and the second P
Arbitrarily controlled signal levels can be input to the gates of the channel and the N-channel transistor.

[Procedure amendment 11]

[Document name to be amended] Statement

[Correction target item name] 0028

[Correction method] Change

[Correction contents]

Next, in the second embodiment of the present invention, the operating point is determined by the gate bias of the second P-channel and N-channel transistors.
The operating point and the level of the output amplitude can be adjusted by changing the ratio of the gate length to the gate width of the P-channel and N-channel transistors. That is, by setting the ratio between the gate length and the gate width of each transistor to be switchable, the optimum ratio between the gate length and the gate width can be selected, and the output amplitude can be adjusted.

[Procedure amendment 12]

[Document name to be amended] Statement

[Correction target item name] Fig. 1

[Correction method] Change

[Correction contents]

FIG. 1 is a direct feedback inverter circuit diagram which is the most basic of the present invention .

Claims (7)

[Claims] 1. An inverter circuit comprising a first P-channel transistor and a first N-channel transistor connected in series via a drain in a CMOS LSI, wherein a second P-channel transistor connected to a source side of the first P-channel transistor is provided. A P-channel transistor, a second N-channel transistor connected to the source of the first N-channel transistor, and an output signal of the inverter circuit connected to the gates of the second P-channel transistor and the second N-channel transistor. An inverter circuit having feedback means for feeding back. 2. The inverter circuit according to claim 1, wherein said feedback means is a feedback means for directly feeding back the output signal of said inverter circuit to the gates of said second P-channel transistor and said second N-channel transistor. 3. The inverter circuit according to claim 1, wherein said feedback means is a feedback means for dividing and feeding back the output signal of said inverter circuit to the gates of said second P-channel transistor and said second N-channel transistor. 4. A resistor for dividing the output signal of the inverter circuit by a connection point of two resistor elements connected in series between the output signal of the inverter circuit and the source, and providing feedback. The inverter circuit according to claim 3, further comprising a voltage divider. 5. A feedback means for dividing and feeding back an intermediate potential for dividing and outputting the output signal of the inverter circuit by a combination of a resistor and a transistor connected in series between the output signal of the inverter circuit and the source. The inverter circuit according to claim 3, further comprising a circuit. 6. The second P-channel transistor and the second N-channel transistor have feedback means for changing the ratio of the gate length to the gate width of the transistors and feeding back the output signal of the inverter circuit to the gate. Item 6. The inverter circuit according to any one of Items 1 to 5. 7. The inverter circuit according to claim 1, wherein the inverter circuits are connected in series to form an inverter buffer.