JP2006314117A - Automatic deskew system and automatic compensation method of skew - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a simpler and more robust deskew system capable of operating over a wider range input values with greater accuracy and over a broader range of temperature regarding a system for performing automatic deskew tuning and alignment across high-speed, parallel interconnection in a high performance digital system to compensate for inter-bit skew. <P>SOLUTION: Rather than using a VDL, digital elements such as registers and multiplexers are used for performing the automatic deskew tuning and alignment procedure. In addition, the present invention performs 1-4 unfolding of signals on each interconnection. The system includes a deskew control mechanism (135) and a plurality of skew subsystems (192, 190). The deskew control mechanism computes the amount of delay needed to correct the skew on each interconnection and feeds a different (or appropriate) delay value to each deskew subsystem located at the receiving end of each interconnection. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

The present invention relates to an automatic deskew system and method for use in high speed parallel interconnects for digital systems, including high performance microprocessor systems, memory systems and input / output (“I / O”) systems.
Cross-reference of related applications The subject of this application is "Automatic initialization and tuning via high-speed plesiochronous parallel link" and is a co-pending application filed by Richard L. Schober Jr. et al. In connection with the contents of US patent application Ser. No. 09 / 249,825, all of the above applications are incorporated throughout the present invention for reference.

  As data communication speeds increase in high performance digital systems, and as the length of signal lines, such as copper or optical cables or printed circuit board traces, connecting the components of such high performance digital systems increases, Therefore, the skew of the time when data arrives at the receiving end of each signal line becomes significant. Skew on each signal line is the result of differences in the characteristics and length of each cable, connector or printed circuit board trace. In addition, the skew becomes worse as the data transmission rate increases.

Conventional deskew circuits exist to solve the problem of bit-to-bit skew on high speed parallel interconnects. However, conventional deskew circuits typically use analog devices called variable delay lines (“VDL”). VDL adds a certain amount of delay to a 1-bit data input with skew and aligns such 1-bit data input with other data input bits on parallel signal lines.
The following are known examples related to the present invention.

EP 0 847 732 A1

  There are a number of problems with conventional VDL. First, it is difficult and expensive to create a VDL that can operate with high accuracy over a wide input range. In general, the larger the operating range and the higher the accuracy of VDL, the greater the required number of delay elements that are buffers. These buffers occupy a constant space, increase the overall chip size and pin connections, and are therefore expensive.

  Second, it is difficult to build a linearly operating VDL. Linearity in VDL is a desirable characteristic. For example, if the input value of VDL is 1 and the delay is 2 microseconds, and if the input value is 2 and the delay is 4 microseconds, then the VDL generates a delay of 6 microseconds when the input value is 3. Should do. Alternatively, if the VDL generates a 10 microsecond delay for an input value of 3, then an incorrect amount of delay is added to the skewed input data line, resulting in a parallel input data line. A misalignment between will result.

  Third, VDL is not temperature stable. For example, a VDL operating under low temperature conditions may output a 2 microsecond delay for certain inputs and a 3 microsecond delay for the same input when operating under high temperature conditions. Therefore, when a conventional deskew circuit including VDL is installed in an environment where the temperature fluctuates, the performance of the VDL becomes low in reliability. This results in an incorrect amount of delay added to the skewed 1-bit input, resulting in signal misalignment on the parallel lines.

  In addition to adding a delay to correct for skew on parallel data input lines, conventional deskew circuits can also perform an operation of “unfolding”. Specifically, in the case of 1 to 4 expansion circuits, four consecutive bits of the data signal are converted into a 4-bit wide output signal of 1 bit per output, and each output bit is a quarter of the input speed. Has a speed of 1. The purpose of lowering and deploying input speed is to make it easier to design core logic circuits in digital systems. In general, the core logic circuit in such a system is extremely complicated, and thus the design is facilitated by reducing the operating frequency. A conventional deskew circuit generally performs an operation of adding and developing a sequential delay.

  As a result, it is used in high-speed parallel interconnects for digital systems that (i) operate over a wide input range with high accuracy, (ii) be suitable for temperature fluctuation environments, and (iii) perform deployment. There is a need for an automatic deskewing system.

  The present invention includes systems and methods for performing automatic deskew tuning and alignment via high speed parallel interconnects in high performance digital systems to compensate for bit-to-bit skew. Rather than using VDL, the present invention rather uses digital elements such as registers and multiplexers, so that it has the ability to operate over a wider input value range with greater accuracy and over a wider temperature range. A simpler and more robust deskewing system is obtained. In addition, the present invention performs 1-4 deployments of signals on each interconnect.

  A system according to the present invention may include a deskew control mechanism and a plurality of deskew subsystems. The deskew control mechanism calculates the amount of delay required to correct the skew on each interconnect and is different (or appropriate) for each deskew subsystem at the receiving end of each interconnect. Supply a delay value.

Each deskew subsystem includes a clock recovery subsystem, a retiming subsystem, and two coarse deskew subsystems. The clock recovery subsystem compensates for skew that is less than the time period ("1 bit time" or "T") for the transmission of 1 bit of information on one interconnect.
The retiming subsystem and coarse skew removal subsystem collectively correct any residual skew by adding a delay within an integer multiple of 1 bit time T from 0T to 7T. The retiming subsystem and the coarse skew removal subsystem collectively perform 1 to 4 expansions of the input signal.

The final output of the automatic deskew system is the 1-4 deployment of each data input signal line and the alignment of all data on parallel interconnects in the digital system.
The features and advantages described herein are not all inclusive, and many additional features and advantages will become apparent to those skilled in the art, especially in light of the drawings, specification, and claims. Moreover, the terminology used herein is selected primarily for the purposes of legibility and explanation, and is not selected for describing or limiting inventive content.

  As will be apparent from the following description, according to the present invention, a digital system that (i) operates over a wide input range with high accuracy, (ii) is suitable for a temperature fluctuation environment, and (iii) performs expansion. An automatic deskew system is provided for use in high speed parallel interconnects.

  Preferred embodiments of the invention are described with reference to the figures, wherein like reference numerals represent identical or functionally similar elements. In the figures (FIGS. 1 to 10), the number at the leftmost digit of each reference number corresponds to the number of the figure in which the number is first used (however, in FIG. 11 and subsequent figures, the number is reduced by one). ). The present invention relates to a system and method for automatic deskewing for use in high speed parallel interconnects for digital systems.

FIG. 1 is a block diagram of an automatic deskew system 100 for use in a high speed parallel interconnect for a digital system according to one embodiment of the present invention. As the digital system, for example, a high-performance microprocessor, a memory system, or a router chip can be considered.
The automatic deskew system 100 includes a plurality of deskew subsystems 192 and 180 and a deskew control mechanism 135. One deskew subsystem is present at the receiving end of each parallel interconnect. According to the present invention, an automatic deskew system has at least two deskew subsystems, but precisely the number of such deskew subsystems depends on the number of parallel interconnects in the digital system.

  The deskew subsystem has a single bit input 145a for receiving a skewed signal and four bit outputs 160a-160d and is coupled to a deskew control mechanism 135. The signal on input 145a carries 1 bit of information every 1 bit time T. “One bit time” or “T” is defined as 1 / N seconds, where N is the number of information bits transmitted on the interconnect per second. The signals on the 4-bit output terminals 160a to 160d are developed after skew correction. In other words, each output is properly aligned with the other output signal, and the speed of each output is reduced by a factor of four in relation to input 145a.

  FIG. 2 illustrates a timing diagram of input and output values for the entire deskew subsystem and automatic deskew system. A timing diagram for data arriving on input line 145a is shown in column 200, and a timing diagram for data arriving on input line 145b is shown in column 210. As shown in FIG. 2, the data 210 reaching the input line 145b is delayed by approximately 5T in relation to the data 200 reaching the input line 145a. The difference in arrival time represents the skew between the input lines 145a and 145b. Automatic deskew system 100 corrects the skew so that 205a-205d is aligned with 215a-215d and develops signals 200 and 210 on input lines 145a and 145b, respectively, thus the output signal speed is 1/4. Will be slowed down.

  As illustrated in FIG. 1, the deskew subsystem 192 includes a clock recovery subsystem 105 and a retiming / skew removal subsystem 110. Similarly, the deskew subsystem 180 includes a clock recovery subsystem 190 and a retiming / skew removal subsystem 191. The clock recovery subsystem corrects skew that is less than 1 bit time, eg, 0.5T. The clock circuit subsystem is further described in US patent application Ser. No. 09 / 093,056, assigned to the same assignee as the present patent application and incorporated herein by reference.

  FIG. 3 illustrates a block diagram of one embodiment of a retiming / skew removal subsystem according to the present invention. The retiming / skew removal subsystem 110 includes a retiming subsystem 305 and two coarse deskew subsystems 310 and 315. The retiming / skew removal subsystem 110 is coupled to the clock recovery subsystem 105 and the deskew control mechanism 135. Based on the delay control values 320, 325, and 330 calculated by the deskew control mechanism 135, the retiming / skew sub-system may have any clock circuit subsystem 105 and accompanying deskew sub-system 110 installed on any input line 145a. Provide integer multiples of input signal 345a and 345b up to 7-bit time delay, ie, 1T time delay up to 0T, 1T, 2T, 3T, 4T, 5T, 6T or 7T, to collectively correct skew To do. The deskew subsystem 192 (FIG. 1) also performs 1-4 deployments of such signals at its outputs 160a-160d.

The timing diagrams shown at 205a-205d and 215a-215d illustrate the output of the automatic deskew system, which corrects the skew on lines 145a and 145b, respectively.
As illustrated in FIG. 3, the retiming subsystem 305 comprises two inputs 345a and 345b, a delay addition input 320 for receiving a delay control value, and two outputs 350a and 350b. . The coarse deskew subsystem 310 has one input 350a, two delay control inputs 325 and 330 for receiving delay control values (bits), and two outputs 355a and 355b. Each output of retiming subsystem 305 is coupled to an input of a coarse deskew subsystem. The retiming subsystem 305 delays the signals on the input terminals 345a and 345b by 0T or 1T according to the value of the delay addition input terminal 320, and performs 1-2 expansion of the signals on the input terminals 345a and 345b.

  FIG. 4 illustrates one embodiment of the retiming subsystem 305. As shown in FIG. 4, the retiming subsystem 305 includes registers 410, 415, 425 and 430 and a multiplexer 420. The registers are coupled in such a way that the outputs of such registers perform a 1-2 expansion of the two inputs 345a and 345b with a delay of 0T or 1T.

  FIG. 6 illustrates a timing diagram for the retiming subsystem 305. The input signal 600 carries 1 bit of information every 1 bit time T, where the input signal 600 is received via line 145a (FIG. 1). Timing diagrams for the unfolded outputs of registers 410, 415 and 430 are shown at 635, 645 and 650, respectively. The signal shown at 645 is delayed by 2 bit times 2T in relation to the signal shown at 635.

  The multiplexer 420 shown in FIG. 4 has three inputs 455, 465 and 470, an input 320 for receiving 1-bit delay addition control, and two outputs 350a and 350b. Multiplexer 420 is coupled to the outputs of registers 410, 415 and 430. As shown in FIGS. 4 and 5, based on the value of the delay addition control value 320 received from and calculated by the deskew control mechanism 135 (FIG. 1), the multiplexer 420 can receive from the registers 410, 415 and 430. Select two consecutive bits of the delayed and expanded output. The only difference between the two possible outputs of multiplexer 420 is 0T or 1T delay. In short, the retiming subsystem 305 has the ability to delay the signal by 0T or 1T and perform 1-2 expansion of the input signal.

  FIG. 7 illustrates one embodiment of the coarse deskew subsystem 310. The coarse deskew subsystem 310 includes registers 705, 710, 715, 720, 725 and 730 and a multiplexer 735. The register outputs one or two of the input 350a with a delay of 0T, 2T, 4T or 6T, depending on the delay control values 325 and 330 from the deskew control mechanism 135. Combined in shape.

  FIG. 9 illustrates a timing diagram for the coarse deskew subsystem 310. The input signal 900 sends out one information bit every two bit times 2T, where the input signal 900 is received via line 350a. Timing diagrams for the expanded outputs of registers 705, 715, 720, 725 and 730 are shown at 915, 925, 930, 935 and 940, respectively. The signal shown at 935 is delayed by 8 bit times 8T in relation to signal 915 and 4 bit times 4T in relation to signal 925. Signal 940 is delayed by 4 bit times 4T relative to signal 930.

  The multiplexer 735 shown in FIG. 7 has five inputs 770, 780, 790, 785 and 795, inputs for receiving the 2-bit delay control values 325 and 330, and two outputs 355a and 355b. Have. Multiplexer 735 is coupled to the outputs of registers 705, 715, 720, 725 and 730. As shown in FIGS. 7 and 8, based on the delay control bit values 325 and 330 calculated by the deskew control mechanism 135, the multiplexer 735 selects two consecutive bits of the expanded output. . The only difference between the four possible outputs of multiplexer 735 is a delay of 0T, 2T, 4T or 6T.

  Briefly, the retiming / skew removal subsystem 110 (including two coarse deskew subsystems 310 and 315 coupled to the output of the retiming subsystem 305) receives the input signal 0T, 1T, 2T. , 3T, 4T, 5T, 6T or 7T, each of the four output bits 355a-355b being aligned and having a transmission rate that is one-fourth the rate of the input signal 145a, one of the input signals 345a and 345b. Has the ability to implement ~ 4 deployments.

  Each retiming / skew subsystem 110 and 191 is coupled to a deskew control mechanism 135. The deskew control mechanism 135 calculates a 3-bit delay value for each interconnect. As shown in Chart 1 below, the least significant bit (LSB) from the deskew control mechanism is provided in the retiming subsystem 305 as a retiming delay addition bit 320, while the most significant 2 bits (MSB1 and MSB2). ) Is provided in the coarse deskew subsystems 310 and 315 as coarse skew removal delay addition bits 325 and 330. The amount of added delay based on the values of bits MSB1, MSB2 and LSB is shown in the third column of Chart 1 below.

These delay values 320, 325, and 330 are unique to each interconnect, and the retiming / skew subsystem 110 compensates for different skews on each parallel interconnect to align the outputs on each parallel interconnect. Make it possible.
FIG. 10 illustrates a functional block diagram of the deskew control mechanism 135. The deskew control mechanism 135 includes a selector 1000, a control mechanism 1035, four detectors 1015, 1020, 1025 and 1030, and a plurality of registers 1050 and 1055, the number of registers depending on the number of parallel interconnects. .

  The deskew control mechanism 135 is enabled by an enable signal 1085 from any suitable control unit. One suitable control unit is a “high-speed pre-geochronous parallel link” filed on February 12, 1999 by Richard L. Schober Jr. et al., Assigned to the same assignee as this patent application and incorporated herein by reference. In US patent application Ser. No. 09 / 249,825, entitled “Automatic Initialization and Tuning via”.

  Selector 1000 receives the outputs of deskew subsystems 192 and 180 in the digital system. As illustrated in FIG. 10, the output ends 160a-160d of the deskew subsystem 192 associated with the input end 145a and the output ends 165a-165d of the deskew subsystem 180 associated with the input end 145b are connected to the selector 1000. Supplied in. The selector 1000 selects the output of one skew removal subsystem based on the input 1040 from the control mechanism 1035.

Outputs 1070a-1070d of selector 1000 are received by detector 1015 that detects for all "1" values and detector 1020 that detects for all "0" values.
The outputs 1075a and 1075b of detectors 1015 and 1020 are input into a control mechanism 1035 so that the control mechanism can calculate the delay on the interconnect associated with the selected deskew subsystem.

  Detectors 1025 and 1030 receive input directly from the output of each deskew subsystem, eg, 192 and 180, in the digital system. Detector 1025 detects all “1” values, and detector 1030 detects all “0” values. The outputs 1080a and 1080b of the detectors 1025 and 1030 are input into the control mechanism 1035 in such a way that the control mechanism 1035 can calculate the delay between each parallel input interconnect 145a and 145b in the digital system.

  Control mechanism 1035 compensates for skew and aligns the outputs on each parallel interconnect based on outputs 1075a, 1075b, 1080a and 1080b from detectors 1015, 1020, 1025 and 1030, respectively. Determine a 3-bit delay value for the input interconnect. These 3-bit delay values calculated by the control mechanism 1035 are provided in registers 1050 and 1055, which are coupled to deskew subsystems 192 and 180, respectively. In short, there is a 3-bit delay value for each register and one register for each interconnect.

  More specifically, the least significant bit 1090c of output register 1050 is coupled to delay addition input 320 of retiming subsystem 305 (FIG. 3) for input 145a, while the higher order 2 of output register 1050 The two significant bits 1090a and 1090b are coupled to the delay control inputs 325 and 330 of the coarse deskew subsystems 310 and 315, respectively, for the input 145a. Similarly, the least significant bit 1095c of the output register 1055 is coupled to the delay addition input 320 of the retiming subsystem 305 (FIG. 3) for the input 145b, while the higher two significant bits of the output register 1055. Bits 1095a and 1095b are coupled to delay control inputs 325 and 330 of coarse deskew subsystems 310 and 315, respectively, for input 145b.

  FIG. 11 is a functional block diagram of the control mechanism 1035 in the skew removal control mechanism 135 of FIG. The control mechanism 1035 is enabled by a signal 1085 received from any suitable control unit. As noted above, one such control unit is assigned to the United States, entitled “Automatic Initialization and Tuning Across High-Speed Pre-Geochronous Parallel Links,” assigned to the same assignee as this patent application and incorporated herein by reference. It is disclosed in patent application 09 / 249,825.

  The phase status register 1087 triggers a “start phase 1” signal to initiate phase 1 tuning 1410 (FIG. 15) in response to receiving the deskew enable signal 1085 from any suitable control unit. Phase status register 1087 also generates control signal 1089 to direct selection stage 1091 to phase 1 tuning 1410 or phase 2 tuning 1415 procedures. The selection stage 1091 outputs a control signal 1040 to the selector 1000 (FIG. 10) for the following purpose. In the phase 1 tuning procedure 1410 (FIG. 16), the input line is selected by the phase 1 line selection register 1093a (FIG. 11) using the selector 1000 (FIG. 10).

  In the phase 2 tuning procedure 1415 (FIG. 17), the input line is selected by the phase 2 line selection register 1093b (FIG. 11). Selection stage 1091 switches the source of selection values for selector 1000 (FIG. 10) from register 1093a or 1093b based on signal 1089 from phase status register 1087.

  The phase 1 status register 1088a receives the phase 1 start signal and generates a control signal 1092 for input into the phase 1 line select register 1093a. The phase 1 line selector 1094a associates one interconnection whose value is stored in the phase 1 line selection register 1093a with the delay value from the phase 1 status register 1088a. In the preferred embodiment, the phase 1 line selector 1094a is a multiplexer whose control value is the output of the phase 1 line selection register 1093a.

  Phase 1 status register 1088a also determines the value of the two least significant bits to provide delay control bits 320 and 330 (see FIG. 3 and Chart 1). The least significant bit corresponds to bit 320 and the next least significant bit corresponds to bit 330. The phase 1 status register 1088a determines the above-described values based on the input signals 1075a and 1075b from the detectors 1015 and 1020, respectively (see FIG. 10).

  When phase 1 tuning 1410 is complete, the phase 1 status register generates a “phase 1 complete” signal for input into phase status register 1087, and in response the phase status register initiates phase 2 tuning 1415 In order to do this, a “phase 2 start” signal is generated. Phase 2 status register 1088b generates control signal 1098 for input into phase 2 line select register 1093b. Phase 2 line selector 1094b associates the delay value from phase 2 status register 1088b with one interconnection whose value is stored in phase 2 line selection register 1093b. In the preferred embodiment, the phase 2 line selector 1094b is a multiplexer and its control value is the output of the phase 2 line selection register 1093b.

  Phase 2 line select register 1093b allows phase 2 line selector 1094b to select one of the outputs of the deskew subsystem based on the “select” signal from phase 2 line select register 1093b. In the preferred embodiment, phase 2 line selector 1094b is a multiplexer.

  Phase 2 status register 1088b also determines the value of the most significant bit to provide a delay control value 325 (see FIG. 3 and Chart 1). Phase 2 status register 1088b is based on input signals 1075a and 1075b from detectors 1015 and 1020, respectively (see FIG. 10) and from input signals 1080a and 1080b (see FIG. 10) from detectors 1025 and 1030, respectively. Determine the value of.

  When phase 2 tuning 1415 is complete, phase 2 status register 1088b generates a “phase 2 complete” signal for input into phase status register 1087, and in response, phase status register de-skews according to the present invention. A “done” signal is generated indicating the completion of the tuning procedure. A “complete” signal may be generated for any suitable control unit, as described above.

FIG. 12 illustrates a flowchart of one embodiment of a method for automatically correcting skew on signals propagating over a parallel interconnect according to the present invention. At the start of operation 1105 that occurs when the control mechanism 1035 receives the enable signal 1085, the deskew control mechanism 135 starts the deskew tuning 1115.
During de-skew tuning, the de-skew control mechanism 135 calculates an appropriate delay value for each interconnect to correct for skew on each parallel interconnect. Once in FIG. 15, it can be seen that the deskew tuning for each interconnect includes a phase that receives a known deskew initialization pattern 1405 and performs phase 1 tuning 1410 and phase 2 tuning 1415. . In one embodiment, the deskew initialization pattern is 1111 1111 0000.

  Basically, phase 1 tuning 1410 includes determining the amount of skew on each individual interconnect and aligning each of the four outputs of the deskew subsystem, while phase 2 tuning 1415 includes digital Determining the amount of delay that should be added to each interconnect to compensate for different amounts of skew between or within the parallel interconnects in the system. To perform phase 1 tuning and phase 2 tuning, detectors 1015, 1020, 1025 and 1030 search for a known de-skew initialization pattern. Based on the observed amount of skew, the automatic deskew system 100 assembles information bits on each interconnect so that all outputs are aligned (ie, adds delay to the signals on each interconnect). To do).

  FIG. 16 illustrates a flowchart of one embodiment of a method for phase 1 tuning 1410. During phase 1 tuning, the selector 1000 selects the output 160a-160d or 165a-165d of one of the interconnects 145a or 145b, respectively, in the digital system (1505). The deskew control mechanism 135 then uses the detector 1015 to determine whether all the outputs 1070a-1070d of the selected input line have a value of “1” (1510). If the outputs 1070a-1070d do not all have a value of “1”, the control mechanism 1035 continues to wait for all “1” values from the detector 1015 (1510). However, if the outputs 1070a-1070b of the selected line all have a value of “1”, the deskew control mechanism 135 outputs 1070a-1070d of the next information bits transmitted on the selected interconnect. Whether or not all have a value of “1” is determined using the detector 1015 (1515).

  If the outputs 1070a-1070d all have a value of "1", the control mechanism 1035 continues to wait for the "all values are not 1" condition. In other words, the control mechanism 1035 continues to wait until the output signal from the detector 1015 disappears. However, if the outputs 1070a-1070d do not all have a value of “1”, then the deskew control mechanism 135 uses the detector 1020 to output the next information bit transmitted on the selected interconnect. It is determined whether 1070a to 1070d all have “0” values (1520).

  If the outputs 1070a-1070d do not all have a “0” value, the delay control value will be incremented by 1 (1525) (ie, if the current delay value on the selected interconnect is 0T, this Sometimes the current delay value is 1T, otherwise, if the current delay value is 1T, then the current delay value is 2T, and so on). At this time, the deskew control mechanism 135 repeats steps 1510, 1515 and 1520 for the delayed signal. However, if the outputs 1070a-1070d have exactly all "0" values, the tuning for the selected interconnect is complete and the selector 1000 selects the next interconnect (1530) and is already in the digital system. The procedure is repeated at 1510, 1515, 1520, 1525, 1530 and 1535 until there is no interconnect (1535), at which point phase 1 tuning is complete (1540).

  FIG. 17 illustrates a flow diagram of one embodiment of phase 2 tuning 1415. At the start of phase 2 tuning 1600, the selector 1000 selects the outputs 160a-160d or 165a-165d of the interconnect 145a or 145b, respectively (1602). The deskew control mechanism 135 determines the detector 1025 to determine whether all outputs 160a-160d and 165a-165d of each deskew subsystem in the digital system all have a "1" value (1605). Use. If all the outputs 160a-160d and 165a-165d do not all have a value of “1”, then the control mechanism 1035 will detect all “1” detected from the detector 1025 (as shown in step 1605). I ’ll keep waiting. However, if all the outputs 160a-160d and 165a-165d of each deskew subsystem all have a value of “1”, the deskew control mechanism 135 is transmitted over the parallel interconnect using the detector 1025. To determine whether all outputs 160a-160d and 165a-165d of the next information bit have a value of "1".

  If all outputs 160a-160d and 165a-165d have exactly the value "1", the control mechanism 1035 continues to wait for the "all values are not 1" condition. In other words, the control mechanism 1035 continues to wait until the output signal from the detector 1025 disappears. However, if all the outputs 160a-160d and 165a-165d of each deskew subsystem do not all have a value of “1”, then the deskew control mechanism 135 then uses the detector 1030 to connect the parallel interconnects. Determine whether all outputs 160a-160d and 165a-165d of the next information bit transmitted above all have "0".

  In step 1615, if detector 1030 does not detect an “all zero” condition, control mechanism 1035 then looks at the outputs of detectors 1015 and 1020 (ie, signal lines 1075a and 1075b, respectively). If "0000" is detected by detector 1020 at step 1620, the most significant bit of the delay control 3 bits is set to "1" (1625), which means that 4T delay is interconnected (Eg, 0T delay value becomes 4T delay value; 1T delay value becomes 5T delay value; 2T delay value becomes 6T delay value; 3T delay value becomes 7T delay value) And so on ...)

  If "1111" is detected by the detector 1015 at step 1620, the delay control is not changed because the interconnect (line) selected at step 1602 is already aligned with other parallel interconnects. . At this time, selector 1000 selects the next interconnect (1630) and steps 1605-1630 are repeated to align the next interconnect with all other parallel interconnects.

If the detector 1030 detects all zeros (“0000... 0”) at step 1615, phase 2 tuning is terminated (1635).
Returning to FIG. 12, after completion of the deskew tuning 1115, it can be seen that the automatic deskew system 100 receives (1120) a 1-bit signal on the input lines 145a and 145b. Clock recovery subsystems 105 and 190 correct for any skew less than 1 bit time T on parallel interconnects 145a and 145b (1125).

  As shown in more detail in FIG. 13, the retiming subsystem 305 (i) delays the 0T or 1T signal based on the value of the 1-bit delay addition 320 calculated by the deskew control mechanism 135. Add (1210), (ii) Perform 1-2 expansion of the signal (1215), (iii) Select two consecutive bits from the delayed expanded signal (1220).

  As shown in FIG. 14, the coarse deskew subsystems 110 and 191 are now based on the values of the 2-bit delay controls 325 and 330 calculated by the deskew control mechanism 135, 0T, 2T, 4T, and 6T. An additional delay is added to the signal 320 received from the retiming subsystem in the amount of (1310). Further, the coarse skew removal control mechanisms 110 to 191 perform 1-2 expansion of the received signal (1315), and select two consecutive bits from the delayed and expanded signal (1320).

Thus, the end result of the above-described method implemented by the automatic deskew system is that all outputs on all parallel interconnects in the digital system are aligned and each output is 4 times the transmission rate of the corresponding input signal. A 4-bit expansion of the signal on each interconnect, skew corrected to have a fraction of the transmission rate.
While the invention has been particularly shown and described with reference to a preferred embodiment and a plurality of alternative embodiments, those skilled in the art will appreciate that various forms and details can be made without departing from the spirit and scope of the invention. It will be appreciated that changes can be made.

1 is a block diagram of an automatic deskew system according to an embodiment of the present invention. Fig. 3 illustrates a timing diagram for an automatic deskew system according to the present invention. FIG. 3 is a block diagram of a timing change / skew removal subsystem according to the present invention. FIG. 2 is a schematic diagram of an embodiment of a timing change subsystem according to the present invention. 4 is an input / output table for a multiplexer housed in one embodiment of a timing change subsystem. FIG. 6 is a timing diagram for a timing change subsystem. 1 is a schematic diagram of one embodiment of a coarse deskew subsystem according to the present invention. FIG. FIG. 6 illustrates an input / output table for a multiplexer housed in one embodiment of a coarse deskew subsystem. FIG. 6 illustrates a timing diagram for a coarse deskew subsystem. FIG. It is a block diagram of a skew removal control mechanism according to an embodiment of the present invention. FIG. 4 is a block diagram of a control mechanism for calculating delays between or during each parallel input interconnect. 6 is a flowchart illustrating one method of operation of the present invention for a single deskew subsystem. 6 is a flowchart illustrating one method of operation of the retiming subsystem. 6 is a flowchart illustrating one method of operation of the coarse deskew subsystem. It is a flowchart which illustrates one operation | movement method of a deskew control mechanism. It is a flowchart which illustrates one operation | movement method of the phase 1 of a deskew control mechanism. It is a flowchart which illustrates one operation | movement method of the phase 2 of a deskew control mechanism.

Explanation of symbols

100 Automatic Deskew System 105, 190 Clock Recovery Subsystem 110, 191 Retiming / Deskew Subsystem 135 Deskew Control Mechanism 145a, 145b Input Line 160a-160d Output Line 180, 192 Skew Removal Subsystem 305 Retiming Subsystem 310 , 315 Coarse deskew subsystem 345a, 345b Input signal 410, 415, 425, 430 Register 420 Multiplexer 705, 710, 715, 720, 725, 730 Register 735 Multiplexer 1000 Selector 1015, 1020, 1025, 1030 Detector 1035 Control mechanism 1050, 1055 Register 1087 Phase status register 1088a Phase 1 status register 1088b Phase 2 status register 1091 Selection stage 1093a, 1093b Line selection register 1094b Line selector

Claims (10)

An automatic deskew system for use in a high speed parallel interconnect for a digital system, wherein the automatic deskew system is adapted to receive a delay control signal for correcting skew on each of the high speed parallel interconnects. There,
A plurality of clock recovery subsystems for correcting skew less than one bit time;
Each signal coupled to the corresponding interconnect and having a skew of an integer multiple of one bit time aligns with other bits received from other interconnects based on the delay control signal A plurality of retiming / deskew subsystems capable of deploying and correcting signals on the corresponding interconnects in such a way that
Automatic deskew system with Each said retiming / deskew subsystem is
A retiming subsystem for delaying and expanding the signal by an integer multiple of one bit time;
Two coarse coupled to the retiming subsystem to delay the signal received from the retiming subsystem by an integer multiple of one bit time and to develop the signal received from the retiming subsystem. A deskew subsystem;
The automatic deskew system according to claim 1, further comprising: The retiming subsystem includes a selector;
A plurality of registers coupled to perform a 1-2 expansion of the signal on the corresponding interconnect with a delay of up to 2 bit times;
A multiplexer coupled to the register and capable of selecting one of two expanded signals, wherein each expanded signal includes two consecutive bits of an input signal and two expanded A multiplexer wherein each of the generated signals is separated by zero bit time (0T) or one bit time (1T);
An automatic deskew system according to claim 2 comprising: The coarse deskew subsystem comprises:
A plurality of registers coupled to perform a 1-2 expansion of the signal received from the retiming subsystem with a delay of up to 8 bit times;
A multiplexer coupled to the register and capable of selecting one of four expanded signals, wherein each expanded signal includes four consecutive bits of the input signal and four expanded A multiplexer wherein each of the signals separated by zero bit time (0T), 2 bit time (2T), 4 bit time (4T) or 6 bit time (6T);
An automatic deskew system according to claim 3 comprising: The clock recovery subsystem is
An interleave circuit for latching each input bit from the input signal on the corresponding interconnect in a first latch or a second latch;
A phase interpolator for providing a pulse signal in the first latch and the second latch such that the register captures a stable input value from the input signal;
A clock unit for generating the pulse signal;
The automatic deskew system according to claim 1, further comprising: An automatic deskew system for use in a high speed parallel interconnect for digital systems to correct skew on each of each parallel interconnect, the interconnect corrected for skew that is less than one bit time In an automatic deskew system adapted to receive the above signal,
A deskew control mechanism for calculating the amount of delay each interconnect requires to align the signals thereon;
A plurality of skews coupled to each corresponding interconnect and capable of being expanded and corrected so that signals on the interconnect having skew are aligned with other bits received from other interconnects. A removal subsystem;
A system comprising: In an automatic deskew system for use in a high speed parallel interconnect for a digital system to correct skew on each said parallel interconnect,
A deskew control mechanism for calculating the amount of delay each line requires to align the signals on each interconnect;
A plurality of clock recovery subsystems for correcting skew less than one bit time on the corresponding interconnect;
Each on the corresponding interconnect coupled to the deskew control mechanism and the corresponding clock recovery subsystem on the corresponding interconnect and having a skew that is an integer multiple of one bit time of up to 8 bit times (8T) A plurality of retiming / deskewing subsystems that are capable of expanding and correcting signals on the corresponding interconnects in such a way that the signals on the corresponding interconnects are aligned with other bits received from other interconnects;
A system comprising: A method for automatically correcting skew on signals propagating on a parallel interconnect, wherein each signal on one interconnect has a skew that is an integer multiple of one bit time.
Calculating a delay control value for correcting skew for each of the interconnects;
Providing an integer multiple of a one bit time delay for each of the signals based on the delay control value;
Deploying each of the signals to reduce the speed of each of the signals;
A skew correction method comprising: A method for automatically correcting skew on signals propagating on a parallel interconnect, wherein each of the signals on the interconnect has a delay control value,
Correcting for skew of less than 1 bit on each interconnect;
Providing an integer multiple of the delay from 1 bit time to 8 bit time (8T) for each of the signals based on the delay control value;
Deploying each of the signals to reduce the speed of each of the signals;
Comprising a method. In a method for automatically correcting skew on a signal propagating on a parallel interconnect,
Correcting for skew less than 1 bit time on each interconnect;
Calculating a delay control value for correcting skew for each of the interconnects;
Providing an integer multiple of a delay from 1 bit time to 8 bit time (8T) for each of the signals based on the delay control value, and each of the signals to reduce the speed of each of the signals. Deployment stage,
An automatic skew correction method comprising:

Images