JP2006313762A - Semiconductor integrated circuit and capacitance adding method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To grasp a capacitance value of capacitance to be added by FIB (focused ion beam) processing. <P>SOLUTION: An input pad 4 for a probe is connected to an input terminal of an inverter 7 for FIB processing test which is arranged in a vacant region of a device periphery, and an output pad 5 for the probe is connected to an output terminal. The capacitance C1 of a pattern of a predetermined shape dimension is formed by FIB processing so that it is connected to the output pad 5 for the probe. The inverter 7 is set in an operation enable state, a signal is inputted into the input pad 4 for the probe via a first probe, and an output signal is acquired from the output pad 5 for the probe via a second probe. A capacitance value of the capacitance C1 is acquired from the relational characteristic of the capacitance value, an actual response transition time of the output signal, and a previously acquired response transition time of the inverter 7. The capacitance of a desired capacitance value is added to a desired portion on the basis of the pattern of the capacitance C1 of the acquired capacitance value. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a capacitance adding method in a semiconductor integrated circuit for adding a capacitance and controlling the capacitance value of the capacitance, and a semiconductor integrated circuit for realizing the method.

  Conventionally, when a capacitor is added to a semiconductor integrated circuit by FIB (focused ion beam) processing for the purpose of delay adjustment or the like, a wiring node to which the capacitor is added extends to a device surface of the semiconductor integrated circuit, such as a lower layer metal or via. Then, the insulating film and the conductive metal are deposited over a long time on the extracted node.

  However, in the above method, although the capacitance can be formed without any problem, it is difficult to control the capacitance value, and it is difficult to control the circuit failure by delay adjustment or timing adjustment on the logic circuit or phase compensation on the analog circuit. A valid constant could not be narrowed down. That is, it has not been possible to quantitatively grasp how much capacitance value is added to the wiring node by FIB processing.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a capacitance adding method in a semiconductor integrated circuit capable of grasping the capacitance value of a capacitor added by FIB processing and a semiconductor integrated circuit for realizing the method.

  In the capacity addition method of the present invention, a logic gate for FIB processing test is arranged in an empty area around the device, and a probe input pad is connected to the input terminal of the logic gate and a probe output pad is connected to the output terminal. Then, a capacitor having a pattern having a predetermined shape and dimension is formed by FIB processing so as to be connected to the probe output pad, and the logic gate is set in an operable state. A signal is input through the probe and an output signal is obtained from the probe output pad through the second probe, and an actual response transition time of the output signal and a response transition time of the logic gate obtained in advance. The capacitance value of the capacitance is obtained from the relationship characteristics of the capacitance value and the capacitance value of the desired capacitance value is added to a desired location based on the pattern of the capacitance value obtained. The features.

  The semiconductor integrated circuit according to the present invention includes a logic gate for FIB processing test arranged in an empty area at the periphery of the device, a probe input pad connected to an input terminal of the logic gate, and an output of the logic gate. And a probe output pad connected to the terminal.

  Here, it is preferable that the probe input pad and the probe output pad are formed so as to have a stopper shape for preventing skidding when the probe needle is applied.

  Further, it is preferable that the connection between the probe input pad and the input terminal of the logic gate and the connection between the probe output pad and the output terminal of the logic gate are made by lower metal and vias.

  According to the present invention, a logic gate having a known output transition characteristic (calculatable by simulation, the same applies hereinafter) is arranged, and an additional capacitor is formed on the output side by FIB processing. As a result, it is possible to place a capacitor whose capacitance value has been clarified at a desired location.

  In the present invention, a logic gate for FIB processing test with known output transition characteristics is arranged in a vacant area in the periphery of the device of the semiconductor integrated circuit. Also, the input terminal and output terminal of the logic gate are pulled up to the upper layer part of the device by vias (Stacked Via) or the like so as to facilitate probing. Then, a capacitance is formed by FIB processing, the capacitance is driven by a logic gate, and the output transition time of the logic gate is monitored to quantitatively measure the capacitance value. This makes it possible to determine the conditions for the FIB processing. With reference to this, it becomes possible to place a capacity having a desired capacitance value at a desired location by the FIB processing. This will be described in detail below.

  FIG. 1 is a diagram showing a part of the upper surface of a semiconductor integrated circuit device, wherein 1 is a ring-shaped VDD electrode wiring (power supply line on I / O), 2 is a ring formed outside the VDD electrode wiring 1 This is a GND electrode wiring (ground line) having a shape. 3 is an input / output pad formed in an empty area outside the GND electrode wiring 2, 4 is a probe input pad, 5 is a probe output pad, and 6 is an inverter high-potential power connection electrode, both of which are upper layers The metal is arranged on the upper surface of the device. The shape of the probe input pad 4 and the probe output pad 5 is a U shape suitable for a skid prevention stopper at the time of probe needle application, but it may be L-shaped and the needle application direction is free. An X shape may be used to increase the degree.

  Reference numeral 7 denotes a CMOS inverter as a logic gate formed in an empty area outside the GND electrode wiring 2, and includes a common gate electrode 71, a PMOSFET source 72, a PMOSFET drain 73, an NMOSFET source 74, and an NMOSFET drain 75. It has. The gate electrode 71 is connected to the probe input pad 4 through the lower metal 81 and vias 91 and 92. The source 72 of the PMOSFET is connected to the high potential power connection electrode 6 by a lower metal 82 and vias 93 and 94. Further, the drain 73 of the PMOSFET and the drain 75 of the NMOSFET are connected to the probe output pad 5 through the lower metal 83 and vias 95 to 97. The source 74 of the NMOSFET is connected to the GND electrode wiring 2 through the lower layer metal 84 and the via 98. Thus, each terminal portion of the inverter 7 is pulled up to the same upper layer as the VDD electrode wiring 1 and the GND electrode wiring 2 by vias and lower layer metal.

  Hereinafter, the addition of the test capacity by the FIB will be described. First, as described above, the probe input pad 4, the probe output pad 5, the high-potential power connection electrode 6, and the inverter 7 as a logic gate are arranged in advance in an empty area around the device. At this time, the source 84 of the NMOSFET of the inverter 7 is also connected to the GND electrode wiring 2 in advance by the lower layer metal 84 and the via 98.

  Next, the power electrode 101 is formed between the high potential power connection electrode 6 of the inverter 7 and the VDD electrode wiring 1 by FIB processing. At this time, the GND electrode wiring 2 is insulated by an insulating film.

  Further, an insulating film (not shown) is deposited on the upper surface of the GND electrode wiring 2 by FIB processing, and further, the lead electrode 102 is formed thereon by FIB processing, and the capacitor electrode 103 is further formed to form the capacitor C1. Similarly, the capacitor electrode 104 is also formed by FIB processing to form the capacitor C2. The capacitor electrodes 103 and 104 are patterns having the same shape and size.

  FIG. 2 is a diagram showing a circuit of the inverter part before the FIB processing and after the FIB processing. Before the FIB processing, the high potential power connection electrode 6 of the inverter 7 is open as shown in FIG. 2A, but after the processing, as shown in FIG. Are connected to the VDD electrode wiring 1, and capacitances C 1 and C 2 are added to the probe output pad 5 by the capacitive electrodes 103 and 104.

  As described above, the probe 7 is applied to both the probe input pad 4 and the probe output pad 5 when the capacitor C1 is formed and when the capacitor C1 + C2 is formed. On the other hand, a pulse signal is input from the outside, and the transition time of the output waveform (for example, the rising transition time of 10% to 90% of the maximum voltage) is observed. FIG. 3 shows the characteristic P1 when the capacitance is only C1 and the characteristic P2 when C1 + C2. The rising transition times of the characteristics P1 and P2 are Tr1 and Tr2, respectively.

Therefore, for the inverter 7, the relationship between the transition time Tr of the output waveform and the value of the capacitor connected to the output side as a load is obtained in advance by simulation. This characteristic is as shown in FIG. 4, for example. The characteristics of FIG.
Tr = a × C + T0
(Where T0 is the rising transition time when there is no load, and a is the slope of the linear equation, both of which are known values), so that the capacitance value of the load capacitance C is obtained from the transition time Tr obtained by the above observation. Can be requested.

Therefore, as described above, if the capacitances C1 and C2 are made so that C2 = C1 (capacitance load area ratio is C1: C1 + C2 = 1: 2) and Tr2-Tr1 is obtained, 1 from the characteristics of FIG. : A = C1: (Tr2-Tr1)
C1 = (Tr2-Tr1) / a
Thus, the capacitance value of C1 can be obtained.

  Based on the shape and size of the electrodes 103 and 104 of the additional capacitors C1 and C2 and the thickness of the insulating film for which specific capacitance values are obtained as described above, a desired portion of the semiconductor integrated circuit is subjected to FIB processing. If an arbitrary number of similar capacitors are connected in parallel, a capacitor having a desired capacitance value can be added.

  In the embodiment described above, a case where a capacitor is formed between the capacitance electrodes 103 and 104 on the extension of the probe output pad 5 and the GND electrode wiring 2 is taken as an example. However, on the extension of the probe output pad 5 A capacitor can be formed between the capacitor electrode and the VDD electrode wiring 1, and the capacitance value can be adjusted similarly.

  Alternatively, the outermost periphery of the I / O ring may be replaced with the VDD electrode wiring 1 and the high potential power connection electrode 6 of the inverter 7 may be connected to the outermost VDD electrode wiring 1 by a metal wiring. In this case, the low-potential power connection electrode of the inverter 7 and the GND electrode wiring 2 are connected later by FIB processing. The low-potential power connection electrode is connected to the upper metal wiring by the via from the source 74 of the NMOSFET. It is necessary to draw out like the potential power supply electrode 6.

  Further, the logic gate is not limited to the inverter 7 and may be a transmission gate. In this case, a signal may be applied to the input side in advance and an ON pulse signal may be input to the gate. Further, a multi-input AND gate, an OR gate, an exclusive OR gate, or an inverting gate thereof can be used. In these cases, a pulse signal may be applied to one of the multi-input terminals, and a signal that turns on the gate when the one pulse signal is applied may be given in advance to the remaining input terminals.

It is explanatory drawing of the semiconductor integrated circuit for description of the capacity | capacitance addition method of this invention. It is the circuit diagram before the FIB process of the circuit of an inverter part, and after a process. It is an output transition characteristic figure of an inverter. It is a characteristic view which shows the relationship between the rising transition time and the value of load capacity.

Explanation of symbols

1: VDD electrode wiring 2: GND electrode wiring 3: Input / output pad 4: Probe input pad 5: Probe output pad 6: High potential power connection electrode 7: Inverter 71: Gate electrode, 72: Source of PMOSFET, 73 : PMOSFET drain, 74: NMOSFET source, 75: NMOSFET drain 81-84: Lower metal 91-98: Via 101: Power electrode, 102: Lead electrode, 103, 104: Capacitance electrode

Claims (4)

  A logic gate for FIB processing test is arranged in an empty area around the device, a probe input pad is connected to the input terminal of the logic gate, a probe output pad is connected to the output terminal, and the probe output pad is connected to the probe output pad. A pattern having a predetermined shape and dimension is formed by FIB processing so as to be connected, the logic gate is set in an operable state, and then a signal is input to the probe input pad via the first probe. In addition, an output signal is obtained from the probe output pad via the second probe, and an actual response transition time of the output signal and a relationship characteristic between the response transition time of the logic gate and the capacitance value obtained in advance are obtained. Obtaining a capacitance value of the capacitance, and adding a capacitance of a desired capacitance value to a desired location based on the pattern of the capacitance of the obtained capacitance value Capacitance adding method in the road.   A logic gate for FIB processing test arranged in an empty area in the periphery of the device, a probe input pad connected to the input terminal of the logic gate, and a probe output pad connected to the output terminal of the logic gate A semiconductor integrated circuit comprising: The semiconductor integrated circuit according to claim 2,
2. The semiconductor integrated circuit according to claim 1, wherein the probe input pad and the probe output pad are formed so as to have a skid prevention stopper shape at the time of probe needle contact. The semiconductor integrated circuit according to claim 2,
The connection between the probe input pad and the input terminal of the logic gate and the connection between the probe output pad and the output terminal of the logic gate are performed by a lower layer metal and a via. .

Images