JP2006313203A - Masking signal controller, image forming apparatus and masking signal control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To secure an operation coping with the occurrence of noise without applying loads on software or the like, even when the frequency of an input signal is changed at any timing, and to prevent a reflection time lag. <P>SOLUTION: A first input signal masking period N is set, and the edge of the first input signal is counted by a second input signal. When the counted value shows the masking period N, a masking signal for the first input signal is generated, and the final counted value X or a value X+1 is held. Next, whether or not the final counted value X or the value X+1 is continued is checked, and when the check result is affirmative, returning to a step S102, and the subsequent processing is repeated, when the result is negative, a final counter value Y larger than the value X or a value Y+1 is held, then, the first input signal masking period N is automatically updated to a period M. Thereafter, the edge of the first input signal is counted by the second input signal, and when the counted value shows the period M, a changed masking signal for the first input signal is generated by a masking signal changing circuit. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a mask signal control device having a function of masking a predetermined area of one input signal based on one input signal of two input signals, an image processing device including the mask signal control device, and the image processing device. The present invention relates to an image forming apparatus such as a digital full-color laser printer, a digital full-color copying machine, and a digital multi-function peripheral.

  As this type of technology, for example, the invention disclosed in Patent Document 1 is known. The present invention inputs a clock synchronized with a video synchronization signal, counts the number of clocks corresponding to one period of the video synchronization signal, and inputs a count value output from the counting means, Count value storage means for storing the count value of the previous period in the video synchronization signal, and the output from the count value storage means, the count value of the current period of the video synchronization signal becomes before and after the count value of the previous period. Mask pulse generating means for generating a mask pulse for masking other than a predetermined count interval, and mask means for masking the video synchronization signal with the mask pulse are provided. Here, a circuit configuration and a sequence for realizing noise removal are simplified by using a counter that measures the frequency of an arbitrary synchronization signal to be input.

Further, as a related technique, for example, an invention described in Patent Document 2 or 3 is also known.
JP 2002-300909 A JP 2003-046766 A Japanese Patent Laid-Open No. 10-010827

  In the invention described in Patent Document 1, the counter for measuring the frequency and the noise removal counter are combined, but this method is general. Furthermore, since the invention described in Patent Document 1 does not include a mask pulse changing means when the frequency of the input signal is intentionally changed except for noise, the conventional masking circuit is insufficient in dealing with the change. Therefore, it is not possible to guarantee an operation for noise generation immediately after the frequency is changed. Further, since the frequency change setting is performed by software or the like, it cannot be denied that there is a delay in the reflection timing.

  The present invention has been made in view of the actual situation of the prior art, and its purpose is to perform an operation against noise generation without applying a load to software or the like, regardless of the timing of the input signal frequency. This is to ensure that there is no delay in the reflection timing.

  The first means receives a first signal having an arbitrary frequency and a second signal having a higher frequency than the first signal, and counts the second signal as a clock. A means for operating the counting means in synchronization with a rising edge or a falling edge of the signal, and a mask for the first signal until a count value of the counting means reaches a preset arbitrary value. A means for generating a signal; a means for estimating a change in the frequency of the first signal based on the count value; and an automatically set arbitrary value based on a result estimated by the means for estimating. A mask comprising: updating means; and means for automatically changing a period of the mask signal generated by the means for generating the mask signal based on an arbitrary value updated by the automatic updating means. Wherein the signal control unit.

  The second means is a transfer medium in which the second signal is a synchronization detection signal for synchronizing the main writing direction of the optical writing device in the first means, and the first signal is a transfer medium on which an image is transferred. In this case, the detection signals are marks detected at regular intervals.

  A third means is characterized in that, in the first means, the second signal is a pixel clock, and the first signal is a motor clock of a motor for driving an image forming medium on which optical writing is performed. To do.

  According to a fourth aspect of the present invention, in the first to third aspects, the automatic updating means is preset at a timing at which the frequency of the first signal of the arbitrary frequency is changed to 1 / n times. Any given value is automatically updated to a length indicated by its reciprocal.

  A fifth means is characterized in that, in the fourth means, the n is 2.

  Sixth means includes optical writing means for optically writing to the image forming medium, image data transfer means for transferring image data from a host device to the optical writing means in synchronization with a predetermined pixel clock, and the optical writing Synchronization detecting means for generating timing for synchronous detection of writing light in the main scanning direction, marks provided on a transfer medium onto which an image formed on the image forming medium is transferred, and the mark Detecting means for outputting a detection signal, generating means for generating a reference timing signal based on the detection signal detected by the detection means, and a mask according to any one of the first to fifth means An image forming apparatus including a signal control device is characterized.

  The seventh means includes a step of setting a mask period N of the first signal, a step of counting the first signal edge with a second signal, and a count value counted in the counting step is the N Generating a mask signal for the first signal and holding a final counter value, and if the held final counter value is not a continuous value, a value larger than the final counter value is set to a final counter value And a step of updating the mask period of the first signal based on the value as a reference.

  The eighth means includes a step of counting the first input signal edge with the second input signal after updating the mask period of the first signal, and a mask period in which the count value is updated in the counting step. And a step of generating a new mask signal when the final counter value corresponding to is reached.

  In the embodiment described later, the counting means is the counter value holding and comparing circuit 3, the means for operating the counting means is the latch circuit 2, the means for generating the mask signal is the mask signal generating circuit 6, The means for estimating the frequency change of the first signal is the first frequency change estimating circuit 4, the means for automatically updating any preset value is the set value N changing circuit 5, the means for automatically changing the period of the mask signal Corresponds to the mask signal changing circuit 7, respectively.

  According to the present invention, the frequency change of the first signal is estimated, and based on the estimated result, the preset arbitrary value is automatically updated and the period of the mask signal is automatically updated. Even if the frequency of the signal is changed at any timing, it is possible to guarantee the operation against the occurrence of noise without causing a load on the software or the like, and to prevent the reflection timing from being delayed.

  Embodiments of the present invention will be described below with reference to the drawings.

<First Embodiment>
FIG. 1 is a functional block diagram showing a configuration of a mask signal control circuit 10 in an image processing apparatus according to an embodiment of the present invention. FIG. 2 is a timing chart showing a relationship between first and second input signals, a counter, and a mask signal. FIG. 3 is an enlarged view of the portion shown in FIG. 2A.
In FIG. 1, a mask signal control circuit 10 includes an edge detection / counter circuit 1, a latch circuit 2, a counter value holding / comparison circuit 3, a first input frequency change estimation circuit 4, a set value N change circuit 5, and a mask signal generation circuit. 6 and a mask signal changing circuit 7.

  The edge detection and counter circuit 1 receives the first and second input signals SG1 and SG2, and the latch circuit 2 receives the first input signal SG1 and the output from the edge detection and counter circuit 1. The counter value holding and comparing circuit 3 receives the second input signal SG2 and the output from the latch circuit 2, and the first input frequency change estimating circuit 4 receives the counter value holding and comparing circuit 3 output. The output of the first input frequency change estimation circuit 4 is input to the set value change circuit 5, and the output of the edge detection and counter circuit 1 and the set value “N” are input to the mask signal generation circuit 6 to change the mask signal. The outputs of the set value changing circuit 5 and the mask signal generating circuit 6 are input to the circuit 7, and the changed mask signal is output from the mask signal changing circuit 7.

  In this embodiment, with respect to the first input signal SG1 having an arbitrary frequency, the second input signal SG2 having a frequency higher than the frequency of the first input signal SG1 is used as a clock for the first input signal SG1. When the counter is operated in synchronization with the rising edge or the falling edge, and the mask signal is generated for the first input signal SG1 until the count value of the counter reaches a predetermined value, A counter value using the second input signal SG2 is used to estimate a change in the frequency of the first input signal SG1, and the preset arbitrary value is automatically updated based on the result, The period of the mask signal is automatically updated.

  Specifically, as shown in FIG. 2, when a first input signal SG1 asynchronous with each other and a second input signal SG2 having a higher frequency than the first input signal SG1 are given, the edge detection and counter circuit 1 uses the first input signal SG1. The rising edge of the signal SG2 is detected, and the up counter is activated by the rising edge of the second input signal SG2 serving as a reference clock. The initial counter value at this time is “0”. The mask signal SGM against external noise that affects the first input signal SG1 in parallel with this operation until the counter value advances to a value preset by a CPU or the like = “N”, for example, in advance. Is generated by the mask signal generation circuit 6. That is, the mask signal SGM is active during the period from “0” to “N” of the up counter (“H” in FIG. 2). Since the first input signal SG1 and the second input signal SG2 are asynchronous with each other, the actual mask signal SGM is the maximum of about one clock of the second input signal SG2 from the rising edge of the first input signal SG1. Delay will occur.

In such a configuration, a case is considered where the frequency of the first input signal SG1 is changed by an external setting or an operation mode change.
In the counter operation by the second input signal clock at the frequency change point of the first input signal SG1 in FIG. 3 (see the enlarged view of FIG. 2A), after the counter value reaches “N” and the mask signal generation ends. The count is further advanced, and the counter value is updated until the next rising edge of the first input signal SG1 is detected. At this time, the counter value is held until the start of the next cycle of the first input signal SG1 (rising detection here). However, since the first input signal SG1 and the second input signal SG2 are asynchronous with each other, the value held in the latch circuit 2 is X + 1 or X + 2 here. In this way, the cycle of the first input signal SG1 is calculated with the counter value based on the second input signal SG2. This operation example is an example in the case where the frequency of the first input signal SG1 is unknown, and is not limited to this if the frequencies of the first and second input signals SG1 and SG2 are known in advance.

  Next, when the frequency of the first input signal SG1 is changed, the holding counter value by the second input signal SG2 inevitably changes as described above. In this embodiment, generally, when the frequency of a signal to which the mask signal SGM is to be applied is changed, a method of changing the setting value of the mask generation period by software is generally considered. As a result, a new set value is reflected after a considerable time has elapsed since the frequency change, and the mask process for the noise pulse superimposed on the first input signal SG1 during that time is often not in time. Therefore, in the present embodiment, processing is performed as follows.

  For example, when the counter value is not cleared to “0” even if the counter value N + 2 is exceeded with respect to the first input signal SG1 that has shifted to the next cycle with the counter value N + 1 or N + 2 in FIG. It is estimated that the frequency of the input signal SG1 has been changed. That is, here, a state in which the next rising edge of the first input signal SG1 has not yet been detected is shown. When such a state is detected, the count operation is continued and the count value is updated until the next rising edge of the first input signal SG1 is reached. FIG. 3 shows an example in which the next rising edge is detected with the count value “M”. This processing is performed by the counter value holding and comparison circuit 3.

  When this state is detected, the first input frequency change estimation circuit 4 determines that the frequency of the first input signal SG1 has changed (here, the frequency has decreased), and the mask signal SGM generated by the first input signal SG1. The setting value N changing circuit 5 for automatically updating the assertion period of is activated. FIG. 3 shows an example in which the preset value (set value) “N” is set to “M” (where N <M) because the frequency of the first input signal SG1 has decreased. Is the reciprocal of the frequency change rate (frequency before change / frequency after change) of the first input signal SG1, the mask period for the first input signal SG1 is the mask signal in the state before the frequency change. It is relatively equivalent to SGM. This change is performed by the mask signal changing circuit 7 (FIG. 1).

  If for some reason the first input signal SG1 stops at "H" or "L" and the next edge cannot be detected, the counter overflows. In this case, the first input signal The following processing or the like may be executed based on the determination that SG1 is stopped. Further, the mask signal SGM may be output to the outside and used for monitoring whether the operation is following the change of the first input signal SG1.

  Further, in the present embodiment, the detection of the first input signal SG1 and the second input signal SG2 and the synchronization edge are all detected as “H: rising”. The combination of signals is not limited to the above-described embodiment.

  The processing procedure at this time is shown in the flowchart of FIG. In this processing procedure, first, a first input signal mask period “N” is set (step SG101), and the edge of the first input signal SG1 is set as described with reference to FIG. 2 or FIG. Is counted by the input signal SG2 (step S102). When the count value reaches the mask period “N” (step S103-Y), a mask signal for the first input signal SG1 is generated (step S104), and the final counter value “X” or “X + 1” is held as the counter value. And it hold | maintains at the comparison circuit 3 (step S105-FIG. 3). Next, it is checked whether or not the final counter value “X” or “X + 1” is continuous (step S106). If it is continuous, the process returns to step S102 and the subsequent processing is repeated. The final counter value “Y” or “Y + 1” larger than “H” is held (step S107), and the first input signal mask period “N” is automatically updated to “M” (see step S108, FIG. 2 and FIG. 3). .

  Thereafter, the first input signal edge is counted by the second input signal SG2 (step S109), and when the count value becomes “M” (step S110-Y), the mask signal changing circuit 7 performs the first input signal edge. After the change to the input signal SG1, a mask signal SGM ′ is generated (step S111), and the process is finished.

  Even in the superimposition of noise that tends to occur frequently in the vicinity of the change point of the rise or fall of the input signal by the configuration and processing as described above, the second of the frequency higher than the frequency of the first input signal SG1. The mask pulse period can be changed with a simple circuit configuration using the input signal SG2 as a clock. For this reason, no matter what timing the frequency of the first input signal SG1 is changed, the noise mask signal is applied at a prompt timing without imposing a load on software or the like with respect to noise affecting the input signal SG1. Can be generated.

<Second Embodiment>
The second embodiment is an example in which the mask signal control apparatus in the first embodiment is applied to an image forming apparatus. FIG. 5 is a block diagram showing a schematic configuration of a control system of a digital full-color copying machine as an image forming apparatus according to the present embodiment, and FIG. 6 is an engine unit of a 2LD digital full-color copying machine having two LDs. 6 is a diagram showing a schematic configuration, and an image printing unit in FIG. 5 corresponds to the engine unit in FIG.

  5, the control system of the digital color copying machine according to the present embodiment includes a main control unit 108, a FAX control unit 102 connected to the main control unit 108, a printer control unit 103, an input image processing unit 106, a writing It mainly comprises a control unit 110, a key operation unit 107, and a memory unit 109. The FAX control unit 102 includes a FAX I / F 101, the printer control unit 104 includes a host I / F 103, the input image processing unit 106 includes a document reading unit 105, and the writing control unit 110 includes an image printing unit 111. Each is connected.

  A FAX I / F 101 is an interface from a FAX application, and is an interface part for transferring FAX transmission / reception data. The FAX control unit 102 performs processing according to transmission / reception data from the FAX I / F 101 in accordance with the communication specifications of each FAX, and the host I / F 103 transfers images from the host or network. The printer control unit 104 processes data from the host I / F 103 via a controller, and the document reading unit 105 reads a document from a document table or an ADF (automatic document feeder). The input image processing unit 106 has a function of performing input processing on the document read by the development reading unit 105.

  The key operation unit 107 is used to select an application, the number of printed sheets, a paper size, enlargement / reduction, a user program (UP), and a service program (SP) in the digital full-color copying machine (hereinafter simply referred to as a copying machine) according to the present embodiment. Each selection / setting key, other various settings, and various keys for clearing the setting mode and starting / stopping the operation are included. The main control unit 108 has a function of overall control of data transfer from each application of the copier main body, and communicates with a control circuit that controls each peripheral application such as a CPU, timing control, and command I / F. To manage. The memory unit 109 stores image data from the FAX control unit 102, the printer control unit 104, and the input image control unit 106, and the write control unit 110 matches the image data from the main control unit 108 with the transfer paper size. It has a function of setting an image area and performing LD modulation and transferring it to the engine portion of the copier. The image printing unit 111 is an image printing unit that prints an image on a transfer sheet via a transfer of a photoconductor (OPC), an intermediate transfer belt, and the like, and fixes and outputs the image. The CPU performs various controls by executing a program stored in a ROM (not shown) while using a RAM (not shown) as a work area.

  In a copier having such a control system, each unit is controlled in accordance with an instruction signal from the key operation unit 107, and a printing operation is started by a command signal from the main control unit 108. The functions of the key operation unit 107, the main control unit 108, and the write control unit 110 are realized by a program, and the program data of the program is written in the storage means of each unit in advance, but a hard disk (not shown) or rewritable Download and use program data via a known recording medium such as a CD-ROM or SD card driven by a server or storage medium drive connected to a network (not shown) in a storage device, or upgrade the version Is also possible.

  In the case of a copy operation, the function of the writing control unit 110 first transfers the image data from the input image processing unit 106 from the main control unit 108 to the writing control unit 110, and the image printing unit 111 is transferred based on the transferred image data. Drives and prints image data. By repeating this operation in the main scanning direction and the sub-scanning direction by the writing control unit 110 (the writing unit in FIG. 6), printing of a plurality of sheets is continued.

  In FIG. 6, the copying machine 100 includes an image forming system, a writing system, a transfer system, a fixing system, a paper feeding system, a duplex paper feeding system, and a paper discharging system.

  The image forming system includes a photosensitive belt 215, a charging unit 205 for charging the photosensitive belt 215, a magenta developing unit for developing each color latent image, a cyan developing unit, a yellow developing unit, and a black (yellow) developing unit. Black) A developing unit 202 composed of a developing unit, a photosensitive member cleaning unit 203 for removing residual toner on the photosensitive belt 220, and the charge removal on the photosensitive belt 215 in order to reuse the photosensitive belt 215 in the next development cycle. The static elimination unit 204 to be used.

  The writing system corresponds to the writing control unit 110 in FIG. 5, and includes a writing image processing IC, a pixel clock generation / LD modulation IC, first and second two laser diodes, a writing optical system including a polygon mirror, and synchronization. A detection unit is provided, and optical writing (exposure) is performed on the photosensitive belt 215 charged by the charging unit 205 to form a latent image for each color.

  The transfer system includes an intermediate transfer belt 206, a primary transfer brush 208 for transferring a toner image from the photosensitive belt 215 to the intermediate transfer belt 206, and a toner image transferred to the intermediate transfer belt 206 transferred to a sheet (transfer material). The secondary transfer roller 210 is a cleaning brush roller 207 that removes toner remaining after the transfer.

  The fixing system includes a fixing belt type fixing unit 211 provided downstream of the secondary transfer roller 210 in the sheet conveyance direction, and fixes a full-color image on the sheet by heating and pressing.

  The paper feed system includes a paper feed tray 209 that stores paper used for image formation, a paper feed roller 216 that pulls out the paper from the paper feed tray 209 and feeds the paper to the transport path 218 side, and a transport roller that transports the paper through the transport path 218. 217 and a registration roller 219 that feeds a sheet in time with the leading edge of the image on the intermediate transfer belt 206 in the secondary transfer portion where the secondary transfer roller 210 is disposed.

  The duplex feeding system includes a duplex unit 221 having a branch unit 212 and a switchback path 222. The branch unit 212 includes a branch claw 220, and switches between a transport path for discharging a fixed sheet and a transport path for transporting the sheet to the duplex unit 221 side. The duplex unit 221 carries a sheet from the branch unit 212 and leads it to a switchback path 222, a switchback roller 224 that switches back a sheet carried from the sheet carry-in path 223 to the switchback path 222, and a switch A conveyance path 226 that guides the sheet from the back roller 224 to the secondary transfer roller 210 again through the branch claw 225 is provided. The sheet conveyance path 226 guides the sheet reversed by the duplex unit 221 to the nip of the registration roller 219. Note that a plurality of transport roller pairs 227 for transporting paper are provided in the paper transport path 226.

  The paper discharge system includes a paper discharge tray 228 and a paper discharge roller 229 that discharges paper from the branch unit 212 to the paper discharge tray 228.

  The operation of the image printing unit (one-drum type engine portion) including the write control unit 110 configured as described above is roughly as follows.

  A latent image is formed on the photosensitive belt 215 by laser light exposed from a writing unit (same as the writing control unit 110 in FIG. 1), and toner development is performed by a developing device 202 for each of magenta, cyan, yellow, and black. Do. Further, the charging unit 203, the charge removal unit 204, and the photosensitive member cleaning unit 205 perform the removal / charging of the photosensitive member and the cleaning of the photosensitive belt 215. Thereafter, intermediate transfer to the intermediate transfer belt 206 is performed by the intermediate transfer belt 206, the cleaning brush roller 207, and the primary transfer brush 208, and the image on the intermediate transfer belt 206 is transferred to the sheet fed from the sheet feed tray 209 by 2. The image is transferred by the next transfer roller 210 to form an image on the paper. The image formed on the sheet is heat-fixed by the fixing unit 211 and passes through the branch unit 212 and is discharged to the main body or in any of the discharge paths to the duplexer 213 in the case of FIG. . Through the series of operations described above, printing is performed based on print data input from the host via the host I / F 103. In the case of color printing of two or more colors, the above series of operations is repeated for each color.

  In a color copying machine (image forming apparatus) having such a configuration, a polygon mirror for reflecting laser light from a laser light source, a polygon motor driving means for driving a polygon motor for controlling rotation of the polygon mirror, and a laser light source A synchronization signal from a synchronization detection circuit that generates timing for detecting the laser beam for synchronization detection in the main scanning direction is defined as a first input signal SG1 in the first embodiment. Further, a predetermined pixel clock for transferring image data from the host device to the laser driving unit is set as a second input signal SG2. Although not shown above, the polygon motor driving means and the synchronization detection circuit are mounted inside the writing unit 201 of FIG.

  FIG. 7 is an enlarged view of the intermediate transfer portion of FIG. 6, and FIG. 8 shows a belt mark formed on the intermediate transfer belt 206 of the intermediate transfer portion and a sensor SN1 for detecting the belt mark. Repetitive black / silver marks MK1 and MK2 as shown in FIG. 8 are formed on the back surface of the intermediate transfer belt 206, and the marks are read by the sensor SN1. Reference numeral 206a denotes a detent guide for detaining the intermediate transfer belt 206.

  FIG. 9 is a timing chart showing the timing of mask processing in this embodiment in which the belt mark signal is the first input signal SG1 and the synchronization detection signal is the second input signal SG2. When the marks MK1 and MK2 pass through the detection portion of the sensor SN1 due to the travel of the intermediate transfer belt 206, for example, the black mark MK1 reacts such as ON when passing the sensor, and OFF when the silver mark MK2 passes the sensor SN1. The output from the sensor SN1 is obtained as a digital rectangular wave as shown in the timing chart of FIG. The sensor SN1 includes sensors of different types such as a transmission type and a reflection type. In the present embodiment, a description will be given using a reflection type sensor.

As shown in FIG. 9, the signals obtained by the belt marks MK1 and MK2 that have passed through the sensor SN1 in the above-described state are used for the first input signal SG1, the polygon mirror rotation, and synchronization detection in the first embodiment. A synchronization detection signal obtained as a result of LD lighting is the second input signal SG2 in the first embodiment. In this embodiment, the belt mark signal SG1 has a frequency (belt mark frequency: fb) of 178 mm / s for the linear velocity of the photosensitive belt 215, 25 belt marks on the intermediate transfer belt 206, and 21 mm for the belt mark interval. Then,
fb = 1 / (21/178)
= About 8.5 Hz (first input signal SG1)
It becomes. On the other hand, the frequency fd of the synchronization detection signal is equal to the polygon scanning frequency when the polygon rotational speed is about 21000 rpm, the sub-scanning pixel density is 600 dpi, and the device using the 2LD method.
fd = 600 × 178 / 25.4 / 2
= About 2102 Hz (2nd input signal SG2)
Thus, the higher the frequency of the second input signal SG2 to be synchronized, the more accurate the mask signal can be generated.

  By applying the control conditions of the mask signal control apparatus in the first embodiment to the color copying machine configured as described above, the noise mask pulse for the belt marks MK1 and MK2 on the intermediate transfer belt 206 is changed to the frequency of the synchronization detection signal ( The signal can be generated by a signal based on the polygon scanning frequency (in FIG. 9, the number of mask counters is “N”), and the noise portion generated in the belt mark signal SG1 can be masked.

  Other parts that are not particularly described are configured in the same manner as the first embodiment and function in the same manner.

  The first arbitrary value set at the timing when the first input signal SG1 having an arbitrary frequency or the frequency of the belt mark signal from the intermediate transfer belt marks MK1 and MK2 is changed to 1 / n times is: It can also be configured to automatically update to the length indicated by its reciprocal. With this configuration, no matter what frequency change occurs in the first input signal SG1, the noise mask period after the frequency change is changed to the reciprocal value of the frequency change, so the noise with respect to the first input signal SG1 In the mask period, it is possible to keep the same state as before the frequency change as viewed relatively. In order to realize this configuration, the first input frequency change estimation circuit 4 in FIG. 1 in the first embodiment compares the counter value before and after the counter value, and the frequency change rate (frequency before change / after change) from the ratio. And a function for obtaining the reciprocal thereof. Thereby, even if the first input signal SG1 causes any frequency fluctuation, the period of the mask signal corresponding to the frequency fluctuation can be flexibly and automatically changed.

  If the frequency 1 / n times n is set to 2, for example, noise mask signal generation in the operation of switching from constant speed to half speed can be realized with a simple configuration and high accuracy.

  According to this embodiment, a change in the speed of the intermediate transfer belt 206 occurs due to a change in the speed of the photoreceptor motor that drives the photoreceptor belt 215 (for example, constant speed → half speed), and the frequency of the belt mark input signal is changed. Even if it exists, it becomes possible to change the length of the noise mask signal with respect to the change of the frequency by automatically updating an arbitrary set value set in advance, and to secure a mask area for noise.

<Third Embodiment>
In general, in the case of printing using thick paper or OHP paper, a system is adopted in which the fixing motor accuracy is increased by dropping the photosensitive motor from a constant speed to a half speed during fixing. In such a case, when the speed of the photoconductor motor is halved, the frequency of the photoconductor motor clock also changes. The third embodiment is an example in which a mask signal is generated using a photoconductor motor clock.

  Also in this embodiment, the mask signal control circuit 10 according to the first embodiment is applied to the color copying machine according to the second embodiment, and the photosensitive motor clock and the second input signal SG2 are used as the first input signal SG1. The pixel clock is used. A timing chart at this time is shown in FIG. The other parts are configured in the same way as in the first and second embodiments, so redundant description is omitted.

  With this configuration, when the frequency of the photoconductor motor clock (first input signal SG1) changes, the photoconductor motor speed → the running speed of the intermediate transfer belt → the frequency of the intermediate transfer belt mark changes in conjunction with it. Since the configuration uses the change in the photoconductor motor clock SG1 directly, the photoconductor is detected with higher accuracy than when detecting and controlling the belt marks MK1 and MK2 on the intermediate belt 206 as in the second embodiment. A change in the speed of the belt 215 can be detected. As a result, it is possible to generate a more accurate noise mask signal for the noise signal superimposed on the intermediate transfer belt 206. Furthermore, since a pixel clock with higher accuracy than the synchronization detection signal is used, it is possible to expect improvement in accuracy on the circuit.

  The details of the timing chart of FIG. 10 are the same as those described in the first embodiment with reference to FIG. 3, and the first input signal SG1 in the first embodiment is used as the photoconductor motor clock. Is merely replaced with the pixel clock.

  According to this embodiment, since the frequency change is detected using the photoconductor motor clock itself, the length of the noise mask signal is changed following the timing with higher accuracy than the method of the second embodiment, so that A mask area can be secured.

1 is a block diagram showing a schematic configuration of a mask signal control circuit according to a first embodiment of the present invention. 2 is a timing chart showing output timings of first and second input signals, counters, and mask signals in FIG. 1. It is a figure which expands and shows the principal part of FIG. It is a flowchart which shows the process sequence of the mask signal processing control circuit of FIG. FIG. 5 is a block diagram illustrating a schematic configuration of a control system of a digital full-color copying machine as an image forming apparatus according to a second embodiment of the present invention. It is a figure which shows schematic structure of the engine part of the digital full-color copying machine of FIG. FIG. 7 is an enlarged view of an intermediate transfer portion in FIG. 6. FIG. 8 is a diagram illustrating a belt mark formed on an intermediate transfer belt of the intermediate transfer unit in FIG. 7 and a sensor for detecting the belt mark. It is a timing chart which shows the timing of the mask process which made the belt mark signal the 1st input signal and made the synchronous detection signal the 2nd input signal. 10 is a timing chart illustrating timing when a photosensitive motor clock is used as a first input signal and a pixel clock is used as a second input signal in the third embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Edge detection and counter circuit 2 Latch circuit 3 Counter value holding | maintenance and comparison circuit 4 1st input frequency change estimation circuit 5 Set value N change circuit 6 Mask signal generation circuit 7 Mask signal change circuit 10 Mask signal control circuit 104 Printer control part 108 Main control unit 110 Write control unit 111 Image printing unit SG1 first input signal SG2 second input signal SGM mask signal

Claims (8)

Means for inputting a first signal having an arbitrary frequency and a second signal having a higher frequency than the first signal, and counting the second signal as a clock;
Means for operating the means for counting in synchronization with a rising edge or a falling edge of the first signal;
Means for generating a mask signal for the first signal until the count value of the means for counting reaches a predetermined arbitrary value;
Means for inferring a change in frequency of the first signal based on the count value;
Means for automatically updating the preset arbitrary value based on the result estimated by the estimating means;
Means for automatically changing the period of the mask signal generated by the means for generating the mask signal based on an arbitrary value updated by the means for automatically updating;
A mask signal control device.   The second signal is a synchronization detection signal for synchronizing in the main scanning direction of the optical writing device, and the first signal is a detection signal of a mark provided at a fixed interval on a transfer medium to which an image is transferred. 2. The mask signal control apparatus according to claim 1, wherein the mask signal control apparatus is provided.   2. The mask signal control apparatus according to claim 1, wherein the second signal is a pixel clock, and the first signal is a motor clock of a motor that drives an image forming medium on which optical writing is performed.   The means for automatically updating automatically updates the preset arbitrary value to a length indicated by its reciprocal at a timing when the frequency of the first signal of the arbitrary frequency is changed to 1 / n times. The mask signal control device according to claim 1, wherein the mask signal control device is a mask signal control device.   5. The mask signal control apparatus according to claim 4, wherein n is 2. Optical writing means for performing optical writing on the image forming medium;
Image data transfer means for transferring image data from the host device to the optical writing means in synchronization with a predetermined pixel clock;
Synchronization detection means for generating timing for synchronization detection in the main scanning direction of the writing light of the light writing means, marks provided at regular intervals on a transfer medium to which an image formed on the image forming medium is transferred,
Detecting means for detecting the mark and outputting a detection signal;
Generating means for generating a reference timing signal based on the detection signal detected by the detecting means;
The mask signal control apparatus according to any one of the first to third aspects;
An image forming apparatus. Setting a mask period N of the first signal;
Counting the first signal edge with a second signal;
Generating a mask signal of the first signal when the count value counted in the counting step becomes N, and holding a final counter value;
If the held final counter value is not a continuous value, a value larger than the final counter value is held as a final counter value, and the mask period of the first signal is updated based on the value;
A mask signal control method comprising: Counting the first input signal edge with the second input signal after updating the mask period of the first signal;
Generating a new mask signal when the count value reaches a final counter value corresponding to the updated mask period in the counting step;
The mask signal control method according to claim 7, further comprising:

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