JP2006310650A - Imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a structure where the leakage of an electric charge to an adjacent pixel can be prevented at a high level. <P>SOLUTION: The imaging device is equipped with a photoelectric converter which is constituted including an n-type semiconductor area 302 and a p-type buried semiconductor area 309, a transferring area (floating diffusion) 307 to which an electric charge generated in the photoelectric converter is transferred, an element separating area 306 which encloses a pixel area including the photoelectric converter and the transferring area 307, and a potential barrier area 310 (310a, 310b and 310c) which encloses at least a part of the pixel area located below the element separating area 306. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an imaging device having a potential barrier region.

  A MOS imaging device having an amplifying element in a pixel consumes less power and has a lower driving voltage than a CCD imaging device. Furthermore, since the MOS type imaging device is manufactured by a general-purpose semiconductor manufacturing process, it is advantageous in terms of cost.

  Patent Documents 1 and 2 disclose a technique for preventing charge from leaking from a pixel to a pixel adjacent thereto in a MOS type imaging device.

  In Patent Document 1, a high-concentration P-type semiconductor region is disposed on an N-type silicon substrate, and an N-type epitaxial layer serving as a cathode of a photodiode is disposed on the P-type semiconductor region. A structure is disclosed in which an isolation region (potential barrier) is disposed in contact with the P-type semiconductor region in the layer, and a P-type well is disposed on the isolation region. Here, the isolation region (potential barrier) and the P-type well are disposed under the field oxide film and under the transfer gate.

  Patent Document 2 discloses a configuration having a deep channel stop region below a transfer gate.

Patent Document 3 discloses a configuration in which a photoelectric conversion element is surrounded by a P well at a predetermined depth and a P well provided under an element isolation region.
JP 2004-193547 A JP 2003-069005 A JP 2001-053260 A

  In the imaging devices described in Patent Documents 1 and 2, since an isolation region or a channel stop region that forms a potential barrier is arranged below the transfer gate, these are the channel of the transfer transistor and the depletion region of the photodiode. To affect. Therefore, the impurity concentration distribution in the isolation region or channel stop region must be determined in consideration of the channel of the transfer transistor and the depletion region of the photodiode in addition to preventing charge leakage to adjacent pixels. The degree is low. Therefore, in the imaging devices described in Patent Documents 1 and 2, it is difficult to form a potential barrier that prevents charge leakage to adjacent pixels at a high level.

In the imaging device described in Patent Document 3, the P-well provided under the element isolation region is formed by a single ion implantation process, and the photoelectric conversion element is extended to the deep part of the substrate in order to improve sensitivity. When formed, the characteristics as a potential barrier may not be sufficient. This tendency is particularly noticeable when a P-type semiconductor region having a concentration peak in the depth direction is formed at a deep position on the substrate.
In the case where the isolation characteristics are designed to be sufficient, the potential barrier region expands in the lateral direction, which may affect the characteristics of the photoelectric conversion portion and the transistor in the pixel region.

  The present invention has been made on the basis of the above problem recognition, and an object of the present invention is to provide a structure capable of reducing charge leakage to adjacent pixels at a high level.

  An imaging device according to a first aspect of the present invention includes a semiconductor substrate, a first semiconductor region of a first conductivity type that is the same conductivity type as a signal charge formed on the semiconductor substrate, and the first semiconductor A photoelectric conversion unit configured to include a second semiconductor region of a second conductivity type formed in a deeper part of the semiconductor substrate than the region, a transfer region to which charges generated by the photoelectric conversion unit are transferred, An element isolation region surrounding a region including the photoelectric conversion unit and the transfer region, and a second conductivity type disposed below the element separation region and surrounding at least a part of the region together with the second semiconductor region. A potential barrier region, and the potential barrier region includes a plurality of barrier regions arranged at different depths.

  An imaging device according to a second aspect of the present invention is an imaging device having first and second pixels formed on a semiconductor substrate, and each of the first and second pixels has the same conductivity type as a signal charge. And a first conductive type first semiconductor region, and a second conductive type second semiconductor region formed deeper in the semiconductor substrate than the first semiconductor region. And a transfer region to which charges generated by the photoelectric conversion unit are transferred, and the imaging device is disposed between the transfer region of the first pixel and the photoelectric conversion unit of the second pixel The device has a device isolation region and a potential barrier region disposed below the device isolation region, and the potential barrier region includes a plurality of barrier regions disposed at different depths.

  An imaging system according to a third aspect of the present invention is output from the imaging device according to the first or second aspect, an optical system that forms an image on the imaging surface of the imaging device, and the imaging device. A signal processing circuit for processing the signal.

  ADVANTAGE OF THE INVENTION According to this invention, the structure which can reduce the leakage of the electric charge to an adjacent pixel at a high level can be provided.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

(Pixel circuit configuration)
FIG. 1 is an equivalent circuit diagram of one pixel in an imaging device (MOS type imaging device) according to a preferred embodiment of the present invention. Note that the pixels constituting the imaging device are not limited to the example shown in FIG. 1 and may have various configurations.

  A pixel 10 illustrated in FIG. 1 includes a photodiode (photoelectric conversion unit) 100, a transfer transistor 101, a reset transistor 102, an amplification transistor 103, a selection transistor 104, a power supply line Vcc, and an output line 106. A plurality of pixels 10 are arranged in a matrix in the imaging area of the imaging device.

  The photodiode 100 has an anode connected to the ground line and a cathode connected to the source of the transfer transistor 101. The source of the transfer transistor can also serve as the cathode of the photodiode. The drain of the transfer transistor 101 forms a floating diffusion (transfer region) FD, and its gate 101g is connected to the transfer signal line. The reset transistor 102 has a drain connected to the power supply line Vcc, a source constituting the floating diffusion FD, and a gate 102g connected to the reset signal line. The amplification transistor 103 has its drain connected to the power supply line Vcc, its source connected to the drain of the selection transistor 104, and its gate 103g connected to the floating diffusion FD. The selection transistor 104 has its drain connected to the source of the amplification transistor 103, its source connected to the output line 106, and its gate 104g connected to a vertical selection line driven by a vertical selection circuit (not shown). .

(First embodiment)
FIG. 2 is a cross-sectional view showing a part of an imaging region in the imaging apparatus according to the first embodiment of the present invention. FIG. 2 shows a photodiode 100 and a transfer transistor 101 for two pixels. The reset transistor 102, the amplification transistor 103, and the selection transistor 104 constituting the pixel 10 can be disposed on the front side or the back side in FIG. Here, two pixels 10 will be described as a first pixel 12 and a second pixel 14.

  In FIG. 2, 301 is an n-type (first conductivity type) silicon substrate, 302 is an n-type semiconductor region, 309 is a buried p-type (second conductivity type) semiconductor region, and 303 is a gate electrode of a transfer transistor (MOS transistor) 101. (Transfer electrode). The n-type semiconductor region 302 may be formed by epitaxial growth on the n-type silicon substrate 301 or may be formed as a well by implanting ions into the n-type substrate.

  Reference numeral 304 denotes an n-type storage region for storing signal charges, and reference numeral 305 denotes a surface p-type region. Reference numerals 302 and 304 denote semiconductor regions having the same conductivity type as the signal charge, and are regions having a low potential with respect to the signal charge electrons. Therefore, the electric charge moves in these regions and is finally stored in the semiconductor region 304. The photodiode 100 can be configured by the buried p-type semiconductor region 309 and the n-type semiconductor region 302. In the embodiment shown in FIG. 2, the photodiode 100 includes an n-type accumulation region 304 that collects and accumulates electrons generated in the n-type semiconductor region 302, and a surface p-type region 305 for embedding the photodiode 100. But they are not necessary. The n-type accumulation region 304 contributes to efficiently collecting charges generated by photoelectric conversion in the photodiode 100. The surface p-type region 305 contributes to reduction of dark current.

  306 is an element isolation region (LOCOS oxide film) for element isolation, 307 is a high-concentration n-type semiconductor region that forms a floating diffusion (transfer region) FD to which charges are transferred from the signal charge storage region 304, and 308 is a transfer A gate insulating film of the transistor 101.

  Note that here, the substrate 301 which is a material substrate is expressed as a “substrate”, but such a material substrate is processed, for example, a member in a state where one or a plurality of semiconductor regions or the like are formed, or A member that is in the middle of a series of manufacturing steps or a member that has undergone a series of manufacturing steps can also be called a substrate.

  The charges generated in the photodiode 100 are accumulated in the n-type accumulation region 304 and transferred to the floating diffusion (FD) 307 through a channel formed under the transfer electrode 303. Reference numeral 312 denotes a channel stop region formed under the element isolation region (LOCOS oxide film) 306. 310 (310a, 310b, 310c) is a p-type isolation region (p-type potential barrier region) that is disposed between adjacent pixels to form a potential barrier, and is formed at different depths by a plurality of ion implantation steps. The plurality of barrier regions 310a, 310b, and 310c. This makes it possible to reduce leakage to adjacent pixels at a high level. In this embodiment, the p-type isolation region 310 is arranged such that the n-type semiconductor region 302 is interposed between the upper end of the p-type isolation region 310 and the lower end of the channel stopper region 312.

  The p-type isolation region 310 that forms the potential barrier is between the floating diffusion (FD) 307 of the first pixel 12 and the photodiode 100 (the buried p-type semiconductor region 309 and the n-type semiconductor region 302) of the second pixel 14. The device is disposed below the device isolation region 306 and the channel stop region 312. Since the structure for two pixels shown in FIG. 2 is repeatedly arranged, the p-type isolation region 310 includes, for example, the floating diffusion (FD) of the left pixel (not shown) of the first pixel 12 and the first pixel 12. It is also disposed under the element isolation region 306 and the channel stop region 312 disposed between the photodiode 100 (the buried p-type semiconductor region 309 and the n-type semiconductor region 302).

  From another point of view, the p-type isolation region 310 is formed by performing multiple times of ion implantation at different depths, and includes a photodiode 100 and a floating diffusion (FD) 307. , The device is disposed below the element isolation region 306 and the channel stop region 312 that are disposed so as to surround at least a part (preferably the entire circumference) of the pixel region including the photodiode 100 and the floating diffusion (FD) 307. Surrounding at least a part of the pixel region.

  According to such a configuration, since the influence of the p-type isolation region 310 on the operating conditions of the transfer transistor 101 (transfer gate 303) and the depletion region of the photodiode 100 is small, the concentration design of the p-type isolation region 310 is free. The degree is improved. On the other hand, in the structures described in Patent Documents 1 and 2, since the isolation region or the channel stop region is arranged below the transfer gate, they affect the channel of the transfer transistor and the depletion region of the photodiode. In the structure described in Patent Document 3, it is difficult to form a sufficient potential barrier.

  Below the transfer gate 303, typically, an n-type semiconductor region 302 constituting a part of the photodiode 100 extends.

  The p-type isolation region 310 can be configured to extend downward from the lower end of the channel stop region 312 and penetrate the high-concentration buried p-type semiconductor region 309.

  FIG. 3 is a diagram showing the impurity concentration distribution in the structure shown in FIG. 2, where the solid line is the impurity concentration distribution of the p-type isolation region 310 in BB ′ of FIG. 2, and the broken line is the impurity concentration of the photodiode in AA ′ of FIG. Distribution is shown. 4 is a diagram showing the acceptor concentration distribution in the structure shown in FIG. 2. The solid line is the acceptor concentration distribution of the p-type isolation region 310 in BB ′ of FIG. 2, and the broken line is the acceptor concentration of the photodiode in AA ′ of FIG. Distribution is shown. FIG. 5 is a diagram showing an acceptor concentration distribution in CC ′ of FIG.

  3 and 4, the p-type isolation region 310 can be formed by overlapping a plurality of p-type isolation regions (barrier regions) 310a, 310b, 310c in the vertical direction (depth direction). Here, it is preferable that the p-type isolation regions 310a, 310b, and 310c have a higher p-type impurity concentration as they are formed deeper. According to such an impurity distribution, the outflow of signal charges (electrons) to the substrate 301 side can be reduced.

  As exemplarily shown in FIGS. 3 and 4, the impurity concentration in BB ′ may be higher than the impurity concentration in AA ′ at the depth α at which the concentration of the high-concentration buried p-type semiconductor region 309 becomes the maximum value. preferable. For example, at the depth α, it is preferable that the impurity concentration in BB ′ has a value of three times or more the impurity concentration in AA ′.

  According to such an impurity concentration distribution, the potential generated by the isolation region 310 is that electrons generated in the vicinity of the concentration peak of the p-type semiconductor region 309 leak into the adjacent pixels along the potential gradient of the p-type semiconductor region 309. Suppressed by barriers. In order to more effectively suppress electrons from leaking into adjacent pixels, the p-type isolation region 310 preferably penetrates the high-concentration buried p-type semiconductor region 309.

  In the impurity concentration distributions illustrated in FIGS. 3 and 4, both the impurity concentration distribution at AA ′ and the impurity concentration distribution at BB ′ have maximum values at or near the depth α. However, as illustrated in FIG. 6, the p-type isolation region 310 may have a maximum value at a position deeper than the depth α. Here, FIG. 6 is a diagram showing the acceptor concentration distribution in the structure shown in FIG. 2, the solid line is the acceptor concentration distribution of the p-type isolation region 310 in BB ′ of FIG. 2, and the broken line is the photodiode in AA ′ of FIG. The acceptor concentration distribution is shown. FIG. 7 is a diagram showing an acceptor concentration distribution in CC ′ of FIG. 2 corresponding to FIG.

  As described above, it is preferable that the impurity concentration in BB ′ has a value not less than three times the impurity concentration in AA ′ at the depth α at which the concentration of the buried p-type semiconductor region 309 becomes the maximum value. Further, at other depths, it is preferable that the impurity concentration of the p-type isolation region 310 in BB ′ has a value of three times or more the p-type impurity concentration in AA ′.

(Second Embodiment)
FIG. 8 is a cross-sectional view showing a part of the imaging region of the imaging apparatus according to the second embodiment of the present invention. FIG. 8 shows a photodiode 100 and a transfer transistor 101 for two pixels. The reset transistor 102, the amplification transistor 103, and the selection transistor 104 constituting the pixel 10 can be arranged on the front side or the back side in FIG. Here, two pixels 10 will be described as a first pixel 12 and a second pixel 14.

  In FIG. 8, 401 is an n-type (first conductivity type) silicon substrate, 402 is an n-type semiconductor region, 409 is a buried p-type (second conductivity type) semiconductor region, and 403 is a gate electrode of a transfer transistor (MOS transistor) 101. (Transfer electrode). The n-type semiconductor region 402 may be formed on the n-type silicon substrate 401 by epitaxial growth, or may be formed as a well by implanting ions into the substrate.

  Reference numeral 404 denotes an n-type accumulation region, and reference numeral 405 denotes a surface p-type region. The photodiode 100 can be configured by the buried p-type semiconductor region 409 and the n-type semiconductor region 402. In the embodiment shown in FIG. 8, the photodiode 100 includes an n-type accumulation region 404 that collects and accumulates electrons generated in the n-type semiconductor region 402, and a surface p-type region 405 for making the photodiode 100 an embedded structure. But they are not necessary. The n-type accumulation region 404 contributes to efficiently collecting charges generated by photoelectric conversion in the photodiode 100. The surface p-type region 405 contributes to reduction of dark current.

  406 is an element isolation region (LOCOS oxide film) for element isolation, 407 is a high-concentration n-type semiconductor region that forms a floating diffusion (transfer region) FD to which charges are transferred from the signal charge storage region 404, and 408 is a transfer. A gate insulating film of the transistor 101.

  Note that here, the substrate 401 which is a material substrate is expressed as a “substrate”, but such a material substrate is processed, for example, a member in a state where one or a plurality of semiconductor regions or the like are formed, or A member that is in the middle of a series of manufacturing steps or a member that has undergone a series of manufacturing steps can also be called a substrate.

  The electric charge generated in the photodiode 100 is accumulated in the n-type accumulation region 404 and transferred to the floating diffusion (FD) 407 through a channel formed under the transfer electrode 403. Reference numeral 412 denotes a channel stop region formed under the element isolation region (LOCOS oxide film) 406. 410 (410a, 410b, 410c, 410d) is a p-type isolation region (p-type potential barrier region) that is disposed between adjacent pixels and forms a potential barrier. In this embodiment, the p-type isolation region 410 is disposed such that the upper end of the p-type isolation region 410 is in contact with the lower end of the channel stopper region 412.

  The p-type isolation region 410 forming the potential barrier is between the floating diffusion (FD) 407 of the first pixel 12 and the photodiode 100 (the embedded p-type semiconductor region 409 and the n-type semiconductor region 402) of the second pixel 14. The device isolation region 406 and the channel stop region 412 are disposed below the device isolation region 406 and the channel stop region 412. The p-type isolation region 410 is formed by performing multiple times of ion implantation at different depths. Since the structure for two pixels shown in FIG. 8 is repeatedly arranged, the p-type isolation region 410 includes, for example, the floating diffusion (FD) of the left pixel (not shown) of the first pixel 12 and the first pixel 12. It is also disposed under the element isolation region 406 and the channel stop region 412 disposed between the photodiode 100 (the buried p-type semiconductor region 409 and the n-type semiconductor region 402).

  From another point of view, the p-type isolation region 410 is formed by performing a plurality of ion implantations at different depths, and includes a photodiode 100 and a floating diffusion (FD) 407. 2, the device is disposed under the element isolation region 406 and the channel stop region 412 disposed so as to surround at least a part (preferably, the entire circumference) of the pixel region including the photodiode 100 and the floating diffusion (FD) 407. Surrounding at least a part of the pixel region.

  According to such a configuration, the influence of the p-type isolation region 410 on the operating conditions of the transfer transistor 101 (transfer gate 403) and the depletion region of the photodiode 100 is small. The degree is improved.

  Below the transfer gate 403, typically, an n-type semiconductor region 402 constituting a part of the photodiode 100 extends.

  The p-type isolation region 410 can be configured to extend downward from the lower end of the channel stop region 312 and penetrate the high-concentration buried p-type semiconductor region 409.

  9 is a diagram showing the impurity concentration distribution in the structure shown in FIG. 8, where the solid line is the impurity concentration distribution of the p-type isolation region 410 in BB ′ of FIG. 8, and the broken line is the impurity concentration of the photodiode in AA ′ of FIG. Distribution is shown. 10 is a diagram showing the acceptor concentration distribution in the structure shown in FIG. 8. The solid line is the acceptor concentration distribution of the p-type isolation region 410 in BB ′ of FIG. 8, and the broken line is the acceptor concentration of the photodiode in AA ′ of FIG. Distribution is shown. FIG. 11 is a diagram showing an acceptor concentration distribution in CC ′ of FIG.

  As illustrated in FIGS. 8 to 10, the p-type isolation region 410 is preferably disposed so as to completely connect the channel stop region 412 and the p-type semiconductor region 409. According to such a configuration, signal charges (electrons) pass between the first pixel 12 and the second pixel 14 through the region between the channel stopper region 412 and the high-concentration p-type semiconductor region 409, that is, The probability of moving between adjacent pixels is reduced.

The p-type isolation region 410 is formed by overlapping a plurality of p-type isolation regions (barrier regions) 410a, 410b, 410c, 410d in the vertical direction (depth direction). Here, it is preferable that the plurality of p-type isolation regions 410a, 410b, 410c, and 410d have a higher p-type impurity concentration as they are formed deeper. According to such an impurity concentration distribution, the outflow of signal charges (electrons) to the substrate 401 side can be reduced. The plurality of p-type isolation regions 410a, 410b, 410c, and 410d have a higher p-type impurity concentration, for example, as they are formed deeper in a range of 1 × 10 ¹¹ to 1 × 10 ¹⁵ [/ cm ³ ]. Is preferred.

  As illustrated in FIGS. 9 and 10, it is preferable that the impurity concentration in BB ′ is higher than the impurity concentration in AA ′ at a depth where the concentration of the high-concentration buried p-type semiconductor region 409 becomes a maximum value. . For example, at the depth α, it is preferable that the impurity concentration in BB ′ has a value of three times or more the impurity concentration in AA ′.

  According to such an impurity concentration distribution, electrons generated in the vicinity of the concentration peak of the p-type semiconductor region 409 leak into the adjacent pixels along the potential gradient of the p-type semiconductor region 409. It is suppressed by the potential barrier that forms. In order to more effectively suppress electrons from leaking into adjacent pixels, it is preferable that the p-type isolation region 410 penetrates the buried p-type semiconductor region 409.

  As described above, according to this embodiment, the signal charges (electrons) move between the pixels through the semiconductor region 402, and the signal charges (electrons) between the pixels by connecting the potential gradient of the p-type semiconductor region 409. Is prevented by the p-type isolation region 410.

(Third embodiment)
FIG. 12 is a cross-sectional view illustrating a part of the imaging region of the imaging apparatus according to the third embodiment of the present invention. FIG. 12 shows a photodiode 100 and a transfer transistor 101 for two pixels. The reset transistor 102, the amplification transistor 103, and the selection transistor 104 constituting the pixel 10 can be disposed on the front side or the back side in FIG. Here, two pixels 10 will be described as a first pixel 12 and a second pixel 14.

  In FIG. 12, 501 is an n-type (first conductivity type) silicon substrate, 502 is an n-type semiconductor region, 509 is a buried p-type (second conductivity type) semiconductor region, and 503 is a gate electrode (MOS transistor) of a transfer transistor (MOS transistor). Transfer electrode). The n-type semiconductor region 502 may be formed by epitaxial growth on the n-type silicon substrate 501 or may be formed as a well by implanting ions into the n-type substrate.

  Reference numeral 504 denotes an n-type accumulation region, and 505 denotes a surface p-type region. The photodiode 100 can be configured by the buried p-type semiconductor region 509 and the n-type semiconductor region 502. In the embodiment shown in FIG. 12, the photodiode 100 includes a buried n-type accumulation region 504 that collects and accumulates electrons generated in the n-type semiconductor region 502, and a surface p-type region 505 for making the photodiode 100 have a buried structure. These are not necessarily required. The n-type accumulation region 504 contributes to efficiently collecting charges generated by photoelectric conversion in the photodiode 100. The surface p-type region 505 contributes to reduction of dark current.

  506 is an element isolation region (LOCOS oxide film) for element isolation, 507 is a high-concentration n-type semiconductor region that forms a floating diffusion (transfer region) FD to which charges are transferred from the signal charge storage region 504, and 508 is a transfer A gate insulating film of the transistor 101.

  Note that here, the substrate 501 that is a material substrate is expressed as a “substrate”. However, such a material substrate is processed, for example, a member in a state where one or a plurality of semiconductor regions and the like are formed, or A member that is in the middle of a series of manufacturing steps or a member that has undergone a series of manufacturing steps can also be called a substrate.

  The charges generated in the photodiode 100 are accumulated in the n-type accumulation region 504 and transferred to the floating diffusion (FD) 507 through a channel formed under the transfer electrode 503. Reference numeral 512 denotes a channel stop region formed under the element isolation region (LOCOS oxide film) 506. 510 (510a, 510b, 510c, 510d) is a p-type isolation region (p-type potential barrier region) that is disposed between adjacent pixels and forms a potential barrier. In this embodiment, in the p-type isolation region 510, the upper end of the p-type isolation region 510 is in contact with the lower end of the channel stopper region 512, and the lower end of the p-type isolation region 510 is in contact with the high concentration buried p-type semiconductor region 509. Are arranged as follows.

  The p-type isolation region 510 forming the potential barrier is between the floating diffusion (FD) 507 of the first pixel 12 and the photodiode 100 (the buried p-type semiconductor region 509 and the n-type semiconductor region 502) of the second pixel 14. The device isolation region 506 and the channel stop region 512 are disposed below the device isolation region 506 and the channel stop region 512. The p-type isolation region 510 is formed by performing multiple times of ion implantation at different depths. Since the structure for two pixels shown in FIG. 12 is repeatedly arranged, the p-type isolation region 510 includes, for example, the floating diffusion (FD) of the left pixel (not shown) of the first pixel 12 and the first pixel 12. The photodiode 100 (the buried p-type semiconductor region 509 and the n-type semiconductor region 502) is also disposed under the element isolation region 506 and the channel stop region 512.

  From another point of view, the p-type isolation region 510 is formed by performing a plurality of ion implantations at different depths, and includes a photodiode 100 and a floating diffusion (FD) 507. , The device is disposed below the element isolation region 506 and the channel stop region 512 disposed so as to surround at least a part (preferably, the entire circumference) of the pixel region including the photodiode 100 and the floating diffusion (FD) 507. Surrounding at least a part of the pixel region.

  According to such a configuration, since the influence of the p-type isolation region 510 on the operating conditions of the transfer transistor 101 (transfer gate 503) and the depletion region of the photodiode 100 is small, the concentration design freedom of the p-type isolation region 510 is free. The degree is improved.

  Below the transfer gate 503, typically, an n-type semiconductor region 502 constituting a part of the photodiode 100 extends.

  13 is a diagram showing the impurity concentration distribution in the structure shown in FIG. 12, where the solid line is the impurity concentration distribution of the p-type isolation region 510 in BB ′ of FIG. 12, and the broken line is the impurity concentration of the photodiode in AA ′ of FIG. Distribution is shown. 14 is a diagram showing the acceptor concentration distribution in the structure shown in FIG. 12, where the solid line is the acceptor concentration distribution of the p-type isolation region 410 in BB ′ of FIG. 12, and the broken line is the acceptor concentration of the photodiode in AA ′ of FIG. Distribution is shown. FIG. 15 is a diagram showing an acceptor concentration distribution in CC ′ of FIG.

  As illustrated in FIGS. 12 to 15, the p-type isolation region 510 is preferably disposed so as to completely connect the channel stop region 512 and the p-type semiconductor region 509. According to such a configuration, signal charges (electrons) pass between the first pixel 12 and the second pixel 14 through the region between the channel stop region 512 and the p-type semiconductor region 509, that is, between adjacent pixels. Is prevented from moving by.

  The p-type isolation region 510 is formed by overlapping a plurality of p-type isolation regions 510a, 510b, 510c, and 510d in the vertical direction (depth direction).

The channel stop region 512, the p-type isolation regions 510a, 510b, 510c, 510d, the impurity (acceptor) concentration peak value D [/ cm ³ ] of the buried p-type semiconductor region 509, and the depth t [μm at the peak value. ] Are preferably determined within the following ranges, respectively.

(1) Channel stop (512)
0.25 ≦ t ≦ 0.35, 1.0 × 10 ¹³ ≦ D ≦ 1.0 × 10 ¹⁴
(2) p-type isolation region (510a)
1.0 ≦ t ≦ 1.4, 1.0 × 10 ¹¹ ≦ D ≦ 1.0 × 10 ¹²
(3) p-type isolation region (510b)
1.2 ≦ t ≦ 1.7, 1.0 × 10 ¹¹ ≦ D ≦ 1.0 × 10 ¹²
(4) p-type isolation region (510c)
1.6 ≦ t ≦ 2.0, 1.0 × 10 ¹² ≦ D ≦ 5.0 × 10 ¹²
(5) p-type isolation region (510d)
1.8 ≦ t ≦ 2.5, 1.0 × 10 ¹² ≦ D ≦ 1.0 × 10 ¹³
(6) High concentration buried p-type semiconductor region (509)
2.5 ≦ t ≦ 4.0, 1.0 × 10 ¹³ ≦ D ≦ 1.0 × 10 ¹⁴
The peak value of the impurity concentration in the p-type isolation regions 510a, 510b, 510c, and 510d preferably satisfies the relationship 510b <510a <510c <510d within the above range. According to such an impurity distribution, the outflow of signal charges (electrons) to the substrate 501 side can be reduced. In addition, by increasing the impurity concentration of the p-type isolation region 510d in contact with the high-concentration buried p-type semiconductor region 509 among the p-type isolation regions 510a, 510b, 510c, and 510d, near the concentration peak of the p-type semiconductor region 509. The electrons generated in (1) are prevented from leaking to adjacent pixels along the potential gradient of the p-type semiconductor region 509 by the potential barrier formed by the isolation region 510d.

(Application example to imaging system)
FIG. 16 is a diagram illustrating a configuration example of an imaging system (for example, a digital camera) in which an imaging apparatus according to the present invention represented by the first to third embodiments is incorporated. A shutter 1001 for controlling exposure (exposure time) is disposed at an appropriate position such as in front of the photographing lens (optical system) 1002. Exposure can also be controlled by the aperture 1003. The taking lens 1002 forms a subject image on the image pickup surface of the image pickup apparatus 1004 to which the present invention is applied. A signal output from the imaging device 1004 is processed by a signal processing circuit 1005 and converted from an analog signal to a digital signal by an A / D converter 1006. The digital signal is arithmetically processed by the signal processing unit 1007 and recorded in the memory unit 1010 or sent to an external device through the external I / F 1013. The imaging device 1004, the imaging signal processing circuit 1005, the A / D converter 1006, and the signal processing unit 1007 are controlled by a timing generation unit 1008. The entire system is controlled by an overall control unit / arithmetic unit 1009. The digital signal (digital image) processed by the signal processing unit 1007 is recorded on the recording medium 1012 by the recording medium control I / F unit 1011.

It is an equivalent circuit diagram of one pixel in the imaging device (MOS type imaging device) of a preferred embodiment of the present invention. It is sectional drawing which shows a part of imaging region in the imaging device of 1st Embodiment of this invention. It is a figure which shows the impurity concentration distribution in the structure shown in FIG. It is a figure which shows the acceptor density | concentration distribution in the structure shown in FIG. It is a figure which shows the acceptor density | concentration distribution in the structure shown in FIG. It is a figure which shows the other example of the acceptor density | concentration distribution in the structure shown in FIG. It is a figure which shows the other example of the acceptor density | concentration distribution in the structure shown in FIG. It is sectional drawing which shows a part of imaging region of the imaging device of 2nd Embodiment of this invention. It is a figure which shows the impurity concentration distribution in the structure shown in FIG. It is a figure which shows the acceptor density | concentration distribution in the structure shown in FIG. It is a figure which shows the acceptor density | concentration distribution in the structure shown in FIG. It is sectional drawing which shows a part of imaging region of the imaging device of 2nd Embodiment of this invention. It is a figure which shows the impurity concentration distribution in the structure shown in FIG. It is a figure which shows the acceptor density | concentration distribution in the structure shown in FIG. It is a figure which shows the acceptor density | concentration distribution in the structure shown in FIG. It is a figure which shows the structural example of the imaging system (for example, digital camera) in which the imaging device concerning this invention represented by the 1st-3rd embodiment was integrated.

Claims (11)

A semiconductor substrate;
A first conductivity type first semiconductor region having the same conductivity type as the signal charge formed on the semiconductor substrate, and a second conductivity type formed deeper in the semiconductor substrate than the first semiconductor region. A photoelectric conversion unit configured to include a second semiconductor region;
A transfer region to which charges generated by the photoelectric conversion unit are transferred;
An element isolation region surrounding a region including the photoelectric conversion unit and the transfer region;
A potential barrier region of a second conductivity type disposed below the element region and surrounding at least a part of the region together with the second semiconductor region;
The potential barrier region is composed of a plurality of barrier regions arranged at different depths;
An imaging apparatus characterized by that.   The imaging apparatus according to claim 1, wherein the first semiconductor region extends below the transfer region. A channel stop region is disposed under the element isolation region,
The potential barrier region is arranged to connect the channel stop region and the second semiconductor region with a semiconductor region of a second conductivity type;
The imaging apparatus according to claim 2.   The imaging apparatus according to claim 3, wherein the potential barrier region penetrates the second semiconductor region.   The imaging device according to claim 3, wherein the barrier region disposed at the deepest position of the potential barrier region has the highest impurity concentration. An imaging device having first and second pixels formed on a semiconductor substrate,
Each of the first and second pixels has a first conductivity type first semiconductor region having the same conductivity type as a signal charge, and a first region formed deeper in the semiconductor substrate than the first semiconductor region. A photoelectric conversion unit configured to include a second semiconductor region of two conductivity type, and a transfer region to which charges generated by the photoelectric conversion unit are transferred,
The imaging device
An element isolation region disposed between the transfer region of the first pixel and the photoelectric conversion unit of the second pixel;
A potential barrier region disposed below the element isolation region,
The potential barrier region is composed of a plurality of barrier regions arranged at different depths;
An imaging apparatus characterized by that.   The imaging apparatus according to claim 6, wherein the first semiconductor region extends below the transfer region. The second semiconductor region is disposed under the first semiconductor region;
A channel stop region is disposed under the element isolation region,
The potential barrier region is arranged to connect the channel stop region and the second semiconductor region with a semiconductor region of a second conductivity type;
The imaging apparatus according to claim 7.   The imaging device according to claim 8, wherein the potential barrier region penetrates the second semiconductor region.   10. The imaging device according to claim 8, wherein the barrier region disposed at a deepest position of the potential barrier region has the highest impurity concentration. The imaging device according to any one of claims 1 to 10,
An optical system for forming an image on an imaging surface of the imaging device;
A signal processing circuit for processing a signal output from the imaging device;
An imaging system comprising:

Images