JP2006304019A - Image processing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image processing device capable of outputting a high quality image signal even though band width of an external memory is to be limited in the image processing device for outputting after synthesizing a main image signal and the other image signals. <P>SOLUTION: A first image processing means 102 for applying an IP conversion process to the main image signal has a motion adaptive IP conversion processing function and an in-field interpolation IP conversion processing function, and a signal process controlling means 109 is designed to switch a process function of the first image signal processing means 102 in response to combination of display of the main image signal and the other image signals based on image signal combination setting information 108, to control data transfer from a storing means (external memory) 101, to apply an in-field interpolation IP conversion process to the main image signal of a line where the main image signal and the other image signals being superposed, and to apply a motion adaptive IP conversion process to the main image signal of the line where only the main image signal is to be outputted. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention provides a main video signal including information such as moving images and still images, a sub video signal (sub picture data) including information such as subtitles, and an OSD (ON Screen Display) including information such as menus and title screens. The present invention relates to a video processing apparatus that generates a video signal for combining and displaying a plurality of different video signals such as data.

  In recent years, with the spread of progressive television and the like, the function of converting interlace signals into progressive signals (IP conversion processing) has become essential in televisions and DVD players. In addition, there is a need for higher image quality. Correspondingly, as a method for realizing higher image quality of IP conversion processing, motion adaptive IP conversion processing using temporal correlation (frame correlation) is available. Proposed.

Hereinafter, a conventional IP conversion processing circuit that performs motion adaptive IP conversion processing using frame correlation of video signals will be described.
FIG. 10 is a block diagram showing a configuration of a conventional IP conversion processing circuit.

  In FIG. 10, reference numeral 1001 denotes a field memory that delays the video signal by 262 lines, 1002 denotes a field memory that delays the video signal by 263 lines, and 1003 denotes a line memory that delays the video signal by one line.

  The field memory 1001 delays a video signal (interlace signal) transferred from an external memory (not shown) by 262 lines. The field memory 1002 delays the video signal delayed by 262 lines by the field memory 1001 by 263 lines. The line memory 1003 delays the video signal delayed by 262 lines by the field memory 1001 by one line.

  Reference numerals 1004 and 1005 denote adders. The adder 1004 adds the video signal delayed by 262 lines by the field memory 1001 and the video signal delayed by one line by the line memory 1003 (that is, the video signal delayed by 263 lines). The adder 1005 adds a video signal (video signal one frame before) delayed by 525 lines by the field memories 1001 and 1002 and a video signal transferred from an external memory (not shown).

  Reference numeral 1006 denotes a motion detection circuit. The motion detection circuit 1006 receives a video signal transferred from an external memory (not shown) and a video signal delayed by 525 lines by the field memories 1001 and 1002 (video signal one frame before), and the pixel and 525 lines (1) Frame) It is determined whether or not the image is moving by taking the difference of the previous pixel.

  Reference numeral 1007 denotes a field memory for delaying the video signal by 262 lines or 263 lines. Reference numeral 1008 denotes a determination unit. The field memory 1007 delays the output from the motion detection circuit 1006 by 262 lines or 263 lines, and the determination unit 1008 detects a specific pattern based on the outputs of the motion detection circuit 1006 and the field memory 1007.

  Reference numeral 1009 denotes a mixing circuit. The mixing circuit 1009 selects or mixes the signals from the adders 1004 and 1005 based on the result of the determination unit 1008. Reference numerals 1010 and 1011 denote time compression circuits. The time compression circuit 1010 outputs the video signal input from the mixing circuit 1009 in half the time of the input horizontal synchronization, and the time compression circuit 1011 outputs the video signal input from the line buffer 1003 to a time half of the input horizontal synchronization. To output. Reference numeral 1012 denotes a selector. The selector 1012 converts the outputs of the time compression circuits 1010 and 1011 alternately into sequential scanning signals (pregressive signals).

  As described above, in order to realize the motion adaptive IP conversion processing, data transfer of a plurality of fields from the external memory to the IP conversion processing circuit is required (see, for example, Patent Document 1). However, in recent years, the system LSI has been made into one chip, and various functions are required. On the other hand, there has been a demand for a lower price of the system, and the bandwidth of the external memory of the system LSI has been restricted.

  Therefore, when a motion adaptive IP conversion process that requires data transfer of a plurality of fields is adopted in a video processing device that synthesizes a main video signal and a plurality of other video signals, the main video signal and other video signals are stored in an external memory. Since multiple video signals are held and data is transferred from this external memory to a circuit that performs IP conversion processing on the main video signal and a circuit that performs video processing on video signals other than the main video signal, the bandwidth is limited. As a result, all data transfer performance is guaranteed, such as the transfer of video signals other than the main video signal to be combined makes it impossible to guarantee the amount of data transfer per unit time required to perform motion-adaptive IP conversion processing. There was a problem that it was impossible.

Therefore, conventionally, inter-field interpolation IP conversion processing that performs IP conversion processing in a single field is adopted, and data transfer performance is guaranteed by reducing the data transfer amount per unit time required for IP conversion processing. There is a problem that the image quality is inferior when compared with a video signal generated by the motion adaptive IP conversion processing.
JP 2000-175195 A

  In view of the above problems, the present invention outputs a main video signal subjected to motion adaptive IP conversion processing for lines on which only the main video signal is displayed, and sub-picture data, OSD data, etc. in front of the main video signal. For a line on which a video signal other than the main video signal is superimposed, the main video signal subjected to the intra-field interpolation IP conversion process is output, or only the video signal other than the main video signal is output, so that the external memory An object of the present invention is to provide a video processing apparatus capable of outputting a high-quality main video signal for a line on which only the main video signal is displayed even when the bandwidth is limited.

  The video processing device according to claim 1 of the present invention is a video processing device that generates a video signal for selectively displaying or blending a plurality of different types of video signals, and the plurality of different types of video signals. A storage means for storing a video signal; and a first video signal having a plurality of types of video processing functions and inputting a main video signal among the plurality of different video signals stored in the storage means to perform video processing. The video signal processing means and a video signal other than the main video signal stored in the storage means are input, and video processing is performed with processing contents corresponding to the display combinations of the plurality of different video signals. 2 video signal processing means, video output means for outputting video by combining the output from the first video signal processing means and the output from the second video signal processing means, the storage means, and the first Video Transfer control means for controlling data transfer between the signal processing means and the second video signal processing means, video signal combination setting means for setting a display combination of the plurality of different types of video signals, and the video Based on the display combination set by the signal combination setting means, the processing content determination means for determining the processing content of the video processing by the second video signal processing means, and the processing content determined by the processing content determination means. A data transfer amount per unit time between the storage unit and the second video signal processing unit is obtained, and a method of a video processing function by the first video signal processing unit is switched according to the data transfer amount. In addition, the data transfer between the storage means and the first video signal processing means with a data transfer amount per unit time according to the switched video processing function. Transfer is characterized by comprising a signal processing control means for controlling said transfer control means to be performed.

  According to a second aspect of the present invention, there is provided a video processing apparatus for generating a video signal for selectively displaying or blending a plurality of different types of video signals, wherein the different types are used. Storage means for storing a plurality of video signals and video processing functions of a plurality of systems are inputted and main video signals of the plurality of different types of video signals stored in the storage means are inputted and processed. Input a video signal other than the main video signal stored in the first video signal processing means and the storage means, and perform video processing with processing contents corresponding to a combination of display of the plurality of different video signals Second video signal processing means, video output means for outputting video by combining the output from the first video signal processing means and the output from the second video signal processing means, the storage means and the first 1 Controls data transfer between the video signal processing means and the second video signal processing means, and notifies the data transfer status between the storage means and the second video signal processing means every unit time. Transfer control means, video signal combination setting means for setting a display combination of a plurality of different types of video signals, and the second video signal processing based on the display combination set by the video signal combination setting means The processing content determining means for determining the processing content of the video processing by the means, and switching the video processing function system by the first video signal processing means based on the notification from the transfer control means, and the switched video processing Data transfer between the storage means and the first video signal processing means is performed at a data transfer amount per unit time according to the function. Characterized by comprising a signal processing control means for controlling said transfer control means.

  The video processing device according to claim 3 of the present invention is the video processing device according to claim 1, wherein the main video signal is an interlace signal, and the first video signal processing means is The signal processing control means having a video processing function of a filter processing system for performing interlace / progressive conversion from a multi-field interlace signal and a video processing function of a filter processing system for performing interlace / progressive conversion from a single field interlaced signal. The video processing function of the first video signal processing means can be switched on a line-by-line basis.

  According to the present invention, the video processing method for the main video signal is switched according to the display combination of the video signal, and motion adaptive IP conversion processing is performed on the line where the data transfer amount of the video signal other than the main video signal is small. The main video signal can be output, and even when the bandwidth of the external memory is limited, a high-quality main video signal can be output.

  Furthermore, according to the invention described in claim 2, the data transfer amount of the video signal other than the main video signal is measured every unit time, and the video processing method for the main video signal is adaptively switched according to the measurement result. Therefore, it is not necessary to store a combination of data transfer amounts determined in advance by the system.

  Hereinafter, a video processing apparatus according to an embodiment of the present invention will be described with reference to the drawings. The video processing apparatus includes a main video signal including information such as moving images and still images, a sub video signal including subtitle information (sub-picture data), OSD data including information such as a menu and a title screen, and the like. A device for generating a video signal for displaying a plurality of different types of video signals selectively or blended and combined, and a device for displaying video signals and sub-video signals recorded on a disk medium such as a DVD In addition, it is used for television signal reception display devices such as digital broadcasting and terrestrial broadcasting.

(Embodiment 1)
FIG. 1 is a diagram showing the configuration of the video processing apparatus according to the first embodiment.
In FIG. 1, reference numeral 101 denotes storage means. The storage means 101 stores a main video signal and video signals other than the main video signal as a plurality of different types of video signals.

  Specifically, the storage unit 101 is realized as an external memory of a system LSI using, for example, a frame memory, stores a multi-field interlace signal as a main video signal, and multi-plane OSD data as a video signal other than the main video signal And sub-picture data.

  Reference numeral 102 denotes first video signal processing means. The first video signal processing unit 102 has a plurality of types of video processing functions, and performs video processing on the main video signal transferred from the storage unit 101. Here, as a plurality of video processing functions, a motion adaptive IP conversion process and an intra-field interpolation IP conversion process are included.

  Specifically, the first video signal processing means 102 has a plurality of line buffers therein, inputs line data of the main video signal (interlace signal) transferred from the storage means 101, and is a motion adaptive type. IP conversion processing or intra-field interpolation IP conversion processing is performed to generate interpolation line data, and line data and interpolation line data of the main video signal transferred from the storage means 101 are alternately output.

  Reference numeral 103 denotes second video signal processing means. The second video signal processing unit 103 performs video processing with processing contents corresponding to a combination of display of a plurality of different types of video signals on video signals other than the main video signal transferred from the storage unit 101.

  Reference numeral 104 denotes a video output means. The video output means 104 receives the output from the first video signal processing means 102 and the output from the second video signal processing means 103 as input, and based on the priority of selection included in the video signal or the weight for blend display. The main video signal subjected to the IP conversion process and the other video signal are output in combination.

  Reference numeral 105 denotes a transfer control means. The transfer control unit 105 controls data transfer from the storage unit 101 to the first video signal processing unit 102 and the second video signal processing unit 103 in accordance with transfer control information described later. Reference numeral 106 denotes an internal bus. The internal bus 106 interconnects the transfer control means 105 with the first video signal processing means 102 and the second video signal processing means 103.

  Reference numeral 107 denotes a video signal combination setting unit. The video signal combination setting unit 107 generates the video signal combination setting information 108 based on the video signal display combination arbitrarily set by the user.

  Here, the content of the video signal combination setting information depends on a predetermined degree of freedom of setting. For example, when only the output position (display position) of the OSD data can be set, the video signal combination setting information is only the information of the output line of the OSD data. In addition, the degree of freedom can be increased so that, for example, the output position of the main video signal and other video signals, the size of the video, the blend ratio (weight of blend display), the priority of selection, etc. can be set. Good.

  Reference numeral 109 denotes a signal processing control means. The signal processing control unit 109 generates processing content control information 111, processing method control information 112, and transfer control information 113 based on the video signal combination setting information 108 to generate the first video signal processing unit 102 and the second video signal. The data is output to the processing unit 103 and the transfer control unit 105.

  That is, the signal processing control unit 109 includes a processing content determination unit 110 that determines the processing content of the video processing by the second video signal processing unit 103 in accordance with the display combination of the video signals. Processing content control information 111 is generated by the determination unit 110.

  Then, the signal processing control unit 109 obtains the data transfer amount per unit time of the video signal other than the main video signal necessary for the video processing of the processing content determined by the processing content determination unit 110, and obtains the processing method control information 112. And the processing method of the IP conversion processing by the first video signal processing means 102 is switched according to the data transfer amount. Further, the signal processing control unit 109 performs transfer control so that data transfer between the storage unit 101 and the first video signal processing unit is performed at a data transfer amount per unit time necessary for the switched IP conversion processing. Information 113 is generated.

  Specifically, the signal processing control means 109 has a data amount necessary for video processing of one line of a video signal other than the main video signal determined by the processing content of the second video signal processing means 103, and a motion adaptive type. Data transfer amount of main video signal per unit time required for performing IP conversion processing and intra-field interpolation IP conversion processing, and data amount transferred from storage means 101 per unit time determined by the bandwidth of storage means 101 Is stored in advance, the amount of data transferred per unit time of a video signal other than the main video signal is determined from the determined processing content, and the data necessary for performing motion adaptive IP conversion processing on the main video signal It is determined whether or not the amount can be transferred per unit time. If transfer is possible, switching to motion adaptive IP conversion processing is performed, and if transfer is not possible, intra-field interpolation IP conversion processing is performed. Replace Ri.

  The signal processing control unit 109 also transfers the data transfer amount per unit time based on the processing content of the video processing by the second video signal processing unit 103 and the processing method of the IP conversion processing by the first video signal processing unit 102. Are determined, and transfer control information 113 is generated.

  As described above, the signal processing control unit 109 according to the first embodiment stores a combination of data transfer amounts determined in advance by the system of the video processing apparatus, and processes content control information 111 and processing method control information 112. The transfer control information 113 is generated.

  FIG. 2 is a diagram showing an example of the configuration of the first video signal processing means. Here, a case will be described in which motion adaptive IP conversion processing is performed using main video signals (interlace signals) of three consecutive fields. Hereinafter, n is a natural number.

  In FIG. 2, 201 indicates line data of the (n−1) -th field of the main video signal transferred from the storage unit 101. Reference numeral 202 denotes line data of the nth field of the main video signal transferred from the storage unit 101. Reference numeral 203 denotes line data of the (n + 1) -th field of the main video signal transferred from the storage unit 101.

  Reference numeral 204 denotes an (n−1) th line buffer memory for storing line data 201 of the (n−1) th field of the main video signal. Reference numeral 205 denotes an nth line buffer memory for storing the nth field line data 202 of the main video signal. Reference numeral 206 denotes an (n + 1) -th line buffer memory for storing line data 203 of the (n + 1) -th field of the main video signal.

  Reference numeral 207 denotes IP conversion processing means. The IP conversion processing means 207 executes motion adaptive IP conversion processing or intra-field interpolation IP conversion processing in accordance with the processing method control information 112. Specifically, when the motion adaptive IP conversion process is performed, the line of the main video signal stored in the (n−1) th line buffer memory 204, the nth line buffer memory 205, and the (n + 1) th line buffer memory 206 is stored. Data is input to generate interpolation line data, and the nth field line data and interpolation line data are alternately output. On the other hand, when performing the intra-field interpolation IP conversion processing, the line data of the main video signal stored in the n-th line buffer memory 205 is input to generate the interpolation line data, and the line data and the interpolation line data of the n-th field are generated. Output alternately.

  As described above, the first video signal processing means 102 includes a filter processing type video processing function (motion adaptive IP conversion processing) for performing interlace / progressive conversion (IP conversion) using interlace signals of a plurality of fields, It has a filter processing method video processing function (intra-field interpolation IP conversion processing) that performs interlace / progressive conversion (IP conversion) using field interlaced signals. Output a signal.

Next, the data transfer timing of the IP conversion process in the first embodiment will be described with reference to FIG.
The left diagram of FIG. 3 is a schematic diagram in the case where motion adaptive IP conversion processing is performed using video signals (interlace signals) of three consecutive fields. In the left figure, a1 to a5 indicate line data of the (n-1) th field, b1 to b6 indicate line data of the nth field, and c1 to c5 indicate line data of the (n + 1) field. B1 'to b5' indicate interpolation line data. Specifically, b1 ′ is interpolation line data between lines b1 and b2, b2 ′ is interpolation line data between lines b2 and b3,..., B5 ′ is interpolation line data between lines b5 and b6. It is.

  The first video signal processing means 102 alternately outputs the nth field line data and its interpolation line data in the order of b2 → b2 ′ → b3 → b3 ′ → b4 for each line period (unit time). .

  Here, in order to perform the motion adaptive IP conversion processing in real time, line data of three consecutive fields is used to generate one interpolation line data, so, for example, two lines b2 and b2 ′ are output. It is necessary to transfer the data for three lines a2, b3, and c2 from the storage means 101 to each line buffer memory during the period to generate the interpolation line data b3 ′.

  On the other hand, the right figure is a schematic diagram in the case of performing intra-field interpolation IP conversion processing with only a single field. In the right figure, b1 to b6 indicate line data of the nth field, and b1 ′ to b5 ′ indicate interpolation line data.

  Here, in order to perform intra-field interpolation IP conversion processing in real time, only single-line line data is used to generate one interpolated line data. For example, two lines b2 and b2 ′ are output. Interpolated line data b3 ′ may be generated by transferring only b3 from the storage means 101 to the line buffer memory during the period.

  Therefore, if the data amount necessary for transferring one line of the main video signal is d, a data transfer amount of d × 3/2 is required per one line period when performing motion adaptive IP conversion processing. . On the other hand, when performing intra-field interpolation IP conversion processing, d / 2 data transfer may be performed per line period.

  FIG. 4 is a diagram showing an example of a display video, and shows a case where one OSD is superimposed on the front of the main video from the Nth line to the Mth line (N and M are natural numbers). The operation of the signal processing control means 109 when the main video and the OSD are blended and displayed as shown in FIG. 4 will be described below with reference to the flowchart shown in FIG.

  However, the data transfer amount of the main video signal per line period when performing the motion adaptive IP conversion process is d × 3/2, and the main video signal per line period when performing the intra-field interpolation IP conversion process The data transfer amount is d / 2, the data amount that can be transferred from the storage unit 101 in one line period determined by the bandwidth of the storage unit 101 is e, and the data amount necessary for video processing for one line of OSD data is f. In this case, it is assumed that the relationship of the following expressions is established for these data transfer amounts. These data transfer amounts are determined by the system and are stored in advance in the signal processing control means 109.

信号処理制御手段１０９は、映像信号組み合わせ設定情報１０８を基に、主映像信号以外の映像信号（ＯＳＤデータ）の処理内容を決定し、システムにより決定されるＯＳＤデータの単位時間（１ライン期間）当たりのデータ転送量を求める（ステップＳ５０１）。そして、第１の映像信号処理手段１０２による動き適応型ＩＰ変換処理に必要な１ライン期間当たりの主映像信号のデータ転送量と、ステップＳ５０１で求めたＯＳＤデータの１ライン期間当たりのデータ転送量の和が、転送制御手段１０５が１ライン期間当たりに転送可能なデータ量以内であるか否かを判別する（ステップＳ５０２）。

The signal processing control means 109 determines the processing content of the video signal (OSD data) other than the main video signal based on the video signal combination setting information 108, and the unit time (one line period) of the OSD data determined by the system The data transfer amount per hit is obtained (step S501). Then, the data transfer amount of the main video signal per one line period necessary for the motion adaptive IP conversion processing by the first video signal processing means 102 and the data transfer amount per one line period of the OSD data obtained in step S501. It is determined whether or not the sum is within the amount of data that the transfer control means 105 can transfer per line period (step S502).

  As a result, if it is not the transferable data amount, the intra-field interpolation IP conversion processing with a small data transfer amount per line period of the main video signal is determined (step S503), and the processing method control information 112 and the transfer control information 113 are determined. Is output (step S504). On the other hand, if the amount of data is transferable, the motion adaptive IP conversion process is determined and the processing method control information 112 and the transfer control information 113 are output (step S504).

  In the example shown in FIG. 4, intra-field interpolation IP conversion processing with a small data transfer amount per unit time of the main video signal is performed from the Nth line to the Mth line of the output signal, and motion adaptation is performed for the other lines. A video with better image quality is generated by performing type IP conversion processing. In the line where the OSD is superimposed and displayed on the front surface, the main image on the rear surface is often not noticed, and the deterioration of the image quality is unlikely to be a problem.

  When the main video signal and the OSD data are selectively output, as described above, the data transfer amount of the OSD data per one line period and the main video signal per one line period necessary for the adaptive IP conversion process. The IP conversion processing may be switched by determining whether or not the sum of the data transfer amount and the transfer control means 105 is within the data amount that can be transferred per line period. Since video is not displayed as a result, intra-field interpolation IP conversion processing may be determined.

  In the example shown in FIG. 4, the intra-field interpolation IP conversion processing is performed on the line on which the OSD data is displayed in a superimposed manner. For example, when the OSD data has a small width and the data transfer amount per line period of the OSD data is small. If the sum of these data transfer amounts is small, such as when the main video signal width is narrow and the data transfer amount of the main video signal per line period required for motion adaptive IP conversion processing is small, the OSD Motion adaptive IP conversion processing is also performed on the superimposed lines. Further, although the OSD data has been described as an example in the first embodiment, it goes without saying that the present invention can be similarly performed when a video signal such as sub-picture data is displayed in a superimposed manner.

  According to the first embodiment, the data transfer amount of the main video signal is controlled for each line in accordance with the display combination of the video signal, and the data transfer amount of the video signal other than the main video signal is small. Then, a data amount necessary for performing motion adaptive IP conversion processing on the main video signal is transferred. The display combination is determined by the user's setting. Whenever the combination changes, the data transfer amount of the main video signal is determined according to the data transfer amount of the video signal other than the main video signal determined in advance by the system. Changes. The IP conversion process for the main video signal is switched according to the transferable data amount. Therefore, for a line that can ensure data transfer of a plurality of fields, a motion adaptive IP conversion process can be performed on the main video signal to output a high-quality video signal. Note that the data transfer amount, the switching of the IP conversion processing method for the main video signal, and the determination of the content of the video processing for the video signal other than the main video signal are not limited for each line.

(Embodiment 2)
Hereinafter, the second embodiment will be described.
FIG. 6 is a diagram illustrating the configuration of the video processing apparatus according to the second embodiment. However, members corresponding to those described in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the second embodiment, the transfer control unit 301 notifies the signal processing control unit 303 of data transfer status per unit time between the storage unit 101 and the second video signal processing unit 103 as transfer status information 302. This is different from the first embodiment.

  That is, the transfer control unit 301 transfers data from the storage unit 101 to the first and second video signal processing units 102 and 103 according to the transfer control information 113 from the signal processing control unit 303 as in the first embodiment. While controlling, the transfer condition of video signals other than the main video signal transferred to the 2nd video signal processing means 103 is measured for every line period (unit time). Then, whether or not the transfer of the data amount necessary for performing the video processing by the second video signal processing unit 103 is completed is detected for each line period and notified as the transfer status information 302.

  The signal processing control unit 303 includes a processing content determination unit 110 and generates processing content control information 111 based on the video signal combination setting information 108 as in the first embodiment. Further, the signal processing control unit 303 generates processing method control information 112 based on the transfer status information 302, switches the IP conversion processing method by the first video signal processing unit 102, and switches the switched IP conversion. Transfer control information 113 is generated so that data transfer between the storage unit 101 and the first video signal processing unit 102 is performed at a data transfer amount per unit time necessary for processing.

  FIG. 7 is a diagram showing an example of the display image. The first OSD is superimposed on the Nth to Mth lines on the entire main image, and the second OSD is on the (N + K) th line (M + L). ) The case where it is superimposed on the line is shown. However, N, M, K, and L are natural numbers, and N + K <M.

  Subsequently, the detection of the data transfer status of the video signal other than the main video signal and the data transfer timing of the main video signal and other video signals in the second embodiment will be described with reference to FIG. Will be described. The second video signal processing means 103 has a line buffer memory for buffering each of the first OSD data and the second OSD data for two lines, and the OSD data transferred by the transfer control means 301. Is output with a delay of two lines.

  The data transfer of the main video signal has a higher priority than the data transfer of the OSD data. In FIG. 7, the width of the first OSD is narrow, and the data transfer amount of the main video signal per line period required for the motion adaptive IP conversion processing by the first video signal processing means 102 and the first It is assumed that the sum of data transfer amounts per line period of OSD data is within the data amount that can be transferred by the transfer control unit 301 per line period.

  In FIG. 8, a, b, and c in the data transfer of the main video signal (interlace signal) respectively indicate line data of the (n−1) -th field, line data of the n-th field, and line data of the (n + 1) -th field. . Further, “N + K−1”, “N + K”, etc. in the first and second OSD data transfer indicate the line data of the corresponding lines of the first and second OSD data, respectively. Also, “N + K−2”, “N + K−1”, and the like of the output indicate line data of the corresponding line output from the video output unit 104, respectively.

  At the measurement point α, the transfer control unit 301 detects that the data transfer of the first OSD data line (N + K−1) has been completed two lines before the output, and generates the transfer status information 302. Based on the transfer status information 302, the signal processing control unit 303 allows the data transfer of the main video signal and the data transfer of the first OSD data for performing the motion adaptive IP conversion process in the bandwidth of the storage unit 101. It is determined that

  At the measurement point β after the elapse of the unit time (one line period), the transfer control unit 301 completes the data transfer of the first OSD data line (N + K) two lines before the output. The transfer status information 302 is generated by detecting that the data transfer of the OSD data line (N + K) is not completed. Based on the transfer status information 302, the signal processing control unit 303 performs the data transfer of the main video signal and the data transfer of the first and second OSD data for performing the motion adaptive IP conversion processing in the band of the storage unit 101. It is determined that the width is not allowed.

  In this case, the signal processing control unit 303 generates the processing method control information 112 and the transfer control information 113, stops the data transfer of the main video signal for performing the motion adaptive IP conversion process, and transfers the single field data. Intra-field interpolation IP conversion processing for performing IP conversion processing only by the above is performed. As a result, the data transfer amount of the main video signal is reduced, OSD data can be transferred sufficiently, and failure of the OSD data output process can be prevented.

  Hereinafter, the operation of the signal processing control unit 303 when the main video and the OSD are blended and displayed as shown in FIG. 7 will be described with reference to the flowchart shown in FIG. Note that the signal processing control unit 303 generates processing method control information 112 and transfer control information 113 for performing motion adaptive IP conversion processing in the initial setting.

  The signal processing control unit 303 acquires the transfer status information 302 every unit time (one line period) (step S901). Then, it is determined whether or not the data amount of the video signal other than the main video signal transferred in one line period satisfies the data amount necessary for the video processing by the second video signal processing means 103 (step S902). ).

  As a result, if the data transfer is not completed, an intra-field interpolation IP conversion process with a small data transfer amount per line period of the main video signal is determined (step S903), and the processing method control information 112 and the transfer control information 113 are determined. Is output (step S904). On the other hand, if the data transfer is completed, the motion adaptive IP conversion process is determined and the processing method control information 112 and the transfer control information 113 are output (step S904).

  In the example shown in FIG. 7, the intra-field interpolation IP conversion processing with a small data transfer amount per unit time of the main video signal is performed from the (N + K) line to the M line of the output signal. Performs motion-adaptive IP conversion processing to generate video with better image quality.

  When the main video signal and the OSD data are selectively output, the IP conversion process may be switched based on the data transfer status of the video signal other than the main video signal as described above, Since the main video is not displayed as a result, intra-field interpolation IP conversion processing may be determined. Although the OSD data has been described as an example in the second embodiment, it is needless to say that the present invention can be similarly performed when video signals such as sub-picture data are superimposed and displayed.

  According to the second embodiment, the data transfer amount of the video signal other than the main video signal is measured every line period (unit time), and the video processing method for the main video signal is adaptively determined according to the measurement result. Can be switched. Therefore, for a line that can ensure data transfer of a plurality of fields, a motion adaptive IP conversion process can be performed on the main video signal to output a high-quality video signal.

  Further, it is not necessary to previously store a combination of data transfer amounts determined by the system in the signal processing control means, which is effective in a system that outputs a plurality of video signals in a complex combination.

  As described above, according to the first and second embodiments, a main video signal subjected to motion adaptive IP conversion processing is output for a line on which only the main video signal is displayed, and sub-picture data or For a line in which a video signal other than the main video signal such as OSD data is superimposed and the data transfer amount of the video signal other than the main video signal is increased, a main video signal subjected to intra-field interpolation IP conversion processing is output, or the main video signal is output. Since only the video signal other than the video signal is output, even when the bandwidth of the external memory is limited, a high-quality main video signal can be output for a line with a small data transfer amount of the video signal other than the main video signal.

  The video processing apparatus according to the present invention can output a high-quality main video signal on a line where the data transfer amount of a video signal other than the main video signal is small, even when the bandwidth of the external memory is limited. The present invention can also be applied to devices such as a device for displaying video signals and sub-video signals recorded on a television, and a television signal receiving display device for digital broadcasting and terrestrial broadcasting.

The figure which shows the structure of the video processing apparatus in Embodiment 1 of this invention. The figure which shows an example of a structure of the 1st video signal processing means in Embodiment 1 or 2 of this invention. Schematic diagram showing the data transfer timing of IP conversion processing by the video processing apparatus in Embodiment 1 of the present invention An image figure showing an example of a display picture in Embodiment 1 of the present invention The figure which shows the control flow of the signal processing control means in Embodiment 1 of this invention. The figure which shows the structure of the video processing apparatus in Embodiment 2 of this invention. An image figure showing an example of a display picture in Embodiment 2 of the present invention The figure for demonstrating an example of the detection of the data transfer condition in Embodiment 2 of this invention The figure which shows the control flow of the signal processing control means in Embodiment 2 of this invention. The figure which shows an example of a structure of the conventional motion adaptive IP conversion processing circuit

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Memory | storage means 102 1st video signal processing means 103 2nd video signal processing means 104 Video output means 105, 301 Transfer control means 106 Internal bus 107 Video signal combination setting means 108 Video signal combination setting information 109, 303 Signal processing control Means 110 Processing content determination means 111 Processing content control information 112 Processing method control information 113 Transfer control information 201 Line data of the (n−1) field 202 Line data of the nth field 203 Line data of the (n + 1) field 204 n-1) Line buffer memory 205 nth line buffer memory 206 (n + 1) line buffer memory 207 IP conversion processing means 302 transfer status information 1001, 1002, 1007 field memory 1003 line memory 1 004, 1005 Adder 1006 Motion detection circuit 1008 Determination unit 1009 Mixing circuit 1010, 1011 Time compression circuit 1012 Selector

Claims (3)

A video processing apparatus for generating a video signal for selectively displaying a plurality of different types of video signals or blending them,
Storage means for storing a plurality of video signals of different types;
First video signal processing means for inputting and processing a main video signal among a plurality of different types of video signals stored in the storage means and having a plurality of types of video processing functions;
Second video signal processing means for inputting a video signal other than the main video signal stored in the storage means and processing the video with processing contents corresponding to a combination of display of the plurality of different types of video signals; ,
Video output means for outputting video by combining the output from the first video signal processing means and the output from the second video signal processing means;
Transfer control means for controlling data transfer between the storage means and the first video signal processing means and the second video signal processing means;
Video signal combination setting means for setting a display combination of a plurality of different types of video signals;
Processing content determination means for determining the processing content of the video processing by the second video signal processing means based on the display combination set by the video signal combination setting means;
Based on the processing content determined by the processing content determination means, a data transfer amount per unit time between the storage means and the second video signal processing means is obtained, and the first transfer amount is determined according to the data transfer amount. The method of switching the video processing function by the video signal processing unit is switched, and the data transfer between the storage unit and the first video signal processing unit is performed at a data transfer amount per unit time according to the switched video processing function Signal processing control means for controlling the transfer control means so that
A video processing apparatus comprising: A video processing apparatus for generating a video signal for selectively displaying a plurality of different types of video signals or blending them,
Storage means for storing a plurality of video signals of different types;
A first video signal processing unit that has a plurality of types of video processing functions and inputs a main video signal among the plurality of different types of video signals stored in the storage unit, and performs video processing;
Second video signal processing means for inputting a video signal other than the main video signal stored in the storage means and processing the video with processing contents corresponding to a combination of display of the plurality of different types of video signals; ,
Video output means for outputting video by combining the output from the first video signal processing means and the output from the second video signal processing means;
Controlling data transfer between the storage means and the first video signal processing means and the second video signal processing means, and data transfer between the storage means and the second video signal processing means A transfer control means for notifying the status every unit time;
Video signal combination setting means for setting a display combination of a plurality of different types of video signals;
Processing content determination means for determining the processing content of the video processing by the second video signal processing means based on the display combination set by the video signal combination setting means;
Based on the notification from the transfer control means, the method of the video processing function by the first video signal processing means is switched, and the storage means and the data transfer amount per unit time according to the switched video processing function Signal processing control means for controlling the transfer control means so that data transfer to and from the first video signal processing means is performed;
A video processing apparatus comprising: The video processing apparatus according to claim 1 or 2,
The main video signal is an interlaced signal;
The first video signal processing means includes a filter processing system video processing function that performs interlace / progressive conversion from a multi-field interlace signal and a filter processing system video processing function that performs interlace / progressive conversion from a single field interlace signal. Have
The video processing apparatus characterized in that the signal processing control means can switch the video processing function of the first video signal processing means in units of lines.

Images