JP2006302336A - Disk reproduction device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a disk reproduction device that normally reproduces a disk even if it has high recording density. <P>SOLUTION: The disk reproduction device has a digitizing circuit 3 for phase synchronization for comparing a reproduction signal with a digitizing level for phase synchronization to generate a digitized signal; a first counter circuit 41 for detecting pulse width of the digitized signal; a digitizing circuit 43 for comparing a reproduction signal with a digitizing level different from the above digitizing level to generate a digitized signal; a second counter circuit 44 for detecting pulse width of the digitized signal; a comparator circuit 42 for outputting the pulse width obtained from the first counter circuit 41 only when the difference between two kinds of the pulse width obtained from the first and second counter circuits 41 and 42 is not more than a predetermined value; and a detection circuit 45 for detecting the maximum or minimum value from a plurality of pulse width values outputted from the comparator circuit 42. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a disc reproducing apparatus for reproducing a signal from a disc.

  In a conventional disc reproducing apparatus, a signal reproduced from a disc is converted into a binarized signal having values of “0” and “1”, and the rising and falling edges of the binarized signal and the synchronization clock By comparing the phase with each other, the frequency of the reproduction signal and the frequency of the synchronization clock are made to coincide with each other, and the frequency pull-in and the phase synchronization to make the phases of the reproduction signal and the synchronization clock coincide with each other. However, the range in which frequency pull-in and phase synchronization can be established by phase comparison is about ± 3% of the normal pull-in frequency, so the frequency of the reproduced signal deviates from the normal pull-in frequency beyond that range. In this case, frequency pull-in and phase synchronization cannot be established, and normal reproduction cannot be performed.

Therefore, since the pulse width of the binarized signal obtained by binarizing the reproduction signal as described above changes according to the length of the mark portion where the pit is formed and the space portion where the pit is not formed, By detecting the maximum or minimum value of the pulse width of the binarized signal and controlling the rotational speed of the disc motor so that the detected value becomes a predetermined value, the frequency of the reproduction signal is pulled in and phase synchronization is established. Setting is made within the possible range.
For example, a method is known in which the pulse width of the binarized signal is detected by counting a fixed clock between the edges of the binarized signal, and the rotational speed of the disk motor is controlled so that the detected value becomes a predetermined value. (See Patent Document 1).

FIG. 9 shows the configuration of a disc reproducing apparatus that sets the frequency of a reproduced signal within a range in which frequency pull-in and phase synchronization can be established by the above method.
In the disc reproducing apparatus, the signal recorded on the disc (1) is read out as a reproducing signal by the optical pickup (2), and the reproducing signal is supplied to the binarization circuit (30) to be “0”. After being converted into a binary signal consisting of “1” and “1”, it is supplied to the pattern detection circuit (40) and also to the phase synchronization circuit (5) consisting of a PLL circuit (not shown).

  In the pattern detection circuit (40), the maximum value of the pulse width of the binarized signal is detected based on the count clock supplied from the outside, and the detected value is supplied to the motor control circuit (6). The motor control circuit (6) controls the rotational speed of the disk motor (60) so that the detected value becomes a predetermined value. In this way, the linear velocity is set to an appropriate velocity, and the frequency of the reproduction signal is set within a range where frequency pull-in and phase synchronization can be established.

  In the phase synchronization circuit (5), by comparing the edge of the binarized signal from the binarization circuit (30) with the phase of the synchronization clock, the phase synchronization circuit (5) has the same frequency as the frequency of the reproduction signal and has the same phase. A clock is generated, and the generated synchronous clock is supplied to a circuit (not shown) constituting a signal reproduction system. In this way, frequency acquisition and phase synchronization are established.

FIG. 10 shows the configuration of the binarization circuit (30). The binarization circuit (30) includes a reproduction signal input terminal (31) to which a reproduction signal is to be input and a binarization signal output terminal (32) to which the binarization signal is to be output. One input terminal of a comparator (33) is connected to (31) via a capacitor C. A resistor R is connected between the capacitor C and the input terminal, and a voltage that is ½ times the power supply voltage Vcc is applied to the resistor R.
The output terminal of the comparator (33) is connected to the binarized signal output terminal (32), and a low pass filter (34) comprising a resistor R and a capacitor C is connected between these terminals. . An inverting amplifier (36) is connected to the low-pass filter (34) through a buffer (35). The inverting amplifier (36) includes three resistors R1 to R3 and a comparator (360), and a voltage that is ½ times the power supply voltage Vcc is applied to the resistor R3. The output terminal of the comparator (360) is connected to the other input terminal of the comparator (33).

The reproduction signal input from the reproduction signal input terminal (31) is input to the comparator (33), and the comparator (33) compares the reproduction signal with the slice level input from the inverting amplifier (36) as described later. The binarized signal is generated, and the binarized signal is output from the binarized signal output terminal (32) to the subsequent phase synchronization circuit and pattern detection circuit and supplied to the low-pass filter (34). An average value of the binarized signal is obtained from the low-pass filter (34), and the average value is supplied to the inverting amplifier (36) through the buffer (35) and is subjected to the inverting amplification process. The slice level obtained thereby is input to the comparator (33).
In the binarization circuit (30), when the reproduction signal is binarized, the slice level to be compared with the reproduction signal is substantially equal to the ratio of the values of “0” and “1” constituting the binarization signal. Automatically set to an equal value.
The reproduction signal changing as shown in FIG. 12A is compared with the slice level SL, and as shown in FIG. 12B, the time width corresponding to the length of the mark portion and the space portion formed on the disc. Is converted into a binary signal that is inverted. In the case of CD, the binarized signal is inverted with a time width of 3T to 11T, where T is the clock cycle at the time of recording, and in the case of DVD, it is inverted with a time width of 3T to 14T.

  FIG. 11 shows the configuration of the pattern detection circuit (40), and the binarized signal obtained from the binarization circuit (30) is supplied to the counting circuit (46). The count circuit (46) is supplied with a count clock that fluctuates with a clock cycle T during recording as shown in FIG. 12 (c). In the count circuit (46), between the edges of the binary signal. The number of count clocks supplied is counted. As a result, the count circuit (46) obtains a count value corresponding to the pulse width of the binarized signal as shown in FIG. 12 (d) when the binarized signal is inverted. The value is supplied to the value detection circuit (47). In the maximum value detection circuit (47), the maximum value is detected from the count values obtained within a predetermined time from the counting circuit (46), and the detected maximum value is supplied to the motor control circuit as described above to be supplied to the motor. It is used to control the rotation speed.

  As a method of setting the frequency of the reproduction signal within a range where frequency pull-in and phase synchronization can be established, the phase synchronization circuit ((1) is set so that the maximum count value obtained as described above matches the predetermined number of clocks of the synchronization clock. A method for controlling the frequency of a VCO (Voltage Controlled Oscilator) constituting 5) is also known.

  By the way, in recent years, in order to record a high-definition image at a high bit rate on a disc for a long time, an increase in capacity and an increase in transfer rate of an optical disc has been rapidly advanced. Conventionally, increasing the capacity of an optical disk has been attempted by shortening the wavelength of the laser beam or increasing the numerical aperture of the condenser lens. Recently, however, PRML (Partial Response Maximum Likelihood) By adopting a reproduction signal processing method called a method, it is possible to realize recording at a higher density. For example, HD-DVD (High Density Digital Versatile Disc) is known as a disc that can be reproduced by this method.

  FIG. 13 shows an MTF (Modulation Transfer Function), and the amplitude of the reproduction signal decreases as the spatial frequency increases as shown. For CDs and DVDs with a low recording density and a long pit length, a large amplitude can be obtained because the spatial frequency is low. However, an HD-DVD with a high recording density and a short pit length has a high spatial frequency, so the minimum pit length The amplitude at becomes smaller.

Japanese Patent No. 3434421

In the above conventional disk reproducing apparatus, when a CD or DVD is reproduced, the reproduction signal is sliced regardless of the length of the mark portion and the space portion formed on the disk, as shown in FIG. Although the level SL is crossed, when reproducing a disk having a high recording density such as an HD-DVD, the amplitude of the reproduced signal is reduced and intersymbol interference occurs as described above. Therefore, as shown in FIG. There is a case where the reproduction signal does not cross the slice level SL in the mark portion or the space portion. In this case, since the binarized signal is not inverted at the mark portion or space portion, the pulse width near the mark portion or space portion may be detected as the maximum value. In the example shown in FIG. 14, although the pulse width corresponding to the longest mark portion or space portion is “13”, “16” is detected. In this way, the rotational speed of the disk motor is controlled based on the pulse width that is not the pulse width corresponding to the longest mark portion or space portion. There was a problem that it was not possible to set to, and normal playback could not be performed.
An object of the present invention is to provide a disc reproducing apparatus capable of normally reproducing even a disc having a high recording density.

A disc reproducing apparatus according to the present invention includes a binarization circuit for phase synchronization that generates a binarized signal by comparing a signal reproduced from a disc with a binarization level for phase synchronization, and the generated binarized signal. A synchronization signal generation circuit for generating a synchronization signal whose phase is synchronized with the synchronization signal generation circuit. And the disc playback device
One or a plurality of binarization means for generating a binarized signal by comparing a reproduction signal with a binarization level different from the binarization level for phase synchronization;
First pulse width detection means for detecting the pulse width of the binarized signal generated by the phase synchronization binarization circuit;
One or a plurality of second pulse width detection means for detecting a pulse width of one or a plurality of binarization signals generated by the one or a plurality of binarization means;
Only when the pulse width obtained from the first pulse width detection means and the pulse width obtained from the one or more second pulse width detection means are compared and the difference between the two pulse widths is less than a predetermined value, Pulse width output means for outputting the pulse width obtained from the first pulse width detection means;
And a value detecting means for detecting a maximum value or a minimum value from a plurality of pulse widths output from the pulse width output means.

When a situation occurs in which the reproduction signal does not cross the phase synchronization binarization level at the shortest mark portion or space portion formed on the disc, the pulse width obtained from the first pulse width detection means and the one or more The difference from the pulse width obtained from the second pulse width detecting means becomes large.
Therefore, in the disk reproducing apparatus according to the present invention, the pulse width obtained from the first pulse width detecting means is compared with the pulse width obtained from the one or plural second pulse width detecting means in the corresponding time zone. When the difference between the two pulse widths exceeds a predetermined value, the pulse width obtained from the first pulse width detecting means is not output to the value detecting means, and the pulse width is processed to detect the maximum value or the minimum value. Not subject to. Therefore, the pulse width is not detected as the maximum value or the minimum value, and the pulse width corresponding to the longest or shortest mark portion or space portion can be detected as the maximum value or the minimum value.
Therefore, if the rotational speed of the disk motor is controlled based on the detected maximum value or minimum value, for example, the frequency of the reproduction signal can be set within a range where frequency pull-in and phase synchronization can be established.

  According to the disk reproducing apparatus of the present invention, even a disk having a high recording density can be normally reproduced.

Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings.
First Embodiment As shown in FIG. 1, the disk reproducing apparatus according to the present embodiment includes an optical pickup (2) for optically reading a signal from the disk (1), and is obtained from the optical pickup (2). The reproduced signal is supplied to a phase synchronization binarization circuit (3) and a pattern detection circuit (4). In the binarization circuit (3) for phase synchronization, the supplied reproduction signal is converted into a binarization signal having values of “0” and “1”, and the binarization signal is converted into a pattern detection circuit (4). And a phase synchronization circuit (5) comprising a PLL circuit (not shown).

  In the pattern detection circuit (4), the maximum value of the pulse width of the binarized signal is detected based on the count clock supplied from the outside and the reproduction signal, and the detected value is supplied to the motor control circuit (6). The The motor control circuit (6) controls the rotation of the disk motor (60) so that the detected value becomes a predetermined value. In this way, the linear velocity is set to an appropriate velocity, and the frequency of the reproduction signal is set within a range where frequency pull-in and phase synchronization can be established.

  The phase synchronization circuit (5) has the same frequency as that of the reproduction signal by comparing the edge of the binary signal from the binary circuit for phase synchronization (3) with the phase of the synchronization clock. Synchronous clocks having the same phase are generated and supplied to circuits (not shown) constituting the signal reproduction system. In this way, frequency acquisition and phase synchronization are established.

  The binarization circuit for phase synchronization (3) has the same configuration as the conventional binarization circuit (30) shown in FIG. 10, and the binarization circuit for phase synchronization (3) The slice level SL0 for phase synchronization is calculated so that the ratio of the values “0” and “1” constituting the digitized signal is substantially equal, and the reproduction signal is compared with the slice level SL0 to generate a binary signal. Is done.

  FIG. 2 shows the configuration of the pattern detection circuit (4). As described above, the binarization signal obtained from the phase synchronization binarization circuit (3) is input to the first counting circuit (41). The As shown in FIG. 3B, the first counting circuit (41) is supplied with a count clock having a fixed clock period T as shown in FIG. 3 (b). The number of count clocks supplied is counted. As a result, as shown in FIGS. 4A and 4C, when the reproduction signal crosses the phase synchronization slice level SL0, a count value C1 corresponding to the pulse width of the binarized signal is obtained. C1 is supplied to the comparison circuit (42).

A reproduction signal from the optical pickup is input to the pattern detection binarization circuit (43). In the pattern detection binarization circuit (43), the reproduction signal is compared with the pattern detection slice level SL1 to generate a binarized signal having values of “0” and “1”. Here, the slice level SL1 is set to a value smaller than the phase synchronization slice level SL0 as shown in FIG. 3A, for example, the phase synchronization slice level SL0 and the lowest level of the reproduction signal. Is set to a value that is smaller by 25% of the difference. The pattern detection slice level SL1 can be set to a value larger than the phase synchronization slice level SL0.
The binarized signal obtained from the pattern detection binarization circuit (43) is supplied to the second counting circuit (44). A count clock having a fixed clock period T is supplied to the second counting circuit (44) from the outside as shown in FIG. 3 (b), and the second counting circuit (44) is used between the edges of the binarized signal. The number of count clocks supplied is counted. As a result, as shown in FIGS. 4A and 4D, when the reproduction signal crosses the pattern detection slice level SL1, a count value C2 corresponding to the pulse width of the binarized signal is obtained. The value C2 is supplied to the comparison circuit (42).

In the comparison circuit (42), as described above, the count values C1 and C2 supplied from the first counting circuit (41) and the second counting circuit (44) in the same time zone are compared. For example, when the count value C1 from the first counting circuit (41) is obtained, the count value C1 is compared with the count value C2 obtained from the second counting circuit (44) at that time.
When the difference between the two count values is a predetermined value, for example, 1 or less, the count value C1 supplied from the first count circuit (41) is output to the maximum value detection circuit (45), while both counts When the value difference exceeds the predetermined value, the count value C1 is not output.
In the maximum value detection circuit (45), the maximum value is detected from the count value C1 supplied within a predetermined time from the comparison circuit (42). Here, in a disk recorded at a constant linear velocity, the rotational speed of the disk motor changes depending on the playback position, and particularly during the seek operation, the rotational speed of the disk motor varies greatly. It is preferably set to a value that is twice or more the interval at which the space portion appears. As a result, even when the linear velocity is reduced to ½ times the optimum value, the count value corresponding to the longest mark portion and space portion can be reliably detected as the maximum value. For example, in the case of HD-DVD, since the time interval in which the length of the longest mark portion or space portion appears is “1116T”, the predetermined time is set to “2232T”.
As described above, the maximum value of the pulse width of the binarized signal obtained from the phase synchronization binarization circuit (3) is detected, and the detected maximum value is the motor control circuit (6 ) To be used for controlling the rotation speed of the motor.

In the example shown in FIG. 3, the amplitude of the reproduction signal decreases at the shortest mark portion formed on the disk as shown in FIG. 3A, and the reproduction signal does not cross the phase synchronization slice level SL0. A count value C1 having a value of “18” is obtained from the first counting circuit (41) as shown in (c). At this time, the second counting circuit (44) as shown in FIG. Since the count value C2 having a value of 7 "is obtained and the difference between these count values C1 and C2 is 1 or more, the count value C1 having a value of" 18 "is the maximum value from the comparison circuit (42). It is not output to the detection circuit (45).
On the other hand, when a count value C1 having a value of “13” is obtained from the first counting circuit (41) as shown in (c) in the same figure, the second counting circuit (44) as shown in (d) in the same figure. Since a count value C2 having a value of “12” is obtained and the difference between these count values C1 and C2 is 1, the count value C1 having a value of “13” is the maximum from the comparison circuit (42). It is output to the value detection circuit (45).

  In the disk reproducing apparatus of the present embodiment, as described above, when a situation occurs in which the reproduction signal does not cross the phase synchronization slice level SL0 at the shortest mark portion or space portion formed on the disk, the Since the count value C1 obtained from the one counting circuit (41) is not subjected to the maximum value detection processing, the count value is not detected as the maximum value, and the count corresponding to the longest mark portion or space portion is not detected. The value can be detected as the maximum value. As a result, even with a disk having a high recording density, the reproduction signal can be set within a range in which frequency pull-in and phase synchronization can be established, and normal reproduction can be performed.

Second Embodiment The configuration of the disk reproducing apparatus of the present embodiment is the same as that of the first embodiment except for the configuration of the pattern detection circuit.
FIG. 4 shows the configuration of the pattern detection circuit (7) of this embodiment. The binarized signal obtained from the phase synchronization binarization circuit (3) is input to the first counting circuit (71). The As shown in FIG. 5B, the first counting circuit (71) is supplied with a count clock having a fixed clock period T as shown in FIG. 5 (b). The number of count clocks supplied is counted. As a result, as shown in FIGS. 4A and 4D, when the reproduction signal crosses the phase synchronization slice level SL0, a count value C1 corresponding to the pulse width of the binarized signal is obtained. C1 is supplied to the comparison circuit (72).

A reproduction signal from the optical pickup is input to the first binarization circuit (73) for pattern detection. In the first binarizing circuit for pattern detection (73), the reproduction signal is compared with the first slice level SL1 for pattern detection to generate a binarized signal having values of “0” and “1”. . Here, the slice level SL1 is set to a value smaller than the phase synchronization slice level SL0 as shown in FIG. 5A. For example, the slice level SL1 is equal to the phase synchronization slice level SL0 and the lowest level of the reproduction signal. It is set to a small value by 25% of the difference.
The binarized signal obtained from the pattern detection first binarization circuit (73) is supplied to the second counting circuit (74). As shown in FIG. 5B, the second counting circuit (74) is supplied with a count clock having a fixed clock period T as shown in FIG. 5 (b). The second counting circuit (74) receives an interval between edges of the binarized signal. The number of count clocks supplied is counted. As a result, as shown in FIGS. 9A and 9E, when the reproduction signal crosses the first slice level SL1 for pattern detection, a count value C2 corresponding to the pulse width of the binarized signal is obtained. The count value C2 is supplied to the comparison circuit (72).

The reproduction signal from the optical pickup is input to the pattern detection second binarization circuit (75). In the second binarization circuit for pattern detection (75), the reproduction signal is compared with the second slice level SL2 for pattern detection to generate a binarized signal having values of “0” and “1”. . Here, the slice level SL2 is set to a value larger than the phase synchronization slice level SL0 as shown in FIG. 5A. For example, the slice level SL2 is equal to the slice synchronization level SL0 and the maximum level of the reproduction signal. It is set to a value that is larger by 25% of the difference.
The binarized signal obtained from the pattern detection second binarization circuit (75) is supplied to the third counting circuit (76). The third counting circuit (76) is supplied with a count clock having a fixed clock period T from the outside as shown in FIG. 5 (b), and the third counting circuit (76) is used between the edges of the binarized signal. The number of count clocks supplied is counted. As a result, as shown in FIGS. 4A and 4C, when the reproduction signal crosses the pattern detection second slice level SL2, a count value C3 corresponding to the pulse width of the binarized signal is obtained. The count value C3 is supplied to the comparison circuit (72).

The comparison circuit (72) compares the count values C1, C2, and C3 supplied from the first to third counting circuits (71), (74), and (76) in the same time zone as described above. For example, when the count value C1 from the first count circuit (71) is obtained, the count value C1 is obtained from the second count circuit (74) and the third count circuit (76) at that time. It is compared with the count values C2 and C3.
The difference between the count value C1 from the first count circuit (71) and the count value C2 from the second count circuit (74) is a predetermined value, for example, 1 or less, and from the first count circuit (71). When the difference between the count value C1 and the count value C3 from the third count circuit (76) is not more than the predetermined value, the count value C1 supplied from the first count circuit (71) is the maximum value detection circuit ( 77). On the other hand, when the difference between the count value C1 from the first count circuit (71) and the count value C2 from the second count circuit (74) exceeds the predetermined value, and the count value from the first count circuit (71). When the difference between C1 and the count value C3 from the third count circuit (76) exceeds the predetermined value, the count value C1 is not output from the first count circuit (71).
In the maximum value detection circuit (77), the maximum value is detected from the count value C1 supplied within a predetermined time from the comparison circuit (72). Here, like the first embodiment, the predetermined time is set to a value that is twice or more the interval at which the longest mark portion or longest space portion appears.
As described above, the maximum value of the pulse width of the binarized signal obtained from the phase-synchronizing binarization circuit (3) is detected, and the detected maximum value is supplied to the motor control circuit and supplied to the motor. Used for rotation control.

  In the disk reproducing apparatus of this embodiment, when a situation occurs in which the reproduction signal does not cross the phase synchronization slice level SL0 at the mark portion formed on the disk, and the reproduction signal crosses the slice level SL0 at the space portion. When the situation does not occur, the count value C1 obtained from the first counting circuit (71) at that time is not the target of the maximum value detection process, so the count value is not detected as the maximum value. The count value corresponding to the longest mark portion or space portion can be detected as the maximum value. As a result, even with a disk having a high recording density, the reproduction signal can be set within a range in which frequency pull-in and phase synchronization can be established, and normal reproduction can be performed.

Third Embodiment The configuration of the disk reproducing apparatus of the present embodiment is the same as that of the second embodiment except for the pattern detection circuit. The pattern detection circuit (8) of the present embodiment reproduces as shown in FIG. An amplitude detection circuit (83) for detecting the amplitude of the signal is provided. The amplitude of the reproduction signal is detected, for example, by subtracting the lower peak value from the upper peak value of the reproduction signal. The amplitude detected by the amplitude detection circuit (83) is supplied to the first binarization circuit for pattern detection (81) and the second binarization circuit for pattern detection (82), and these binarization circuits (81 ) (82) respectively change the first slice level SL1 for pattern detection and the second slice level SL2 for pattern detection according to the supplied amplitude. These slice levels SL1 and SL2 are set to values that increase the difference from the phase synchronization slice level SL0 as the amplitude increases, and to values that decrease the difference from the phase synchronization slice level SL0 as the amplitude decreases. Is set. For example, the difference from the phase synchronization slice level SL0 is changed in proportion to the amplitude.

If the first slice level SL1 for pattern detection and the second slice level SL2 for pattern detection are constant regardless of the amplitude of the reproduction signal, when the amplitude of the reproduction signal decreases due to dust, scratches, fingerprints, etc. Since the difference between the count value obtained from the first count circuit (71) and the count value obtained from the second count circuit (74) and the third count circuit (76) becomes large, the first count circuit (71) Although the obtained count value is a count value corresponding to the longest mark portion or space portion, a situation occurs in which the count value is not output from the comparison circuit (72) to the maximum value detection circuit (77).
On the other hand, in the disk reproducing apparatus of the present embodiment, the first slice level SL1 for pattern detection and the second slice level SL2 for pattern detection are changed according to the amplitude of the reproduced signal, so that the above situation is prevented. The count value corresponding to the longest mark portion or space portion can be detected as the maximum value.

Fourth Embodiment The configuration of the disk reproducing apparatus of the present embodiment is the same as that of the second embodiment except for the pattern detection circuit. The pattern detection circuit (9) of the present embodiment reproduces as shown in FIG. A lower peak value detection circuit (92) for detecting the lower peak value of the signal and an upper peak value detection circuit (94) for detecting the upper peak value of the reproduction signal are provided.
The lower peak value detected by the lower peak value detection circuit (92) is supplied to the first binarization circuit (91) for pattern detection, while the upper peak value detected by the upper peak value detection circuit (94). The peak value is supplied to the second binarization circuit (93) for pattern detection.

FIG. 8 shows an example of the waveform of the reproduction signal. The lower envelope shown in FIG. 8 is obtained by performing peak holding with a predetermined time constant by the lower peak value detection circuit (92), and the upper envelope is obtained by the upper peak value detection circuit (94). The bottom hold is performed with a predetermined time constant.
The first binarization circuit (91) for pattern detection subtracts the lower peak value supplied as described above from the slice level SL0 for phase synchronization and calculates the amplitude a below the slice level SL0. The amplitude a is multiplied by a coefficient n (0 <n <1), and the multiplication result is subtracted from the phase synchronization slice level SL0 to calculate the pattern detection first slice level SL1.
On the other hand, the second binarization circuit for pattern detection (93) calculates the amplitude b above the slice level SL0 by subtracting the phase synchronization slice level SL0 from the upper peak value supplied as described above. The amplitude b is multiplied by a coefficient m (0 <m <1), and the multiplication result is added to the phase synchronization slice level SL0 to calculate the pattern detection second slice level SL2.
As the difference between the first slice level SL1 for pattern detection and the second slice level SL2 for pattern detection and the slice level SL0 for phase synchronization increases, it is obtained from the second counting circuit (74) and the third counting circuit (76). Since the difference between the count value and the count value obtained from the first counting circuit (71) becomes large, the coefficients n and m are preferably set to a value of 0.25 or less.

  In the disk reproducing apparatus of the present embodiment, the pattern detection first slice level SL1 is changed according to the amplitude a lower than the phase synchronization slice level SL0 of the reproduction signal, and the pattern according to the upper amplitude b. Since the detection second slice level SL2 is changed, the count value corresponding to the longest mark portion or space portion is detected as the maximum value even when the amplitude of the reproduction signal is reduced, as in the third embodiment. I can do it.

In addition, each part structure of this invention is not restricted to the said embodiment, A various deformation | transformation is possible within the technical scope as described in a claim.
For example, in the first to fourth embodiments, by controlling the rotational speed of the disk motor (60) shown in FIG. 1, the frequency of the reproduction signal is set within a range where frequency pull-in and phase synchronization can be established. However, the frequency of the VCO (not shown) constituting the phase synchronization circuit (5) may be controlled so that the maximum value detected by the pattern detection circuit (4) matches the predetermined number of clocks of the synchronization clock. Is possible.
Also, the maximum value of the pulse width of the binarized signal is detected, and the rotational speed of the disk motor (60) is controlled based on the detected maximum value, but the minimum value of the pulse width of the binarized signal is detected. It is also possible to control the rotation speed of the disk motor (60) based on the detected minimum value.

  Further, the maximum value detection circuit (45) (77) compares the detected maximum count value with the count value obtained from the first count circuit (41) (71) next to the maximum count value, and the comparison result The maximum count value can be output to the motor control circuit (5) according to the above. For example, in the case of HD-DVD, the length of the longest mark portion or space portion is represented by “13T”, and the length of the mark portion or space portion next to the longest mark portion or space portion is “3T”. When the ratio between the maximum count value detected and the count value obtained from the first count circuit (41) (71) is “4” (≈13T / 3T) or less On the other hand, while the maximum count value is output, when it exceeds “4”, the maximum count value is not output. Thereby, it is possible to prevent erroneous detection of the count value corresponding to the longest mark portion or space portion.

In addition, an A / D conversion circuit is provided before the phase synchronization binarization circuit (3) shown in FIG. 1 to convert the signal reproduced from the disk (1) into a digital signal, and then the phase synchronization binary. It is also possible to adopt a configuration for supplying to the circuit 3 (3) and the pattern detection circuit (4). According to this configuration, since there is no influence of a circuit offset or the like, it is possible to prevent erroneous detection of the count value corresponding to the longest mark portion or space portion.
Furthermore, an equalizer circuit is provided in front of the phase-synchronizing binarization circuit (3) shown in FIG. 1, and processing for emphasizing the high frequency band is performed on the signal reproduced from the disk (1). It is also possible to adopt a configuration in which the obtained signal is supplied to the phase synchronization binarization circuit (3) and the pattern detection circuit (4). According to this configuration, since the amplitude of the reproduction signal at the shortest mark portion and space portion increases, the possibility that the reproduction signal does not cross the phase synchronization slice level at the mark portion and space portion is reduced. I can do it.

Further, in the first embodiment, it is possible to provide an amplitude detection circuit for detecting the amplitude of the reproduction signal, and to change the pattern detection slice level SL1 in accordance with the detected amplitude.
In the second to fourth embodiments, the pattern detection first slice level SL1 and the pattern detection second slice level SL2 may be set so that the difference from the phase synchronization slice level SL0 is equal. Is possible.

It is a block diagram showing the structure of the disc reproducing | regenerating apparatus concerning this invention. It is a block diagram showing the structure of the pattern detection circuit of 1st Example. It is a wave form diagram of various signals obtained in the disc reproducing apparatus of the first embodiment. It is a block diagram showing the structure of the pattern detection circuit of 2nd Example. It is a wave form diagram of various signals obtained in the disc reproducing apparatus of the second embodiment. It is a block diagram showing the structure of the pattern detection circuit of 3rd Example. It is a block diagram showing the structure of the pattern detection circuit of 4th Example. It is a waveform diagram of a reproduction signal. It is a block diagram showing the structure of the conventional disc reproducing | regenerating apparatus. It is a circuit diagram showing the structure of a binarization circuit. It is a block diagram showing the structure of the conventional pattern detection circuit. It is a wave form diagram of various signals obtained in a conventional disc reproducing apparatus. It is a graph showing the relationship between a spatial frequency and a signal amplitude. It is a wave form diagram of various signals for explaining a conventional problem.

Explanation of symbols

(1) Disc
(2) Optical pickup
(3) Binary circuit for phase synchronization
(4) Pattern detection circuit
(41) First counter circuit
(42) Comparison circuit
(43) Binary circuit for pattern detection
(44) Second counter circuit
(45) Maximum value detection circuit
(5) Phase synchronization circuit
(6) Motor control circuit
(60) Disc motor

Claims (9)

A binary signal for phase synchronization that generates a binary signal by comparing the signal reproduced from the disc with the binary level for phase synchronization, and a synchronization signal whose phase is synchronized with the generated binary signal In a disk playback device comprising a synchronizing signal generation circuit that
One or a plurality of binarization means for generating a binarized signal by comparing a reproduction signal with a binarization level different from the binarization level for phase synchronization;
First pulse width detection means for detecting the pulse width of the binarized signal generated by the phase synchronization binarization circuit;
One or a plurality of second pulse width detection means for detecting a pulse width of one or a plurality of binarization signals generated by the one or a plurality of binarization means;
Only when the pulse width obtained from the first pulse width detection means and the pulse width obtained from the one or more second pulse width detection means are compared and the difference between the two pulse widths is less than a predetermined value, Pulse width output means for outputting the pulse width obtained from the first pulse width detection means;
A disk reproducing apparatus comprising: a value detecting means for detecting a maximum value or a minimum value among a plurality of pulse widths output from the pulse width output means.   There is one binarization means and one second pulse width detection means, and the pulse width output means is a pulse width obtained from the first pulse width detection means and a second pulse width detection. 2. The disk according to claim 1, wherein the pulse width obtained from the first pulse width detection means is output only when the difference between the two pulse widths is equal to or less than a predetermined value. Playback device.   The disc reproducing apparatus according to claim 2, wherein the binarization level for phase synchronization is set to a value at which the ratio of two values constituting the generated binarized signal is substantially equal.   4. The disc reproducing apparatus according to claim 2, further comprising amplitude detecting means for detecting an amplitude of a reproduction signal, wherein the binarizing means changes a binarization level in accordance with the detected amplitude.   There are two binarization means and two second pulse width detection means, and the pulse width output means includes a pulse width obtained from the first pulse width detection means and one second pulse. The pulse width obtained from the width detecting means is compared, the pulse width obtained from the first pulse width detecting means is compared with the pulse width obtained from the other second pulse width detecting means, and the first pulse width is obtained. The difference between the pulse width obtained from the detection means and the pulse width obtained from the one second pulse width detection means is less than a predetermined value, and the pulse width obtained from the first pulse width detection means and the other 2. The disk reproduction according to claim 1, wherein the pulse width obtained from the first pulse width detecting means is output only when the difference from the pulse width obtained from the second pulse width detecting means is not more than a predetermined value. apparatus.   The binarization level for phase synchronization is set to a value at which the ratio of two values constituting the generated binarized signal is substantially equal, and one of the two binarization means is binarized. The binarization level of the means is set to a value larger than the binarization level for phase synchronization, and the binarization level of the other binarization means is set to a value smaller than the binarization level for phase synchronization. The disk reproducing apparatus according to claim 5.   The difference between the binarization level for the phase synchronization and the binarization level of the one binarization unit is the same as the difference between the binarization level for the phase synchronization and the binarization level of the other binarization unit The disk reproducing apparatus according to claim 6.   8. An amplitude detection unit for detecting an amplitude of a reproduction signal is provided, and the two binarization units change a binarization level according to the detected amplitude. Disc player.   Of the upper and lower peak values appearing in the reproduced signal, the upper peak value detecting means for detecting the upper peak value and the lower peak value detecting means for detecting the lower peak value, the one binarizing means Changes the binarization level in accordance with the difference between the detected upper peak value and the phase synchronization binarization level, and the other binarization means includes the detected lower peak value and the phase 7. The disc reproducing apparatus according to claim 6, wherein the binarization level is changed in accordance with a difference from the binarization level for synchronization.

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