JP2006295264A - Signal multiplexer/demultiplexer and signal multiplexing/demultiplexing method used for same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signal multiplexer/demultiplexer capable of minimizing signal discard without the need for increasing the circuit scale. <P>SOLUTION: PMAs 11, 15 carry out recovery of a clock from a GbE [Gigabit Ethernet (R)] signal received from ports 1, 2, serial/parallel conversion of the signal, and detection of input interruption. 8B/10B synchronization sections 12, 16 synchronize 8B/10B codes on the basis of signals in 10 bits subjected to parallel processing by the PMAs 11, 15, respectively. Pointer insert sections 13, 17 insert a pointer indicating a port number into idle codes of the 8B/10B codes. Fixed pattern generating sections 19, 20 generate dummy signals inserted at signal interruption. Selection sections 14, 18 select either of real signals and the dummy signals. A multiplexer section 21 applies bit multiplex to the signals of the port 1 and the signals of the port 2. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a signal multiplexing / demultiplexing apparatus and a signal multiplexing / demultiplexing method used therefor, and more particularly to a signal multiplexing / demultiplexing apparatus for multiplexing and demultiplexing a GbE [Gigabit Ethernet (registered trademark)] signal.

  Conventionally, in a GbE signal multiplexer / demultiplexer, an 8B / 10B code is used as a TGFP in order to insert a pointer indicating which port the signal to be demultiplexed is, and alarm information when the port signal is disconnected. A method of mapping and multiplexing to another frame such as a (Transparent Generic Framing Procedure) frame or an SDH (Synchronous Digital Hierarchy) frame is generally used.

  In the method of time-division multiplexing the GbE signal described above, when data of a plurality of ports are multiplexed, a comma code (10-bit data starting with “0011111” or “1100000”) is included in data from all ports. Although bit boundaries can be recognized, it is impossible to recognize from which port the data comes.

  In order to solve this problem, as a method of time-division multiplexing a GbE signal, a comma code is replaced with another code at the time of data multiplexing, and another code in which the port boundary of serial data multiplexed at the time of data separation is replaced. A method has been proposed in which the detection is performed on the basis and the other code is returned to the comma code (see, for example, Patent Document 1).

JP 2003-032259 A

  However, in the conventional GbE signal multiplexing / demultiplexing device described above, in the case of the method of mapping and multiplexing to another frame, a mapping circuit from an 8B / 10B code to a TGFP frame or an SDH frame, a clock speed conversion circuit, etc. This is necessary and the circuit scale tends to increase.

  Further, in the conventional multiplexing / demultiplexing device, in the case of the technique described in Patent Document 1 described above, when N port signals are multiplexed, only the port identification marker is inserted into the port 1 signal. If the synchronization is lost, the port signal is discarded until the next port identification marker is detected. Also, this technique does not consider how to deal with when the signal of each multiplexed port is cut off.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a signal multiplexing / demultiplexing apparatus and a signal multiplexing / demultiplexing method used therefor that can solve the above-described problems and can minimize signal discard without increasing the circuit scale. There is.

  Another object of the present invention is to provide a signal multiplexing / demultiplexing apparatus and a signal multiplexing / demultiplexing method used therefor, which can multiplex and transmit signals of other ports when the signal of each port is disconnected. There is to do.

A signal multiplexer / demultiplexer according to the present invention is a signal multiplexer / demultiplexer for demultiplexing signals from a plurality of ports at the level of 8B / 10B code,
On the multiplex side, provided with insertion means for inserting a pointer indicating the port number of the signal into the idle code part included in the 8B / 10B code,
Detection means for detecting the pointer from the multiplexed signal is provided on the separation side. .

In addition to the above-described configuration, another signal multiplexing / demultiplexing device according to the present invention includes a means for detecting that the signal has been disconnected on the multiplexing side, and a signal of the port at which the input has been detected. Means for inserting a fixed pattern instead,
The separation side includes means for detecting the fixed pattern from the multiplexed signal and means for outputting an alarm when the fixed pattern is detected.

A signal multiplexing / demultiplexing method according to the present invention is a signal multiplexing / demultiplexing method used in a signal multiplexing / demultiplexing apparatus that demultiplexes signals from a plurality of ports at the level of 8B / 10B code,
On the multiplexing side of the signal multiplexer / demultiplexer, a pointer indicating the port number of the signal is inserted into the idle code portion included in the 8B / 10B code,
The pointer is detected from the multiplexed signal on the separation side of the signal multiplexer / demultiplexer.

According to another signal multiplexing / demultiplexing method of the present invention, in addition to the above processing, when it is detected on the multiplexing side that the signal is disconnected, the signal of the port where the input disconnection is detected is replaced. Insert a fixed pattern into the
On the separation side, an alarm is output when the fixed pattern is detected from the multiplexed signal.

  That is, the signal multiplexing / demultiplexing device of the present invention is a device that demultiplexes a GbE [Gigabit Ethernet (registered trademark)] signal at the level of 8B / 10B code, as a pointer indicating a port number of a signal required at the time of demultiplexing. By using the idle code portion included in the 8B / 10B code, demultiplexing is performed without mapping the 8B / 10B code to another frame, thereby eliminating the need for a mapping circuit and a clock speed conversion circuit. Realization with a small circuit configuration using (Programmable Logic Device) or the like becomes possible.

  In the signal multiplexing / demultiplexing apparatus of the present invention, an idle code having no information included in the GbE signal is used as a demultiplexing pointer. Therefore, the GbE signal is not mapped to another frame, and the 8B / 10B code level is used. Since demultiplexing is possible, it becomes possible with a small circuit configuration, which contributes to downsizing, higher density, and lower power consumption of the mounted device.

  Further, in the signal multiplexing / demultiplexing apparatus of the present invention, since the idle code part included in the 8B / 10B code is used as a pointer indicating the port number of the signal required at the time of demultiplexing, the signal is out of synchronization. However, if the next pointer is detected, it is possible to recover immediately, and signal discard can be minimized.

  Furthermore, in the signal multiplexing / demultiplexing device of the present invention, when an input signal of a certain port is cut off, a fixed pattern is inserted in place of the signal of that port. These signals can be multiplexed and transmitted without affecting the signals.

  The signal multiplexer / demultiplexer according to the present invention has the configuration and operation described below, whereby the effect of minimizing the discarding of signals can be obtained without increasing the circuit scale.

  In addition, the other signal multiplexing / demultiplexing device of the present invention is configured and operated as described below, so that when the signal of each port is disconnected, the signals of other ports are multiplexed and transmitted. The effect that it can be obtained.

  Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a multiplexing side device of a signal multiplexing / demultiplexing device according to an embodiment of the present invention. In FIG. 1, the multiplexing side device 1 includes PMA (Physical Medium Attachment) 11 and 15, 8B / 10B synchronization units 12 and 16, pointer insertion units 13 and 17, selection units (SEL: Selectors) 14 and 18, The fixed pattern generation units 19 and 20 and the multiplexing unit 21 are included. The multiplexer 1 shown in FIG. 1 is an apparatus that multiplexes two signals of ports 1 and 2.

  The PMAs 11 and 15 perform clock recovery, signal serial-parallel conversion, and input disconnection detection from GbE [Gigabit Ethernet (registered trademark)] signals input from the ports 1 and 2. The 8B / 10B synchronization units 12 and 16 synchronize the 8B / 10B code from the signals parallelized to 10 bits by the PMAs 11 and 15.

  The pointer insertion units 13 and 17 insert a pointer indicating a port number into an idle code of 8B / 10B code. Fixed pattern generation units 19 and 20 generate a dummy signal to be inserted when the signal is interrupted. The selection units 14 and 18 select either the real signal or the dummy signal. The multiplexing unit 21 bit-multiplexes the port 1 signal and the port 2 signal.

  PMA 11, 15, 8B / 10B code synchronization units 12, 16, pointer insertion units 13, 17, selection units 14, 18 are provided for port 1 and port 2, respectively, and port 1 side is PMA 11, 8B / 10B The synchronization unit 12, the pointer insertion unit 13, and the selection unit 14 are connected in this order, and the port 2 side is connected in the order of the PMA 15, the 8B / 10B synchronization unit 16, the pointer insertion unit 17, and the selection unit 18.

  Fixed pattern generation units 19 and 20 are also provided for port 1 and port 2, respectively. The output of fixed pattern generation unit 19 is supplied to selection unit 14 and the output of fixed pattern generation unit 20 is supplied to selection unit 18, respectively. Is done. In addition, signals for notifying the input interruption detected by the PMAs 11 and 15 are connected to the selection units 14 and 18, and outputs of the selection units 14 and 18 are input to the multiplexing unit 21.

  FIG. 2 is a block diagram showing the configuration of the demultiplexing side apparatus of the signal multiplexing / demultiplexing apparatus according to one embodiment of the present invention. In FIG. 2, the separation side device 3 includes a separation unit 31, 8B / 10B synchronization units 32 and 37, pointer detection units 33 and 38, a port selector 34, fixed pattern detection units 35 and 39, and PMA 36 and 40. It is composed of The separation side device 3 shown in FIG. 2 is a device that separates two signals of the ports 1 and 2.

  The demultiplexing unit 31 demultiplexes the multiplexed signal from the multiplexing side device 1 and supplies the output to the 8B / 10B synchronization units 32 and 37, respectively. The 8B / 10B synchronization units 32 and 37 perform 8B / 10B code synchronization of the signals separated by the separation unit 31, and the pointer detection units 33 and 38 detect the pointers inserted by the multiplexing device 1, respectively.

  The port selector 34 performs signal port switching based on pointer information detected by the pointer detectors 33 and 38. The fixed pattern detectors 35 and 39 determine whether or not each input signal is a dummy signal. Each of the PMAs 36 and 40 converts the parallel signal into a 1.25 Gbps serial signal.

  8B / 10B synchronization units 32 and 37, pointer detection units 33 and 38, fixed pattern detection units 35 and 39, and PMAs 36 and 40 are provided in port 1 and port 2, respectively. On the port 1 side, 8B / 10B synchronization is performed. 32, pointer detector 33, port selector 34, fixed pattern detector 35, and PMA 36 are connected in this order. On the port 2 side, the 8B / 10B synchronization unit 37, the pointer detection unit 38, the port selector 34, the fixed pattern detection unit 39, and the PMA 40 are connected in this order.

  From the 8B / 10B synchronization units 32 and 37, a bit shift signal output when synchronization is not established is supplied to the separation unit 31. Further, pointer information indicating which port the processed signal is from is supplied from the pointer detection units 33 and 38 to the port selector 34.

  FIG. 3 is a diagram showing a GbE signal input to the ports 1 and 2 of the signal multiplexing / demultiplexing apparatus according to the embodiment of the present invention. In FIG. 3, the GbE signal means a signal for serially transferring an 8B / 10B code in which one code is composed of 10 bits at a speed of 1.25 Gbps.

  In FIG. 3, “/ S /” is a code representing the beginning of data, “/ D /” is a code representing data, “/ T /” is a code representing the end of data, and “/ I /” is no data. It is an idle code used to fill a state (idle state).

In this embodiment, in order to clarify the signals of the ports 1 and 2, a suffix is added to the above code, and in the GbE signal of the port 1, “/ S ₁ /”, “/ D ₁ /”, “/ T ₁ / ”,“ / I ₁ / ”, and the GbE signal of port 2 is expressed as“ / S ₂ / ”,“ / D ₂ / ”,“ / T ₂ / ”,“ / I ₂ / ”. ing.

  4 is a diagram showing output signals of the PMAs 11 and 15 of FIG. 1, FIG. 5 is a diagram showing rearrangement signals in the multiplexing side device 1 of FIG. 1, and FIG. 17 is a diagram showing the output signal of FIG. 7, FIG. 7 is a diagram showing the output signal of the multiplexing unit 21 of FIG. 1, and FIG. 8 is the output when the port 1 of the multiplexing side device 1 of FIG. It is a figure which shows an example of a signal. 9 and 10 are diagrams showing output signals of the separation unit 31 of FIG. The demultiplexing operation of the signal multiplexer / demultiplexer according to one embodiment of the present invention will be described with reference to FIGS.

  In the multiplexing apparatus 1, first, these GbE signals are input to the PMAs 11 and 15, respectively. Since the PMAs 11 and 15 extract a clock from the received GbE signal and perform serial-parallel conversion of 1:10, a 10-bit parallel signal is output with a 125 MHz clock as shown in FIG.

  The next-stage 8B / 10B synchronization units 12 and 16 synchronize the 8B / 10B code, rearrange the code so that the top of the code comes to the position of Bit0, and output it as shown in FIG. Further, the pointer insertion units 13 and 17 replace one code of the “/ I /” code with a pointer code (in this case, expressed as “/ P /”), and output a signal shown in FIG.

  The pointer code “/ P1 /” for port 1 and the pointer code “/ P2 /” for port 2 are different from each other (bit string) in order to enable the separation side device 3 to identify them. Since the “/ I /” code is a code for filling the no-signal state, even if the “/ P /” code is replaced, the information of the GbE signal is not affected.

  In the signal shown in FIG. 6, the “/ I /” code located in the time slot immediately after the “/ T /” code is replaced. May be replaced.

  On the other hand, the fixed pattern generation units 19 and 20 always generate a fixed pattern in which “/ P /” codes are inserted into a dummy code (in this case, expressed as “/ A /”) at regular intervals.

  The selection units 14 and 18 select and output the input from the pointer insertion units 13 and 17 and the input from the fixed pattern generation units 19 and 20, respectively. Normally, the selection units 14 and 18 select the signals from the pointer insertion units 13 and 17, but when the PMA 11 or 15 detects the disconnection of the GbE signal, the signals from the fixed pattern generation units 19 and 20 are detected. Switch.

  Further, the selection units 14 and 18 switch back the input from the fixed pattern generation units 19 and 20 to the input from the pointer insertion units 13 and 17 when the input disconnection is restored. The signal processing from the PMA 11 and 15 to the selection units 14 and 18 is performed independently at the port 1 and the port 2, respectively.

  The final stage multiplexing unit 21 bit-multiplexes the output of the selection unit 14 which is the signal of the port 1 and the output of the selection unit 18 which is the signal of the port 2, and generates a 2.5 Gbps serial signal as shown in FIG. Output. FIG. 8 shows an example of an output signal when the input of port 1 is cut off. A dummy code “/ A /” is inserted in place of the signal of port 1.

  In the separation side device 3, first, a 2.5 Gbps serial signal shown in FIGS. 7 and 8 is input to the separation unit 31. The separation unit 31 performs 1:20 parallel-serial conversion and outputs a 20-bit parallel signal of a 125 MHz clock as shown in FIG. Bit0 to Bit9 are input to the 8B / 10B synchronization unit 32, and Bit10 to Bit19 are input to the 8B / 10B synchronization unit 37. The separation unit 31 simply performs 1:20 bit separation, and is illustrated in FIG. Thus, Bit0 or Bit10 is not always the first bit of the 8B / 10B code.

  Therefore, in the 8B / 10B synchronization processing in the 8B / 10B synchronization units 32 and 37 in the next stage, the bit shift signal is fed back to the separation unit 31 until synchronization is established. When the separation unit 31 receives the bit shift signal, the output is bit-shifted such that the Bit0 output is Bit1 and the Bit1 output is Bit2.

  When synchronization is established by the 8B / 10B synchronization units 32 and 37, the bit shift signal is stopped, and the output of the separation unit 31 is in a state where the head of the 8B / 10B code comes to Bit0 and Bit10 as shown in FIG. Converge. However, at this time, the 8B / 10B synchronization unit 32 does not necessarily receive the port 1 signal and the 8B / 10B synchronization unit 37 receives the port 2 signal.

Therefore, the next-stage pointer detection units 33 and 38 recognize whether “/ P /” in the input frame signal is “/ P ₁ /” or “/ P ₂ /” and to the port selector 34. The port information is output together with the signal. The pointer detection units 33 and 38 also have a function of returning “/ P /” to “/ I /”.

In the port selector 34,
If the frame input from the pointer detection unit 33 is a port 1 signal, output to the fixed pattern detection unit 35. If the frame input from the pointer detection unit 33 is a port 2 signal, output to the fixed pattern detection unit 39. If the frame input from the pointer detection unit 38 is a port 1 signal, output to the fixed pattern detection unit 35. If the frame input from the pointer detection unit 38 is a port 2 signal, output to the fixed pattern detection unit 39. The switching operation is performed.

  By the operation of the port selector 34 described above, the signal input from the port 1 in the multiplexing side device 1 is output from the port 1 of the separation side device 3, and the signal input from the port 2 in the multiplexing side device 1 is output from the separation side device 3. Is output from the port 2.

  The fixed pattern detectors 35 and 39 have a function of detecting the dummy code “/ A /” pattern, and when the dummy code “/ A /” pattern is detected, the pattern is output to the outside as an alarm.

  The alarm of the fixed pattern detector 35 to which the signal of the port 1 is inputted means that the signal input of the port 1 of the multiplexing side apparatus 1 is interrupted, and the alarm of the fixed pattern detector 39 to which the signal of the port 2 is inputted is This means that the signal input of the port 2 of the multiplex side device 1 is cut off. The PMA 36 and 40 in the final stage convert the 10 parallel signals of the port 1 and the port 2 shown in FIG. 5 into 1.25 Gbps serial signals shown in FIG. 3 and output them.

  As described above, in this embodiment, an idle code that is included in the GbE signal and has no information is used as a demultiplexing pointer. Therefore, without mapping the GbE signal to other frames, the 8B / 10B code level can be used. Demultiplexing is possible, and a mapping circuit and a clock speed conversion circuit are not required, and a small-scale circuit configuration using PLD (Programmable Logic Device) or the like can be realized.

  That is, in this embodiment, an idle code that does not have information included in the GbE signal is used as a demultiplexing pointer. Therefore, the GbE signal is demultiplexed at the 8B / 10B code level without mapping it to another frame. Therefore, it can be realized with a small circuit configuration, which contributes to downsizing, high density, and low power consumption of the mounted device.

  In this embodiment, since the idle code part included in the 8B / 10B code is used as a pointer indicating the port number of the signal required at the time of demultiplexing, the next pointer even if the signal is out of synchronization. If it is detected, it is possible to recover immediately and signal discard can be minimized.

  Further, in this embodiment, when the input signal of a certain port is cut off, a fixed pattern (dummy code “/ A /” pattern) is inserted instead of the signal of that port. These signals can be multiplexed and transmitted without affecting the signals of other ports that are not.

  FIG. 11 is a block diagram showing a configuration of a multiplexing side device of a signal multiplexing / demultiplexing device according to another embodiment of the present invention, and FIG. 12 is a diagram of a separating side device of a signal multiplexing / demultiplexing device according to another embodiment of the present invention. It is a block diagram which shows a structure. 11 and 12 show configuration examples for realizing demultiplexing of n signals by a signal multiplexing / demultiplexing apparatus according to another embodiment of the present invention.

  That is, the multiplexing-side apparatus 1 includes PMAs 11-1 to 11-n, 8B / 10B synchronization units 12-1 to 12-n, pointer insertion units 13-1 to 13-n, and selection units 14-1 to 14-. n, fixed pattern generation units 19-1 to 19-n, and a multiplexing unit 21.

  The separation-side device 3 includes a separation unit 31, 8B / 10B synchronization units 32-1 to 32-n, pointer detection units 33-1 to 33-n, a port selector 34, and a fixed pattern detection unit 35-1. To 35-n and PMA 36-1 to 36-n.

  11 and 12, the multiplexing device 1 and the separating device 3 of the signal multiplexing / demultiplexing device according to another embodiment of the present invention are the signal multiplexing / demultiplexing device according to the embodiment of the present invention shown in FIGS. The configuration is the same as that of the multiplex side device 1 and the separation side device 3 of the separation device, and the same components are denoted by the same reference numerals. The operation is the same as that of the embodiment of the present invention.

It is a block diagram which shows the structure of the multiplexing side apparatus of the signal multiplexing / demultiplexing apparatus by one Example of this invention. It is a block diagram which shows the structure of the isolation | separation side apparatus of the signal multiplexing / demultiplexing apparatus by one Example of this invention. It is a figure which shows the GbE signal input into the ports 1 and 2 of the signal multiplexing / demultiplexing apparatus by one Example of this invention. It is a figure which shows the output signal of PMA of FIG. It is a figure which shows the rearrangement signal in the multiplexing side apparatus of FIG. It is a figure which shows the output signal of the pointer insertion part of FIG. It is a figure which shows the output signal of the multiplexing part of FIG. It is a figure which shows an example of an output signal when the port 1 of the multiplexing side apparatus of FIG. 1 is disconnected. It is a figure which shows the output signal of the isolation | separation part of FIG. It is a figure which shows the output signal of the isolation | separation part of FIG. It is a block diagram which shows the structure of the multiplexing side apparatus of the signal multiplexing / demultiplexing apparatus by other Example of this invention. It is a block diagram which shows the structure of the isolation | separation side apparatus of the signal multiplexing / demultiplexing apparatus by other Example of this invention.

Explanation of symbols

1 Multiplexing device
3 Separation side devices 11, 11-1 to 11-n, 15,
36, 36-1 to 36-n, 40 PMA
12, 12-1 to 12-n, 16,
32, 32-1 to 32-n, 37 8B / 10B synchronization unit 13, 13-1 to 13-n, 17 Pointer insertion unit 14, 14-1 to 14-n, 18 Selection unit 19, 19-1 to 19 -N, 20 fixed pattern generator
21 Multiplexer
31 Separation unit 33, 33-1-33-n, 38 Pointer detection unit
34 Port selector 35, 35-1 to 35-n, 39 Fixed pattern detector

Claims (8)

A signal multiplexer / demultiplexer for demultiplexing signals from a plurality of ports at the level of 8B / 10B code,
On the multiplexing side, there is an insertion means for inserting a pointer indicating the port number of the signal into the idle code part included in the 8B / 10B code,
A signal multiplexing / demultiplexing device comprising a detecting means for detecting the pointer from the multiplexed signal on the demultiplexing side. The multiplex side includes means for detecting that the signal has been disconnected, and means for inserting a fixed pattern in place of the signal of the port where the input has been detected,
2. The signal multiplexing / demultiplexing according to claim 1, further comprising means for detecting the fixed pattern from the multiplexed signal and means for outputting an alarm when the fixed pattern is detected on the demultiplexing side. apparatus.   3. The signal multiplexing / demultiplexing apparatus according to claim 2, further comprising generating means for generating the fixed pattern on the multiplexing side.   4. The signal multiplexing / demultiplexing device according to claim 1, wherein the signal is a Gigabit Ethernet (registered trademark) signal. A signal multiplexing / demultiplexing method used in a signal multiplexing / demultiplexing apparatus that demultiplexes signals from a plurality of ports at the level of 8B / 10B code,
On the multiplexing side of the signal multiplexer / demultiplexer, a pointer indicating the port number of the signal is inserted into the idle code portion included in the 8B / 10B code,
A signal multiplexing / demultiplexing method comprising: detecting a pointer from a multiplexed signal on a separation side of the signal multiplexing / demultiplexing device. On the multiplexing side, when it is detected that the signal has been disconnected, a fixed pattern is inserted in place of the signal at the port where the input has been detected,
6. The signal multiplexer / demultiplexer according to claim 5, wherein an alarm is output when the fixed pattern is detected from the multiplexed signal on the demultiplexing side.   7. The signal multiplexing / demultiplexing apparatus according to claim 6, wherein the fixed pattern is generated on the multiplexing side.   The signal multiplexing / demultiplexing device according to claim 5, wherein the signal is a Gigabit Ethernet (registered trademark) signal.

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