JP2006295231A - Solid-state imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging apparatus capable of further enhancing an optical input dynamic range compared to a conventional device, and performing high-speed image pickup. <P>SOLUTION: This solid-state imaging apparatus is provided with a processing circuit for applying AD conversion to an output of a main imaging section of each pixel to generate a digital video signal; a one-dimensional row direction luminance profile acquiring circuit for adding an output of a row direction detecting imaging section of the pixel per pixel line, and generating a one-dimensional row direction luminance profile on the basis of the output added per pixel; a one-dimensional line direction luminance profile acquiring circuit for adding an output of a line direction detecting imaging section of the pixel per pixel row, and generating a one-dimensional line direction luminance profile on the basis of the output added per pixel; and a controller for generating a gain conversion signal of the processing circuit from the one-dimensional row direction luminance profile and the one-dimensional line direction luminance profile. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device.

A conventional solid-state imaging device is described in Patent Document 1 below. In the solid-state imaging device described in Patent Literature 1, it is possible to detect a two-dimensional position where light is incident as well as an image.
Japanese Patent No. 2003-189181

  However, in the conventional solid-state imaging device, the optical input dynamic range is determined by the characteristics of the elements constituting the solid-state imaging device.

  An object of the present invention is to provide a solid-state imaging device capable of further expanding the optical input dynamic range and capable of performing high-speed imaging as compared with the prior art.

  In the solid-state imaging device of the present invention, one pixel includes a main imaging unit, a column-direction detection imaging unit, and a row-direction detection imaging unit, and the imaging unit has an imaging region in which a plurality of the pixels are two-dimensionally arranged. The processing circuit that AD converts the output from the main imaging unit of each pixel to generate a digital video signal, and the output from the column direction detection imaging unit of the pixel is added for each pixel row, and is added for each pixel row A one-dimensional column direction luminance profile acquisition circuit that generates a one-dimensional column direction luminance profile based on the output and an output from the pixel row direction detection imaging unit are added for each pixel column, and the output is added for each pixel column A one-dimensional row-direction luminance profile acquisition circuit for generating a one-dimensional row-direction luminance profile based on the above, a gain conversion of a processing circuit from the one-dimensional column-direction luminance profile and the one-dimensional row-direction luminance profile The one-dimensional column direction luminance profile acquisition circuit includes a one-dimensional column direction luminance profile shift register for selecting a pixel row, and the one-dimensional row direction luminance profile acquisition circuit includes a pixel. A shift register for a one-dimensional row direction luminance profile for selecting a column is provided, and the processing circuit changes an AD conversion gain based on a gain conversion signal.

  According to the solid-state imaging device of the present invention, the controller uses the one-dimensional column direction luminance profile generated by the one-dimensional column direction luminance profile acquisition circuit and the one-dimensional row direction luminance generated by the one-dimensional row direction luminance profile acquisition circuit. A gain conversion signal of the processing circuit is generated from the profile. The one-dimensional column direction luminance profile acquisition circuit has a one-dimensional column direction luminance profile shift register for selecting a pixel row, and the one-dimensional row direction luminance profile acquisition circuit has a one-dimensional row for selecting a pixel column. Since the directional luminance profile shift register is included, the one-dimensional column-direction luminance profile acquisition circuit and the one-dimensional row-direction luminance profile acquisition circuit independently operate with respect to the imaging unit that generates the digital video signal. Can be set. That is, the one-dimensional column direction luminance profile and the one-dimensional row direction luminance profile are generated at a higher speed than the imaging unit that generates the digital video signal. As a result, the gain conversion signal of the processing circuit configured in the final stage of the imaging unit is generated at high speed.

  Therefore, the AD conversion gain of the processing circuit can be changed based on the gain conversion signal before the output from the main imaging unit is input to the processing circuit. That is, before the output from the main imaging unit is input to the processing circuit, the AD conversion gain of the processing circuit can be changed according to the light intensity input to the main imaging unit. Therefore, the optical input dynamic range of this solid-state imaging device can be expanded.

  The one-dimensional column direction luminance profile acquisition circuit of the present invention adds the output current from the pixel column direction detection imaging unit for each pixel row, and converts the output current added for each pixel row into a voltage. One-dimensional column direction for connecting the column direction detection imaging unit to the one-dimensional column direction luminance profile integration circuit for each pixel row, controlled by the direction luminance profile integration circuit and the one-dimensional column direction luminance profile shift register And a luminance profile switch. The one-dimensional row direction luminance profile acquisition circuit of the present invention adds the output current from the pixel row direction detection imaging unit for each pixel column, and adds the output current for each pixel column. The row direction detection imaging unit is controlled by a one-dimensional row direction luminance profile integration circuit that converts output current into voltage and a one-dimensional row direction luminance profile shift register. Further comprising a switch for one-dimensional row-direction luminance profile for connection to the one-dimensional row-oriented luminance profile for integrating circuit.

  According to this configuration, one one-dimensional column direction luminance profile integration circuit can generate a one-dimensional column direction luminance profile arranged in time series, and one one-dimensional row direction luminance profile integration circuit. Thus, a one-dimensional row direction luminance profile arranged in time series can be generated. Therefore, the mounting area on the circuit board of the one-dimensional column direction luminance profile acquisition circuit and the one-dimensional row direction luminance profile acquisition circuit can be reduced.

  The imaging region of the present invention is composed of K imaging blocks in which N pixel columns are arranged adjacent to each other, and the solid-state imaging device of the present invention performs partial readout according to an input digital video signal. Based on an output of the image data calculation unit, an image data calculation unit for designating a region, a row selection circuit for selecting a pixel row corresponding to the partial readout region, a column selection circuit for selecting a pixel column corresponding to the partial readout region, and an image data calculation unit And a timing generation circuit for generating a control signal for causing the row selection circuit and the column selection circuit to select, and the nth processing circuit switches to the main imaging unit of the nth pixel column in each imaging block. The N processing circuits are connected to the main imaging units of the N pixel columns via switches that are turned on by selection of the column selection circuit, respectively. And it is preferable to generate a digital video signal from the output of each pixel column of the main image pickup unit selected by the column selection circuit.

  According to this configuration, since the main imaging unit of the nth pixel column in each imaging block can be connected to the nth processing circuit via the switch, even when the partial readout area is small. The signals from the main imaging units in adjacent pixel columns are processed separately by different processing circuits. In addition, the image data calculation unit limits the imaging area to the partial readout area. Therefore, it is possible to perform high-speed imaging while expanding the optical input dynamic range.

  In addition, the solid-state imaging device of the present invention includes a plurality of hold circuits connected to the main imaging unit of each pixel column, and the switch is synchronized with a control signal input from the timing generation circuit to the column selection circuit. The charge accumulated in each hold circuit for each pixel column of the main imaging unit is connected to a processing circuit corresponding to the main imaging unit of each pixel column.

  According to this configuration, the output for each pixel row of the main imaging unit is temporarily accumulated in the hold circuit, and the charge accumulated for each pixel row of the main imaging unit is individually connected by connecting the switch with the control signal. Can be transferred to a processing circuit corresponding to the pixel column.

  According to the present invention, it is possible to provide a solid-state imaging device capable of further expanding the optical input dynamic range and capable of performing high-speed imaging as compared with the related art.

  DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals.

  FIG. 1 is a block diagram of a solid-state imaging device according to an embodiment. This solid-state imaging device includes an imaging element and a control circuit.

  This imaging element has an imaging region in which imaging blocks B1, B2, and B3 in which N pixel rows (N1, N2, and N3) are adjacently arranged are arranged in K pieces (K = 3 in this example). is doing. The order from the left of each imaging block is kth. FIG. 2 shows a detailed configuration of each pixel P (x, y) constituting each pixel column.

The pixel P (x, y) includes a photodiode PD1 (x, y), a reset switch Q _reset (x, y) connected between the cathode of the photodiode PD1 (x, y) and the reset potential Vr, and a photodiode. The amplifier AMP (x, y) with the cathode of PD1 (x, y) connected to the input terminal, and the address switch Q _address (x, y) connected between the amplifier AMP (x, y) and the video line L _n y).

By inputting a high-level shift signal (vertical) V _shift (y) to the address switch Q _address (x, y), the pixel signal amplified by the amplifier AMP (x, y) is transferred to the video line L _n . The state to do is possible. Photodiode PD1 (x, y) the charge accumulated in accordance with the amount of light incident on is amplified by the amplifier AMP (x, y), is output as a voltage to the video line _{L n.} Thereafter, when a high level reset signal (vertical) V _reset (y) is input to the reset switch Q _reset and turned on, the charge accumulated in the photodiode PD1 (x, y) is reset.

The pixel P (x, y) includes a photodiode PD2 (x, y) and a photodiode PD3 (x, y). The electric charge accumulated according to the amount of light incident on the photodiode PD2 (x, y) is output as a current to the column direction luminance profile line _LVPn . Photodiodes PD3 (x, y) accumulated charge according to the amount of light incident on is output as a current to _do the row direction luminance profile line L _HP.

  The pixel P (x, y) is formed on the semiconductor substrate and includes a main imaging unit, a column direction detection imaging unit, and a row direction detection imaging unit (for example, the main imaging unit, column direction detection). The imaging unit and the row direction detection imaging unit are areas surrounded by dotted lines). The photodiode PD1 (x, y), the photodiode PD2 (x, y), and the photodiode PD3 (x, y) are formed in the main imaging unit, the column direction detection imaging unit, and the row direction detection imaging unit, respectively. ing.

  The pixels P (x, y) in this example are nine along the row direction (x) and nine along the column direction (y), and are arranged in a two-dimensional manner defined by the address (x, y). Has been. In this example, a partial readout region R is set at the center of the imaging region, and a signal of a pixel P (x, y) inside the partial readout region R is read out.

  The partial read area R is designated by the image data calculation unit 10. The image data calculation unit 10 designates the partial readout region R according to the input digital video signal. That is, for example, the address of a pixel P (x, y) having a luminance equal to or higher than a predetermined value in an image of one frame in a digital video signal is stored. When an object such as a missile is an object to be imaged, the image sensor is made of silicon, and its infrared image spreads continuously around the center of gravity of the object image with the maximum luminance starting point, and the luminance is less than a predetermined value at the periphery. Become.

  That is, a rectangular area that includes a point with the maximum luminance and includes a point with a luminance within a predetermined value ± Δ is selected as the partial readout region R. When the object is moving, the difference between the position of the center of gravity of the object image in the previous frame (x1, y1) and the position of the center of gravity of the object image in the current frame (x2, y2) The vector (x2-x1, y2-y1) is calculated, and the position obtained by adding this vector to the centroid position (x1, y2) of the object image in the current frame is the centroid position (x3, y3) of the next object image. ) And a rectangular area having this as the center of gravity position is set as a new partial readout area R.

  A digital video signal is input to the image data calculation unit 10, and this digital video signal is obtained by processing signals for each pixel column (three columns) from each imaging block B1 (B2, B3) as processing circuits PU1, PU2. , PU3 can be obtained by inputting. Each processing circuit PU1, PU2, PU3 is formed by connecting amplifiers AMP1, AMP2, AMP3 and AD converters ADC1, ADC2, ADC3. The analog pixel signal output from each pixel column is converted into a digital video signal by the processing circuits PU1, PU2, and PU3.

  Partial image selection position information (x = x4 to x6, y = y4 to y6) that defines the partial readout region R is input to the timing generation circuit 11. In addition, the solid-state imaging device includes a row selection circuit 12 that selects a pixel row corresponding to the partial readout region R and a column selection circuit 13 that selects a pixel column corresponding to the partial readout region R. The timing generation circuit 11 generates a row selection circuit control signal and a column selection circuit control signal based on the input partial image selection position information.

  In short, the row selection circuit control signal causes the row selection circuit 12 to select a pixel so that the signal of the pixel row of y = y4 to y6 is read, and the column selection circuit control signal is the pixel column of x = x4 to x6. The column selection circuit 13 is made to select a pixel so that the above signal is read out. In other words, the timing generation circuit 11 generates a control signal that causes the row selection circuit 12 and the column selection circuit 13 to select based on the output of the image data calculation unit 10.

  FIG. 3 is a timing chart of the solid-state imaging device shown in FIG. In this example, an example of reading a signal of the partial reading region R shown in FIG. 1 is shown.

From time t _{0 to} t ₂ , the first to third shift signals (vertical) V _shift (1 to 3), the first to third reset signals (vertical) V _reset (1-3), the fourth shift signal ( (Vertical) V _shift (4), fourth reset signal (vertical) V _reset (4), fifth shift signal (vertical) V _shift (5), fifth reset signal (vertical) V _reset (5), sixth shift Signal (vertical) V _shift (6), sixth reset signal (vertical) V _reset (6), seventh to ninth shift signals (vertical) V _shift (7 to 9), seventh to ninth reset signals (vertical) ) V _reset (7-9), first shift signal (horizontal) H _shift (1), second shift signal (horizontal) H _shift (2), third shift signal (horizontal) H _shift (3) are all Low level. Each number in the signal indicates an address of coordinates x or y. In the description, FIG. 2 is referred to as appropriate.

At time t _{2 to} t ₃ , since the high-level fourth shift signal (vertical) V _shift (4) is input from the row selection circuit 12, the shift switch Q of the fourth pixel row from the bottom in FIG. _address (x, 4) is turned oN, the charge accumulated in the photodiode PD1 (x, 4) in accordance with the incident light is amplified by the amplifier aMP (x, 4), is output as a voltage to the video line _{L n} The hold circuits H (1) to H (9) hold. Each hold circuit is connected in parallel with a current source.

Subsequently, since the high-level fourth reset signal V _reset (4) is input at times t _{3 to} t ₄ , the reset switch Q _reset (x, 4) is turned on, and the photodiode PD1 (x, 4) is turned on. The accumulated charge is reset. At times t _{4 to} t ₅ , the high-level second shift signal (horizontal) H _shift (2) is _sent from the column selection circuit 13 to the fourth column switch Q (4) and the fifth pixel column. Switch Q (5) and the switch Q (6) in the sixth column of the pixel column are simultaneously input, so that the pixel P (4) accumulated in the hold circuits H (4), H (5), H (6) , 4), P (5, 4), and P (6, 4) are input to the processing circuits PU1, PU2, and PU3, respectively.

At time t _{6 to} t ₇ , the high-level fifth shift signal (vertical) V _shift (5) is input from the row selection circuit 12, so that the shift switch Q of the fifth pixel row from the bottom in FIG. _address (x, 5) is turned oN, the charge accumulated in the photodiode PD1 (x, 5) in response to the incidence of light is amplified by the amplifier aMP (x, 5), is output as a voltage to the video line _{L n} The hold circuits H (1) to H (9) hold.

Subsequently, since the high-level fifth reset signal V _reset (5) is input from time t _{7 to} time t ₈ , the reset switch Q _reset (x, 5) is turned on, and the photodiode PD1 (x, 5) is turned on. The accumulated charge is reset. At times t _{8 to} t ₉ , the high-level second shift signal (horizontal) H _shift (2) is _sent from the column selection circuit 13 to the fourth column switch Q (4) and the fifth pixel column. Switch Q (5) and the switch Q (6) in the sixth column of the pixel column are simultaneously input, so that the pixel P (4) accumulated in the hold circuits H (4), H (5), H (6) , 5), P (5, 5), and P (6, 5) are input to the processing circuits PU1, PU2, and PU3, respectively.

At time t _{10 to} t ₁₁ , the high-level sixth shift signal (vertical) V _shift (6) is input from the row selection circuit 12, so that the shift switch Q of the sixth pixel row from the bottom in FIG. _address (x, 6) is turned oN, the charge accumulated in the photodiode PD1 (x, 6) in response to the incidence of light is amplified by the amplifier aMP (x, 6), is output as a voltage to the video line _{L n} The hold circuits H (1) to H (9) hold.

Subsequently, since the high-level sixth reset signal V _reset (6) is input from time t _{11 to} t ₁₂ , the reset switch Q _reset (x, 6) is turned on, and the photodiode PD1 (x, 6) is turned on. The accumulated charge is reset. At time _t 12 _{~t 13,} the column select circuit 13, high-level second shift signal _{(horizontal) H Shift} (2) is, the fourth column of the switch Q (4) of the pixel column, the fifth column of the pixel row Switch Q (5) and the switch Q (6) in the sixth column of the pixel column are simultaneously input, so that the pixel P (4) accumulated in the hold circuits H (4), H (5), H (6) , 6), P (5, 6), and P (6, 6) are input to the processing circuits PU1, PU2, and PU3, respectively.

  As described above, the solid-state imaging device is connected to N pixel columns via the switches Q (4), Q (5), and Q (6) that are turned on by selection of the column selection circuit 13, respectively. N processing circuits PU1, PU2, and PU3 are provided. The n-th processing circuit PU1 (PU2, PU3) is all connected to the n-th pixel column N1 (N2, N3) in each imaging block B1, B2, B3 via the switches Q (1) to Q (9). It is possible to connect. The N processing circuits PU1, PU2, and PU3 generate digital video signals from signals for each pixel column selected by the row selection circuit 12 and the column selection circuit 13.

  According to the above-described solid-state imaging device, the n-th processing circuit (for example, PU1) includes the n-th pixel column (N1) in each of the imaging blocks B1, B2, and B3 as switches Q (1) and Q Since all the connections are possible via (4) and Q (7), even when the partial readout region R is small, signals from the adjacent pixel column N2 are processed separately by different processing circuits PU2. . In addition, since the image data calculation unit 10 limits the area to be read out to the partial read area R, it is possible to perform higher-speed imaging.

  The solid-state imaging device includes a plurality of hold circuits H (1) to H (9) connected to the individual pixel columns N1, N2, and N3, and the switches Q (1) to Q ( 9) The charges accumulated in the individual hold circuits H (1) to H (9) for each pixel column are synchronized with the control signal input from the timing generation circuit 11 to the column selection circuit 13, and The signals are connected to the processing circuits PU1, PU2, PU3 corresponding to the pixel columns N1, N2, N3, and the signals of each pixel row are temporarily stored in the hold circuits (1) to H (9). By connecting with the control signals Q (1) to Q (9), the charges accumulated in each pixel row can be transferred to the processing circuits PU1, PU2, PU3 for each pixel column N1, N2, N3. .

  In the present embodiment, the processing circuits PU1, PU2, and PU3 have a one-dimensional column direction luminance profile generated by the one-dimensional column direction luminance profile acquisition circuit 14 and a one-dimensional row direction generated by the one-dimensional row direction luminance profile acquisition circuit 15. The AD conversion gain can be changed based on the luminance profile.

  FIG. 4 is a diagram illustrating a configuration of the one-dimensional column direction luminance profile acquisition circuit 14. As shown in FIG. 4, the one-dimensional column direction luminance profile acquisition circuit 14 includes a one-dimensional column direction luminance profile switch (hereinafter referred to as column direction switch) 31 and a one-dimensional column direction luminance profile shift register (hereinafter referred to as column). And a one-dimensional column direction luminance profile integrating circuit (hereinafter referred to as a column direction integrating circuit) 33.

Column direction luminance profile lines L _{VP1 to} L _VP9 are connected to one terminal of the column direction switch 31, respectively. Column luminance profile line _{L VP1} is connected to the photodiode PD2 (1,1) ~PD2 (9,1) which are arranged in pixel rows M1. Similarly, the column-direction luminance profile lines L _VP2 , L _VP3 ,..., L _VP9 are photodiodes PD2 (1,2) to PD2 (9,2), PD2 () arranged in the pixel rows M2, M3,. 1, 3) to PD2 (9, 3),..., PD2 (1, 9) to PD2 (9, 9), respectively. The other terminal of the column direction switch 31 is connected to the input terminal of the column direction integration circuit 33.

The column direction switch 31 is controlled by shift signals shift (V1) to shift (V9) output from the column direction shift register 32, and is sequentially closed. The column direction shift register 32 generates shift signals shift (V1) to shift (V9) in synchronization with an externally input clock. The column direction integration circuit 33, sequentially read photodiode PD2 (x, 1) by column shift register 32 ～PD2 current from (x, 9) is, and the column luminance profile line _L VP1 _{~L VP9} The data are sequentially input via the column direction switch 31. The column direction integration circuit 33 sequentially converts these currents into voltages, and generates a voltage signal Vout.

  The column direction integration circuit 33 includes an amplifier 34, a capacitor 35 connected between the input terminal and the output terminal of the amplifier 34, and a column direction integration switch 36 connected between the input terminal and the output terminal of the amplifier 34. Including. The column direction integration switch 36 is turned on by receiving a high level reset signal ΦVreset from the outside, and can initialize the potential of the capacitor 35.

FIG. 5 is a time chart of the one-dimensional column direction luminance profile acquisition circuit 14. First, when the high-level shift signal shift (V1) is input to the column direction switch 31, the column direction switch 31 is turned ON, and the charge accumulated in the photodiodes PD2 (1,1) to PD2 (9,1) The corresponding current is input to the amplifier 34 of the column direction integration circuit 33 via the column direction luminance profile line _LVP1 and the column direction switch 31. When the reset signal ΦVreset is at a low level, the column direction integration switch 36 is turned OFF, and the charges of the photodiodes PD2 (1,1) to PD2 (9,1) are accumulated in the capacitor 35. The column direction integration circuit 33 outputs a voltage corresponding to this charge from the output terminal.

  Next, when the reset signal ΦVreset becomes high level, the column direction integration switch 36 is turned on, and the capacitor 35 is initialized. Thereafter, the shift signal shift (V1) becomes a low level, and the column direction switch 31 is turned OFF. Thereafter, the reset signal ΦVreset becomes low level, and the column direction integration switch 36 is turned OFF. That is, the column direction integration circuit 33 waits for the next input signal.

Next, when the high-level shift signal shift (V2) is input to the column direction switch 31, the column direction switch 31 is turned ON, and the charges accumulated in the photodiodes PD2 (1,2) to PD2 (9,2). Is input to the amplifier 34 of the column direction integration circuit 33 via the column direction luminance profile line _LVP2 and the column direction switch 31. When the reset signal ΦVreset is at a low level, the column direction integration switch 36 is turned OFF, and the charges of the photodiodes PD2 (1,2) to PD2 (9,2) are accumulated in the capacitor 35. The column direction integration circuit 33 outputs a voltage corresponding to this charge from the output terminal.

  Next, when the reset signal ΦVreset becomes high level, the column direction integration switch 36 is turned on, and the capacitor 35 is initialized. Thereafter, the shift signal shift (V2) becomes a low level, and the column direction switch 31 is turned OFF. Thereafter, the reset signal ΦVreset becomes low level, and the column direction integration switch 36 is turned OFF. That is, the column direction integration circuit 33 waits for the next input signal.

Similarly, in accordance with a shift signal shift (V3) ~shift (V9) , by repeating the above-described operation, lined voltage corresponding to the current from the column luminance profile line _{L VP1} ~L _VP9 is chronologically A one-dimensional column direction luminance profile Vout is generated.

  FIG. 6 is a diagram showing a configuration of the one-dimensional row direction luminance profile acquisition circuit 15. As shown in FIG. 6, the one-dimensional row direction luminance profile acquisition circuit 15 includes a one-dimensional row direction luminance profile switch (hereinafter referred to as row direction switch) 21 and a one-dimensional row direction luminance profile shift register (hereinafter referred to as row). And a one-dimensional row direction luminance profile integration circuit (hereinafter referred to as a row direction integration circuit) 23.

Row direction luminance profile lines L _{HP1 to} L _HP9 are respectively connected to one terminal of the row direction switch 21. The row direction luminance profile line L _HP1 is connected to the photodiodes PD2 (1,1) to PD2 (1,9) arranged in the pixel column N1. Similarly, the row direction luminance profile lines L _HP2 , L _HP3 ,..., L _HP9 are photodiodes PD3 (2,1) to PD3 (2,9), PD3 () arranged in the pixel columns N2, N3,. 3,1) to PD3 (3,9),..., PD3 (9,1) to PD3 (9,9), respectively. The other terminal of the row direction switch 21 is connected to the input terminal of the row direction integration circuit 23.

The row direction switch 21 is controlled by shift signals shift (H1) to shift (H9) output from the row direction shift register 22, and is sequentially closed. The row direction shift register 22 generates shift signals shift (H1) to shift (H9) in synchronization with an externally input clock. In the row direction integration circuit 23, currents from the photodiodes PD3 (1, y) to PD3 (9, y) sequentially read out by the row direction shift register 22 are supplied to the row direction luminance profile lines L _{HP1 to} L _HP9 and The data are sequentially input via the row direction switch 21. The row direction integration circuit 23 sequentially converts these currents into a voltage signal Hout.

  The row direction integration circuit 23 includes an amplifier 24, a capacitor 25 connected between the input terminal and the output terminal of the amplifier 24, and a row direction integration switch 26 connected between the input terminal and the output terminal of the amplifier 24. Including. The row direction integration switch 26 is turned on by receiving a high level reset signal ΦHreset from the outside, and can initialize the potential of the capacitor 25.

FIG. 7 is a time chart of the one-dimensional row direction luminance profile acquisition circuit 15. First, when a high-level shift signal shift (H1) is input to the row direction switch 21, the row direction switch 31 is turned on, and the charge accumulated in the photodiodes PD3 (1,1) to PD3 (1,9) is changed. The corresponding current is input to the amplifier 24 of the row direction integration circuit 23 via the row direction luminance profile line _LHP1 and the row direction switch 21. When the reset signal ΦHreset is at a low level, the row direction integration switch 26 is turned OFF, and charges of the photodiodes PD3 (1,1) to PD3 (1,9) are accumulated in the capacitor 25. The row direction integration circuit 23 outputs a voltage corresponding to this charge from the output terminal.

  Next, when the reset signal ΦHreset becomes high level, the row direction integration switch 26 is turned on, and the capacitor 25 is initialized. Thereafter, the shift signal shift (H1) becomes a low level, and the row direction switch 21 is turned OFF. Thereafter, the reset signal ΦHreset becomes low level, and the row direction integration switch 26 is turned OFF. That is, the row direction integration circuit 23 waits for the next input signal.

Next, when the high-level shift signal shift (H2) is input to the row direction switch 21, the row direction switch 21 is turned on, and the charges accumulated in the photodiodes PD3 (2, 1) to PD3 (2, 9) are turned on. Is input to the amplifier 24 of the row direction integration circuit 23 via the row direction luminance profile line _LHP2 and the row direction switch 21. When the reset signal ΦHreset is at a low level, the row direction integration switch 26 is turned OFF, and the charges of the photodiodes PD3 (2,1) to PD3 (2,9) are accumulated in the capacitor 25. The row direction integration circuit 23 outputs a voltage corresponding to this charge from the output terminal.

  Next, when the reset signal ΦHreset becomes high level, the row direction integration switch 26 is turned on, and the capacitor 25 is initialized. Thereafter, the shift signal shift (H2) becomes low level, and the row direction switch 21 is turned OFF. Thereafter, the reset signal ΦHreset becomes low level, and the row direction integration switch 26 is turned OFF. That is, the row direction integration circuit 23 waits for the next input signal.

Similarly, in accordance with a shift signal shift (H3) ~shift (H9) , by repeating the above-described operation, the voltage corresponding to the current from the row luminance profile line _{L HP1} ~L _HP9 took the time series A one-dimensional row direction luminance profile Hout is generated.

  The one-dimensional column direction luminance profile Vout and the one-dimensional row direction luminance profile Hout are input to the controller 16. FIG. 8 is a circuit block diagram of the controller 16. The controller 16 shown in FIG. 8 includes profile timing generation circuits PT1 and PT2, switches SW1 and SW2, comparators Comp1 and Comp2, a NAND circuit Nand, a hold circuit Hold, and a reset transistor Tr.

FIG. 9 is a time chart showing waveforms of each part of the control 16. Hereinafter, the controller 16 will be described in detail with reference to FIGS. 8 and 9. Profile timing generating circuit PT1, in order to enter the one-dimensional column intensity profile portion _{V PR} corresponding 1-dimensional column intensity profile Vout time-sequentially juxtaposed to the partial readout area R to the comparator Comp1, controls the switch SW1 Output a signal. For example, the profile timing generation circuit PT1 responds to a frequency ratio between a clock input to the one-dimensional column direction luminance profile acquisition circuit 14 and a clock V _clk (described later in FIG. 14) input to the row selection circuit 12. Thus, a compressed column direction control signal V _comp obtained by compressing the row selection circuit control signal output from the timing generation circuit 11 in the time direction is output.

Switch SW1 is turned ON in response to the high level compression column direction control signal _{V comp,} and inputs the one-dimensional column intensity profile portion _{V PR} to the first input terminal of the comparator Comp1. The reference voltage V _ref1 is input to the second input terminal of the comparator Comp1. The comparator Comp1 has a one-dimensional column intensity profile is compared with the part _{V PR} and the reference voltage _{V ref1,} and outputs a high level voltage when the one-dimensional column intensity profile portion _{V PR} is greater than the reference voltage _{V ref1} outputs a low level voltage when the one-dimensional column intensity profile portion _{V PR} is less than the reference voltage _{V ref1.}

Profile timing generating circuit PT2, in order to enter the one-dimensional row luminance profile portion H _PR corresponding since one-dimensional row-direction luminance profile Hout arranged in series in the partial readout area R to the comparator Comp2, controls the switch SW2 Output a signal. For example, the profile timing generation circuit PT2 corresponds to a frequency ratio between a clock input to the one-dimensional column direction luminance profile acquisition circuit 14 and a clock H _clk (described later in FIG. 17) input to the column selection circuit 13. Thus, a compressed row direction control signal H _comp obtained by compressing the column selection circuit control signal output from the timing generation circuit 11 in the time direction is output.

Switch SW2 is turned ON in response to the compression row direction control signal _{H comp} high level, inputs the one-dimensional row luminance profile portion _{H PR} to the first input terminal of the comparator Comp2. The reference voltage V _ref2 is input to the second input terminal of the comparator Comp2. The comparator Comp2 is a one-dimensional row luminance profile comparing part _{H PR} and the reference voltage _{V ref2,} it outputs a one-dimensional row luminance profile portion _{H PR} high-level voltage when is greater than the reference voltage _{V ref2,} 1 outputs a low level voltage when the dimension row luminance profile portion H _PR is less than the reference voltage V _ref2.

  The NAND circuit Nand receives the output voltage of the comparator Comp1 and the output voltage of the comparator Comp2. The NAND circuit Nand outputs a high level voltage when both of these voltages are at a high level, and outputs a low level voltage when either of these voltages is at a high level and both of these voltages are at a low level. To do. The output voltage of the NAND circuit Nand is held by the hold circuit Hold. In other words, the output voltage of the NAND circuit Nand is held at a high level once it reaches a high level. Note that the hold circuit Hold may be formed of a capacitor.

The hold circuit Hold holds the output voltage of the NAND circuit Nand until the processing circuits PU1, PU2, and PU3 generate digital video signals. After the processing circuits PU1, PU2, and PU3 generate digital video signals, the reset transistor Tr is turned on by the high-level reset signal C _reset , and the voltage of the hold circuit Hold is initialized. The output voltage of the NAND circuit Nand is a gain conversion signal and is input to each processing circuit PU1, PU2, PU3.

  FIG. 10 is a block diagram illustrating the processing circuit. FIG. 10 shows the processing circuit PU1, but the processing circuits PU2 and PU3 are the same. The processing circuit PU1 includes an amplifier Amp1 and ADC1. In the present embodiment, the ADC 1 is a pipeline type ADC. The ADC 1 includes twelve basic blocks BLK1 (1), BLK2 (1),..., BLK12 (1), a delay circuit Delay (1), and a decoder Decoder (1). The basic block BLK1 (1) includes a sample hold circuit SH (1), ADC (1), DAC (1), an adder ADD (1), and a double amplifier BAY (1).

  The voltage input to the processing circuit PU1 is amplified by the amplifier Amp1 and input to the ADC1. The voltage input to the ADC 1 is sampled by the sample hold circuit SH (1) of the basic block B1, and is input to the ADC (1) and the adder ADD (1). The ADC (1) converts the input voltage into a digital signal (1 or 0). This digital signal is output to the delay circuit Delay (1) and converted into a voltage by the DAC (1).

  The adder ADD (1) adds the voltage from the sample hold circuit SH (1) and the voltage from the DAC (1). The added voltage is amplified twice by the double amplifier BAY (1) and input to the basic block BLK2 (1). The basic blocks BLK2 (1) to BLK12 (1) have the same configuration as the basic block BLK1 (1), and each generate a digital signal.

  The digital signals output from the basic blocks BLK1 (1) to BLK12 (1) have different delays through the delay circuit Delay (1). In the decoder Decoder (1), the digital signal output from the basic block BLK1 (1) is the most significant bit, and the digital signals output from the basic blocks BLK1 (1) to BLK12 (1) are sequentially arranged to form a 12-bit digital signal. Generate a video signal.

  Each of the basic blocks BLK1 (1) to BLK12 (1) may be configured by a switched capacitor circuit including a capacitor and an amplifier, and the delay circuit Delay (1) may be configured by a shift register. Note that the delay of each bit is adjusted by the number of shift registers.

  The ADC 1 of the processing circuit PU1 can change the AD conversion gain in response to the gain conversion signal from the controller 16. When a high level gain conversion signal is input to the ADC 1 of the processing circuit PU1, this high level gain conversion signal is input to the basic blocks BLK1 (1) to BLK12 (1). Hereinafter, the operation of the basic block BLK1 (1) will be described, but the operations of the basic blocks BLK2 (1) to BLK12 (1) are the same.

  When a high-level gain conversion signal is input to the ADC (1), the comparison reference potential (not shown) of the ADC (1) becomes a high potential, and the basic block BLK1 (1) has a low gain. Similarly, the basic blocks BLK2 (1) to BLK12 (1) also have a low gain. Therefore, the ADC 1 has a low gain. Therefore, the AD conversion gain of the processing circuit PU1 is reduced. When a low level gain conversion signal is input to the ADC 1 of the processing circuit PU1, this low level gain conversion signal is input to the basic blocks BLK1 (1) to BLK12 (1). When the low-level gain conversion signal is input to the ADC (1), the comparison reference potential (not shown) of the ADC (1) becomes a low potential, and the basic block BLK1 (1) becomes a high gain. Similarly, the basic blocks BLK2 (1) to BLK12 (1) also have a high gain. Therefore, the ADC 1 has a high gain. Therefore, the AD conversion gain of the processing circuit PU1 increases.

  The processing circuits PU2 and PU3 can also change the AD conversion gain by receiving the gain conversion signal, similarly to the processing circuit PU1.

  According to the solid-state imaging device of this embodiment, the controller 16 is generated by the one-dimensional column direction luminance profile Vout generated by the one-dimensional column direction luminance profile acquisition circuit 14 and the one-dimensional row direction luminance profile acquisition circuit 15. From the one-dimensional row direction luminance profile Hout, gain conversion signals of the processing circuits PU1, PU2, and PU3 are generated.

  The one-dimensional column direction luminance profile acquisition circuit 14 includes a one-dimensional column direction luminance profile shift register 32 for selecting a pixel row, and the one-dimensional column direction luminance profile acquisition circuit 15 selects a pixel column. Since the shift register 22 for the one-dimensional row direction luminance profile is provided, the one-dimensional column direction luminance profile acquisition circuit 14 and the one-dimensional row direction luminance profile acquisition circuit 15 are provided with respect to the imaging unit that generates the digital video signal. The operation speed can be set independently.

  That is, the one-dimensional column direction luminance profile Vout and the one-dimensional row direction luminance profile Hout are generated at a higher speed than the imaging unit that generates the digital video signal. As a result, gain conversion signals of the processing circuits PU1, PU2, and PU3 configured in the final stage of the imaging unit are generated at high speed.

  Therefore, the AD conversion gains of the processing circuits PU1, PU2, and PU3 can be changed based on the gain conversion signal before the output from the main imaging unit is input to the processing circuits PU1, PU2, and PU3. That is, before the output from the main imaging unit is input to the processing circuits PU1, PU2, and PU3, the AD conversion gains of the processing circuits PU1, PU2, and PU3 are changed according to the light intensity input to the main imaging unit. can do. Therefore, the optical input dynamic range of this solid-state imaging device can be expanded.

  FIG. 11 is a diagram illustrating optical input-digital video signal characteristics of the solid-state imaging device according to the present embodiment. As described above, when light of less than a predetermined value is input, the AD conversion gain of the processing circuits PU1, PU2, and PU3 is increased. When light of a predetermined value or more is input, the processing circuits PU1, PU2, and PU3 are increased. By reducing the AD conversion gain, the optical input range is expanded. That is, the optical input dynamic range is expanded.

  When the digital video signal is reproduced, the digital video signal may be reproduced according to whether or not the gains of the processing circuits PU1, PU2, and PU3 are switched by referring to the variable gain signal.

  In FIG. 12, one imaging block is composed of 8 pixel columns, and includes 64 imaging blocks Bk (k = 1 to 64) (K = 64), and the vertical pixel column has 512 pixels. The solid-state imaging device which has a pixel row of a horizontal direction has 512 pixels is shown. Note that the nth processing circuit PUn is connected to each nth pixel column in each of the imaging blocks B1, B2,..., B64 (n = 1 to 8).

  Hold circuit groups H (1) to H (N × K) are interposed between the switch groups Q (1) to Q (N × K) controlled by the column selection circuit 13 and the imaging region. . The switch groups Q (1) to Q (N × K) and the hold circuit groups H (1) to H (N × K) are the above switch groups Q (1) to Q (9) and the hold circuit group H (1 ) To H (9).

  The operation of partial reading with this solid-state imaging device will be described below. Here, partial readout of the central 492 × 492 pixels excluding only the peripheral 10 rows and 10 columns out of the entire 512 × 512 pixels from the previous image based on the output of the image data calculation unit is performed. The timing generation circuit supplies a control signal necessary for the selection to the row selection circuit 12 and the column selection circuit 13.

  FIG. 13 is a detailed circuit diagram of the main imaging unit of the pixel P (x, y). In the following description, a switch refers to a field effect transistor.

The main imaging unit of the pixel P (1,1) includes a transfer switch Q _trans (1) and a reset switch Q _reset (1) interposed in series between the cathode of the photodiode PD1 (1) and the reset potential Vr1. ing. The upstream end of the transfer switch Q _trans (1) is input to the gate of the amplification transistor Q _amp (1) via the hold switch Q _hold (1). An address switch Q _address (1) is interposed between the amplification transistor Q _amp (1) and the video line L ₁ .

The transfer signal V _trans (1) is input to the gate of the transfer switch Q _trans (1), and the reset signal V _reset (1) is input to the gate of the reset switch Q _reset (1). The hold signal V _hold (1) is input to the gate of the hold switch Q _hold (1). An address signal V _address (1) is input to the gate of the address switch Q _address (1). The address signal V _address (1) can also be expressed as a first shift signal (vertical) V _shift (1).

  The configuration of the main imaging unit of the pixel P (1,2) is the same as the configuration of the main imaging unit of the pixel P (1,1) except that the number of each element is “2”. The column direction detection imaging unit and the row direction detection imaging unit of the pixel P (x, y) are the same as those in FIG.

  FIG. 14 is a circuit diagram of the row selection circuit 12 for generating each signal. FIG. 15 is a timing chart of each signal. This figure is for achieving partial readout of the central 492 rows excluding the upper and lower 10 rows in the vertical direction.

Shift registers S1, S2,... Are provided for each row, and each shift register includes a set input terminal ST, a reset input terminal rst, a clock input terminal CLK, and an output terminal Q. The reset input terminal is connected to the ground potential. The set input terminal ST of the shift register S1 is the start signal V _st is input, the output shiftout1 from the output terminal Q of the shift register S1 is, as that is input to the set input terminal of the shift register S2 ST, each shift register The set input terminal sequentially receives the output from the output terminal Q of the previous shift register.

V _reset , V _trans , V _hold , and V _address generated from the timing generation circuit 11 are predetermined timings at the time of reading the first pixel P (1, 1), respectively, and V _reset (1), V _trans (1), As V _hold (1) and V _address (1), the switches QA1, QB1, QC1, and QD1 are turned on and input to the above-described switches. This predetermined timing is determined by the s-mode signal generated by the timing generation circuit 11 and the start signal _Vst , and when the reading of the pixels in the first row is completed, the reading of the pixels in the second row is sequentially performed. Transition.

In FIG. 15, the number indicated by (V _shift ) indicates the pixel row being read, and the number indicated by (H _shift ) indicates the pixel column being read.

The s-mode signal is input to the OR circuit (OR1) together with the output when the start signal _Vst is input to the shift register S1. In the case of reading in the second row, these signals are input to the OR circuit (OR2).

This figure shows an example of operation in the global shutter mode in which the charges accumulated in the photodiodes PD1 (x, y) are simultaneously held in all the 512 × 512 pixels. By setting the s-mode signal to the high level, V _Reset , V _trans , and V _hold signals can be supplied all at once. As a result, the charge accumulated in the photodiode PD1 (x, y) can be transferred and accumulated in the gate of the amplification transistor Q _amp (x, y) over the entire pixel at the same timing.

The actual operation is as follows. The s-mode signal is set to a high level so that signals of V _reset , V _trans , and V _hold are input over all rows. When all signals of V _reset , V _trans , V _hold , and V _address are at a low level, the charge of the gate of the amplification transistor is reset by setting V _reset to a high level and V _hold to a high level. After V _{hold is set} to low level and V _{reset is set} to low level, V _{trans is set} to high level and V _{hold is set} to high level, whereby the charge accumulated in the photodiode PD1 (x, y) is transferred to the gate of the amplification transistor. Transferred.

_Then, after the _{V trans} low level in the _{V hold} in a low _level, and the _{V trans} and _{V reset} to the high level, the photodiode PD1 (x, y) after resetting the electric charges accumulated _{in, V trans} and V _{Reset is set} to low level to start the next accumulation.

  Here, by returning the s-mode signal to the low level, the charges accumulated in the photodiode PD1 (x, y) over all the pixels are transferred and held in the gate of the amplification transistor of each pixel. In the photodiode, the next accumulation is started, and the operation in the global shutter mode in which the accumulation starts and ends in all the pixels is realized at the same time. Thereafter, only the pixel for which the charge held at the gate of the amplification transistor is to be read is selected and read.

The vertical clock signal V _clk generated by the timing generation circuit 11 is input to the clock input terminals CLK of the shift registers S1, S2 _,. Start signal V _st is input to the set input terminal of the shift register S1, so that the output shiftout1 from the output terminal Q of the shift register S1 is input to the set input terminal of the shift register S2, the set input terminal of each shift register When the output from the output terminal Q of the previous shift register is sequentially input, the reading of the charges accumulated in the pixels of each row is started, but V _address is set to the low level, and the vertical clock signal V _clk is By shortening the period, the first 10 lines skip signals.

Thereafter, the voltage obtained by amplifying the accumulated charges from the pixels in the eleventh row by setting _Vaddress to high level is once transferred to the hold circuit and held in the hold circuit. The charge of 512 pixels is accumulated in the hold circuit by _extending the period of the vertical clock signal V _clk , and then the pixel column read start signal H _st generated by the timing generation circuit 11 is input to the column selection circuit 13. Thus, among the charges accumulated in the hold circuit for 512 pixels in synchronization with the horizontal clock signal H _clk generated by the timing generation circuit 11, eight processing circuits are provided for the pixel corresponding to the selected partial readout region R. Are input to the image data calculation unit. This operation will be described later with reference to FIGS. Note that in the subsequent 10 rows from the 503th pixel row, the period of the vertical clock signal is shortened and signal reading is similarly skipped.

That is, by shortening the period of the vertical clock signal, the readout time of unnecessary pixel rows is shortened. In the readout period of unnecessary pixel rows, the address signal V _address is not input, that is, the video signal is Not output.

FIG. 16 is a circuit diagram of the switch groups Q (1) to Q (N × K) for reading out the charges accumulated in the hold circuit groups H (1) to H (N × K). Video lines _{L 1, L 2, L 3} ··· L N × K every switch Q (1), Q (2 ), Q (3) ··· Q (N × K) is connected. The H _shift signal is input to the switch group of one imaging block, and the charge accumulated in the hold circuit is read when the H _shift signal is at a high level.

FIG. 17 is a circuit diagram of the column selection circuit 13 for generating each signal. FIG. 18 is a timing chart of each signal. This figure is for achieving partial reading of only the central 492 columns excluding 10 columns on the left and right in the horizontal direction. This figure shows only the timing at which the horizontal start signal _Hst goes high after the s-mode signal in FIG.

  Shift registers S10, S20, S30... Are provided corresponding to the imaging blocks. Each shift register includes a set input terminal ST, a reset input terminal rst, a clock input terminal CLK, and a Q output terminal. The horizontal clock signal Hclk is input to the clock input terminal CLK.

  The timing generation circuit generates a horizontal readout start signal Hst corresponding to the pixel of the desired readout start number in the 64 imaging blocks and inputs it to the 6-bit decoder (0ch to 63ch) D. The decoder D includes binary input terminals dih0, dih1, dih2, dih3, dih4, and dih5. An OR circuit is interposed between the decoder output terminals 1, 2, 3... And each set input terminal ST.

The decoder D generates a signal in which the H _shift signal input to a desired imaging block becomes a high level in response to H _st and binary input generated by the timing generation circuit 11. And a start signal _{H st,} by the imaging block specifying signal dih0, dih1, dih2, dih3, dih4, dih5 inputs, signals of the pixel column of the given imaging block is read. The H _shift (1) signal generated in response to the decoder output terminal 0 turns on the switches Q (1) to Q (8) when it is at the high level, and the H _shift (2) generated in response to the decoder output terminal 1 ) When the signal is at a high level, the switches Q (9) to Q (16) are turned ON.

The all reset signal H _shift-reset generated by the timing generation circuit 11 can be input to the reset terminal rst of each of the shift registers S10, S20, and S30. If the H _shift-reset is at a high level, the hold signal is held. The readout of the charges accumulated in the circuit is finished, and partial readout is performed at high speed. Thus, by applying both the methods of FIG. 15 and FIG. 18, partial signal readout of the center 492 × 492 pixels can be achieved by removing the 512 × 512 pixel signal by 10 peripheral rows and 10 columns.

  On the other hand, the one-dimensional column direction luminance profile acquisition circuit 14 includes a column direction shift register 32 and 512 column direction switches 31 for acquiring the one-dimensional column direction luminance profile Vout of the column direction detection imaging unit of 512 pixel rows. And have. The column direction shift register 32 outputs shift signals shift (V1) to shift (V512) synchronized with a clock input from the outside, and sequentially turns 512 column direction switches 31 on.

That is, the one-dimensional column direction luminance profile acquisition circuit 14 performs the operation described with reference to FIG. 5 over 512 pixel rows, so that the voltage corresponding to the current from the column direction luminance profile lines L _{VP1 to} L _{VP512 is timed.} Generate one-dimensional column direction luminance profile Vout arranged in series

  The one-dimensional row direction luminance profile acquisition circuit 15 includes a row direction shift register 22 for acquiring a one-dimensional row direction luminance profile Vout of 512 pixel columns and 512 row direction switches 21. The row direction shift register 22 outputs shift signals shift (H1) to shift (H512) synchronized with a clock input from the outside, and sequentially turns on the 512 row direction switches 21.

That is, one-dimensional row-direction luminance profile acquisition circuit 15, by performing over the pixel columns of the operation 512 described with reference to FIG. 7, time is a voltage corresponding to the current from the row luminance profile line L _HP1 ~L _HP512 A one-dimensional row direction luminance profile Hout arranged in a series is generated.

The one-dimensional column direction luminance profile Vout and the one-dimensional row direction luminance profile Hout are input to the controller 16. The controller 16, as described in FIGS. 8 and 9, one-dimensional and column luminance profile portion V _PR corresponding to the partial readout area R, and the one-dimensional row-direction luminance profile portion H _PR corresponding to the partial readout area R When both of the voltages are equal to or higher than a predetermined value, a gain conversion signal that becomes a high level is generated. The gain conversion signal is input to each of the processing circuits PU1 to PU8. These processing circuits PU1 to PU8 change the AD conversion gain based on the gain conversion signal.

  In this embodiment, the image acquisition time is about 3.96 ms, whereas the profile acquisition time is about 0.63 ms. Therefore, according to the present embodiment, it is possible to change the AD conversion gain of the processing circuits PU1 to PU8 before a signal corresponding to the accumulated charge of the main imaging unit is input to the processing circuits PU1 to PU8.

  In the above example, the AD conversion gain of the processing circuit PU1 is changed by changing the AD conversion gain of the ADC1 provided in the processing circuit PU1, but the amplification gain of the amplifier Amp1 provided in the processing circuit PU1 is changed. Thus, the AD conversion gain of the processing circuit PU1 may be changed.

  FIG. 19 is a diagram illustrating a configuration of a processing circuit having an amplifier capable of varying the amplification gain. As illustrated in FIG. 19, the amplifier Amp1 includes an amplifier Amp1 (1). Between the input terminal and the output terminal of the amplifier Amp1 (1), a parallel circuit of the switch SW (1) and the resistor R (1), and a parallel circuit of the switch SW (2) and the resistor R (2) Are connected in series. The switch SW (1) is controlled by a gain conversion signal, and the switch SW (2) is controlled by a gain conversion signal via the inverter Inv (1).

  When the gain conversion signal is at a low level, the switch SW (1) is turned off and the switch SW (2) is turned on, so that the amplifier Amp1 has an amplification gain corresponding to the resistor R (1). When the gain conversion signal is at a high level, the switch SW (11) is turned on and the switch SW (2) is turned off, so that the amplifier Amp1 has an amplification gain corresponding to the resistor R (2).

  If the resistance value of the resistor R (2) is smaller than the resistance value of the resistor R (1), the amplification gain of the amplifier Amp1 is higher when the gain conversion signal is high than when the gain conversion signal is low. Can be reduced. That is, when the gain conversion signal is at a high level, the AD conversion gain of the processing circuit PU1 can be reduced compared to when the gain conversion signal is at a low level. The processing circuits PU2 to PU8 are configured similarly.

  In this configuration, the parallel circuit of the switch SW (1) and the resistor R (1), the switch SW (2) and the resistor R (2) are provided between the input terminal and the output terminal of the amplifier Amp1 (1). Are connected in series, but a series circuit of a switch SW (1) and a resistor R (1) between the input terminal and the output terminal of the amplifier Amp1 (1). And what connected switch SW (2) and the series circuit of resistance R (2) in parallel may be connected.

  FIG. 20 is a diagram illustrating the hold circuit groups H (1) to H (N × K), the switch groups Q (1) to Q (N × K), and the processing circuit PU. FIG. 20 is a diagram in which a part is omitted.

  A voltage Vsignal obtained by amplifying the charge accumulated in the photodiode P (1,1) shown in FIG. 13 by the amplification transistor Qamp (1) is held in the hold circuit H (1).

  During the above-described hold operation, hrset1 is set to the high level, and the input / output of amp1 is reset to the same potential as the DC voltage Vref. Thereafter, when reset1 is set to low level and the shift signal Hshift (1) is set to high level, the voltage Vsignal held in the hold circuit H (1) is transferred to amp1 and amplified. This amplified signal is transferred to the processing circuit PU1.

  In this embodiment, H (1) to H (8) operate simultaneously, Q (1) to Q (8) operate simultaneously, and PU1 to PU8 operate simultaneously. Processed simultaneously.

  For each signal line (L1 to L512), two hold circuits described above (for signal and noise) are provided in parallel, and further, a CDS circuit is provided to remove noise and transfer to the processing circuit PU1. May be.

  In the above example, the partial read region R is determined by the image data calculation unit based on the previous image, and the timing generation circuit generates a necessary control signal. This is shown in Japanese Patent Application No. 2003-189181. It may be determined based on information obtained from a profile detection function of an imaging apparatus (referred to as a profile imager), or may be determined based on an image stored in a hold circuit or a frame memory.

  Further, it is not necessary to limit the partial read region R based on the stored image, and a signal for selecting only a part of all the pixels is read from the outside instead of the image data calculation unit. May be.

  By doing this, the number of pixels to be read and the number of pixels can be changed depending on the signal input from the outside, and the number of pixels can be small. Can be realized.

It is a block diagram of the solid-state imaging device concerning an embodiment. It is a figure which shows the detailed structure of each pixel P (x, y) which comprises each pixel column. 2 is a timing chart of the solid-state imaging device illustrated in FIG. 1. It is a figure which shows the structure of a one-dimensional row direction luminance profile acquisition circuit. It is a time chart of a one-dimensional column direction luminance profile acquisition circuit. It is a figure which shows the structure of a one-dimensional row direction luminance profile acquisition circuit. It is a time chart of a one-dimensional row direction luminance profile acquisition circuit. It is a circuit block diagram of a controller. It is a time chart which shows the waveform of each part of control. It is a block diagram which shows a processing circuit. It is a figure which shows the optical input-digital video signal characteristic of the solid-state imaging device of this embodiment. 1 is a circuit diagram of a solid-state imaging device according to an embodiment. It is a detailed circuit diagram of the main image pick-up part of pixel P (x, y). It is a circuit diagram of a row selection circuit for generating each signal. It is a timing chart of each signal. FIG. 3 is a circuit diagram of a switch group for reading out charges accumulated in a hold circuit group. It is a circuit diagram of the column selection circuit for producing | generating each signal. It is a timing chart of each signal. It is a figure which shows the structure of the processing circuit which has an amplifier which can vary an amplification gain. It is a figure which shows the modification of a hold circuit group, a switch group, a CDS circuit, and a processing circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Image data calculating part, 11 ... Timing generation circuit, 12 ... Row selection circuit, 13 ... Column selection circuit, 14 ... One-dimensional column direction luminance profile acquisition circuit, 15 ... One-dimensional row direction luminance profile acquisition circuit, 16 ... Controller , PU1, PU2, PU3 ... processing circuit, ADC1, ADC2, ADC3 ... converter, H ... hold circuit, P (x, y) ... pixel, B1, B2, B3 ... imaging block, N1, N2, N3 ... pixel array , M1, M2, M3... Pixel rows.

Claims (4)

In a solid-state imaging device having an imaging region in which one pixel includes a main imaging unit, a column direction detection imaging unit, and a row direction detection imaging unit, and a plurality of the pixels are two-dimensionally arranged.
A processing circuit for AD-converting the output from the main imaging unit of each pixel to generate a digital video signal;
A one-dimensional column direction luminance profile acquisition circuit that adds the outputs of the pixels from the column direction detection imaging unit for each pixel row and generates a one-dimensional column direction luminance profile based on the output added for each pixel row; ,
A one-dimensional row direction luminance profile acquisition circuit that adds the outputs of the pixels from the row direction detection imaging unit for each pixel column and generates a one-dimensional row direction luminance profile based on the output added for each pixel column; ,
A controller that generates a gain conversion signal of the processing circuit from the one-dimensional column direction luminance profile and the one-dimensional row direction luminance profile;
With
The one-dimensional column direction luminance profile acquisition circuit has a one-dimensional column direction luminance profile shift register for selecting the pixel row,
The one-dimensional row direction luminance profile acquisition circuit has a one-dimensional row direction luminance profile shift register for selecting the pixel column,
The solid-state imaging device, wherein the processing circuit changes an AD conversion gain based on the gain conversion signal. The one-dimensional column direction luminance profile acquisition circuit includes:
An output current from the column direction detection imaging unit of the pixel is added for each pixel row, and an integration circuit for a one-dimensional column direction luminance profile that converts the output current added for each pixel row into a voltage;
A one-dimensional column direction luminance profile switch for controlling the one-dimensional column direction luminance profile shift register to connect the column direction detection imaging unit to the one-dimensional column direction luminance profile integration circuit for each pixel row. When,
Further comprising
The one-dimensional row direction luminance profile acquisition circuit includes:
An output current from the row direction detection imaging unit of the pixel is added for each pixel column, and an integration circuit for a one-dimensional row direction luminance profile that converts the output current added for each pixel column to a voltage;
A one-dimensional row direction luminance profile switch for controlling the one-dimensional row direction luminance profile shift register to connect the row direction detection imaging unit to the one-dimensional row direction luminance profile integration circuit for each pixel column. When,
Further having
The solid-state imaging device according to claim 1. The imaging region is composed of K imaging blocks in which N pixel columns are adjacently arranged,
An image data arithmetic unit for designating a partial readout area in accordance with an input digital video signal;
A row selection circuit for selecting a pixel row corresponding to the partial readout region;
A column selection circuit for selecting a pixel column corresponding to the partial readout region;
A timing generation circuit for generating a control signal for causing the row selection circuit and the column selection circuit to select based on an output of the image data calculation unit;
Further comprising
The nth processing circuit is all connectable to the main imaging unit of the nth pixel column in each imaging block via the switch,
The N processing circuits are respectively connected to the main imaging units of the N pixel columns via a switch that is turned on by the selection of the column selection circuit, and are selected by the row selection circuit and the column selection circuit. The digital video signal is generated from the output of each pixel column of the main imaging unit.
The solid-state imaging device according to claim 1 or 2. A plurality of hold circuits respectively connected to the main imaging unit of each of the pixel columns;
The switch synchronizes the charge accumulated in each hold circuit for each pixel column of the main imaging unit in synchronization with the control signal input from the timing generation circuit to the column selection circuit. The solid-state imaging device according to claim 3, wherein the solid-state imaging device is connected to the processing circuit corresponding to the main imaging unit in a row.

Images