JP2006295051A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device structured to use a lead of a lead frame as an internal wire of a package, having a simple process and capable of reducing cost, and to provide its manufacturing method. <P>SOLUTION: The lead 10 is provided along the outer periphery of a semiconductor chip 11. The semiconductor chip 11 and the lead 10 are connected via a wire bonding part 13. The semiconductor chip 11, the lead 10 and the wire bonding part 13 are sealed with resin layers (14, 15 and 17). A lead opening C1 is further provided on the resin layers to reach the lead 10. Extraction electrodes (21a and 22a) are embedded in the lead opening. <P>COPYRIGHT: (C)2007,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device in which a semiconductor chip is embedded and packaged and a manufacturing method thereof.

  In recent years, electrical products have become smaller and lighter so that they can be easily carried, such as mobile phones and PDAs. However, modules and semiconductor devices mounted in such sets have been required to be small and light. Yes. For such downsizing, so-called high-density mounting that effectively uses the substrate is necessary.

  High-density mounting means to pack as many parts as possible on the board. To this end, it is realized by downsizing the parts and mounting with a small interval between the parts. For example, the parts themselves are mounted on the board. When it is built in, the mounting density can be further improved, and research and development have been actively conducted in recent years.

  For example, in Patent Document 1, a semiconductor chip is mounted on an insulating substrate having a conductive pattern formed on the surface, side walls are formed on the outer periphery of the semiconductor chip, a cavity is provided, and a sealing resin is filled in the cavity. A semiconductor device having a sealed configuration is disclosed.

In the semiconductor device described in Patent Document 1, in order to form a core substrate used for a packaged semiconductor device, for example, a copper foil pattern forming step and an inner via forming step are required. There was a tendency to be expensive due to the complexity.
In addition, the semiconductor device described in Patent Document 1 has a disadvantage that heat dissipation is poor because a semiconductor chip with high heat generation is basically confined in the package.
JP 2002-26187 A

  The problem to be solved by the present invention is that manufacturing a core substrate for use in a package tends to be complicated and expensive.

  The semiconductor device of the present invention includes a semiconductor chip, a lead disposed on an outer peripheral portion of the semiconductor chip, a wire bonding portion that connects the semiconductor chip and the lead, the semiconductor chip, the lead, and the wire bonding portion. And a lead electrode embedded in a lead opening provided in the resin layer so as to reach the lead.

  In the semiconductor device of the present invention described above, the leads are arranged on the outer peripheral portion of the semiconductor chip, the semiconductor chip and the lead are connected by the wire bonding portion, and the semiconductor chip, the lead and the wire bonding portion are sealed by the resin layer. ing. Further, a lead opening is provided in the resin layer so as to reach the lead, and an extraction electrode is embedded in the lead opening.

  According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the step of disposing a lead at a predetermined position on the outer periphery of a semiconductor chip, the step of forming a wire bonding portion that connects the semiconductor chip and the lead, and the semiconductor A step of forming a resin layer for sealing the chip, the lead and the wire bonding portion; a step of forming a lead opening in the resin layer so as to reach the lead; and a lead electrode embedded in the lead opening. Forming.

  In the method of manufacturing a semiconductor device according to the present invention, the lead is disposed at a predetermined position on the outer peripheral portion of the semiconductor chip, and the wire bonding portion that connects the semiconductor chip and the lead is formed. Next, a resin layer for sealing the semiconductor chip, the lead, and the wire bonding portion is formed. Further, a lead opening is formed in the resin layer so as to reach the lead, and a lead electrode is formed by being embedded in the lead opening.

  According to the semiconductor device of the present invention, the lead frame lead is used as the internal wiring of the package and is embedded in the resin, so that the process is simple and the cost can be reduced.

  According to the semiconductor device manufacturing method of the present invention, the lead frame lead is used as the internal wiring of the package, and the manufacturing process is simple and the cost can be reduced.

  A semiconductor device and a manufacturing method thereof according to embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic cross-sectional view showing the configuration of the semiconductor device according to the present embodiment.
For example, the semiconductor chip 11 is fixed via an adhesive layer 12 such as a die attach film on a chip support portion 10c formed integrally with the lead 10 at a portion not shown, and the lead 10 is connected to the semiconductor chip 11. Are arranged so as to extend from the inner side close to the semiconductor chip 11 toward the outer side. The inner portion 10e of the lead 10 near the semiconductor chip 11 and the surface of the chip support portion 10c are configured to be lower than the surface of the outer portion.

  The lead 10 having the above-described configuration and the chip support portion 10c formed integrally with the lead 10 have, for example, a first pattern which is patterned with an outer surface far from the semiconductor chip 11 of the lead 10 as a surface, as will be described later. A structure in which a metal plate and a second metal plate that is patterned and has a surface (support surface) of the chip support portion 10c as a surface and an inner surface close to the semiconductor chip 11 of the lead 10 are bonded to each other. is there.

  The inner part 10e of the lead 10 and a pad (not shown) of the semiconductor chip 11 are connected by the wire bonding part 13, and the inner part 10e of the lead 10 and the surface of the chip support part 10c are lowered from the outside. For this reason, the top of the wire bonding portion 13 is lower than the outer surface far from the semiconductor chip 11 that is the uppermost surface of the lead 10.

  The semiconductor chip 11 and the wire bonding portion 13 having the above-described configuration are sealed with the sealing resin layer 14, and further, the lead 10 and the chip support portion 10c are integrally formed to constitute the core substrate.

A covering resin layer 15 is bonded to the upper layer of the sealing resin layer 14 of the core substrate having the above-described structure, and a conductive foil 16 such as copper is provided on the upper layer, and the covering resin layer 15 and the conductive foil 16 are provided on the upper layer. On the other hand, a lead opening C1 reaching the outer surface far from the semiconductor chip 11 of the lead 10 is formed, and a conductive layer 19 such as copper is embedded, and the patterned conductive foil 16 and the conductive layer 19 are embedded. An extraction electrode 21a embedded in the lead opening C1 is configured.
Further, the conductive foil 16 and the conductive layer 19 are also patterned on the coating resin layer 15 in the region where the lead opening C1 is not provided, and the wiring and / or electrode 21b formed by connecting to the extraction electrode 21a. Is configured.

Also on the back surface side of the core substrate having the above-described configuration, the coating resin layer 17 is bonded to the upper layer of the sealing resin layer 14, and the conductive foil 18 such as copper is provided on the upper layer, and the coating resin layer 17. A lead opening reaching the surface of the lead 10 is formed with respect to the conductive foil 18, and a conductive layer 20 such as copper is embedded, and the conductive foil 18 and the conductive layer 20 that are patterned in the lead opening A take-out electrode 22a embedded in is formed.
Further, a chip support portion opening C2 reaching the surface of the chip support portion 10c is formed with respect to the coating resin layer 15, and a conductive layer 20 such as copper is embedded, and the conductive foil 18 patterned and conductive is embedded. A heat dissipating layer 22b embedded in the chip support opening C2 is formed from the layer 20.

  A solder resist (23, 24) is formed on the covering resin layer (15, 17) in the gap between the extraction electrode (21a, 22a) and the wiring and / or the electrode 21b, and the extraction electrode (21a, 22a) and Desired electronic components (25, 26) and other semiconductor chips (not shown) are mounted at desired locations on the wiring and / or electrode 21b.

  The semiconductor device having the above configuration is a semiconductor device in which the lead frame lead is used as the internal wiring of the package and is embedded in the resin, and the process is simple and the cost can be reduced.

In addition, since semiconductor chips and electronic components can be arranged on both the upper and lower surfaces of a core substrate incorporating a semiconductor chip, high-density mounting is possible and the substrate area can be reduced, so that cost reduction can be realized.
In addition, the heat dissipation layer thermally connected to the built-in semiconductor chip is thicker than the copper layer (about 35 μm) formed on the normal core substrate, has a sufficient heat capacity, and dissipates heat from the built-in semiconductor chip. It is excellent in reliability, has high reliability, and can incorporate a semiconductor chip with high heat generation.

A method for manufacturing the semiconductor device of the present embodiment will be described.
FIG. 2A is a plan view of a lead frame used in the present embodiment, and FIG. 2B is a cross-sectional view taken along the line XX ′ in FIG.
For example, the first metal plate 10a and the second metal plate 10b are patterned, and are partially overlapped and bonded. A frame portion F is integrally formed on the first metal plate 10a, and a chip support portion 10c is integrally formed on the second metal plate 10b.

  By adopting a lead frame configuration in which two sheets are bonded together as described above, the surface of the first metal plate 10a provides an outer surface far from the semiconductor chip 11 of the lead 10, and the surface of the second metal plate 10b. Provides the surface (support surface) of the chip support portion 10c and the inner surface of the lead 10 near the semiconductor chip 11, whereby the inner portion 10e of the lead 10 near the semiconductor chip 11 and the surface of the chip support portion 10c It can be set as the structure lowered | hanged from the surface of the outer part.

3A to 3C are cross-sectional views showing a process of manufacturing a lead frame in the process of manufacturing a semiconductor device according to this embodiment.
First, as shown in FIG. 3A, a metal plate having a thickness of 0.2 mm, for example, is processed into a predetermined pattern as described above by punching or etching to produce a first metal plate 10a.
On the other hand, as shown in FIG. 3B, for example, a metal plate having a thickness of 0.15 mm is processed into a predetermined pattern having a chip support portion 10c by punching or etching, and the second metal plate 10b. Create
Next, as shown in FIG. 3C, the first metal plate 10a and the second metal plate 10b are bonded with a conductive adhesive layer 10d such as a silver paste. Thus, a lead frame in which the lead 10 and the chip support portion 10c as described above are integrally formed is formed.
The lead frame has a thickness of about 0.35 mm by combining the first metal plate 10a and the second metal plate 10b, and the inner portion 10e of the lead 10 near the semiconductor chip 11 and the surface of the chip support portion 10c are outside. The structure is lowered about 0.2 mm from the surface of the part.

In the lead frame forming method as described above, the first and second metal plates can be processed by a simple processing method such as punching, respectively, and it is not necessary to perform complicated etching. It can be manufactured at a high cost with a high yield.
Alternatively, a method of patterning and bonding three or more metal plates may be used.
Although the yield is low, the same configuration as the above-described configuration in which the two metal plates are bonded together is realized by patterning a single metal plate to have irregularities by a method such as half etching. It is also possible.

  Next, as shown in FIG. 4 (a), for example, in order to prevent resin leakage during molding, a lead frame in which the lead 10 formed as described above and the chip support portion 10c are integrally formed, For example, it is bonded to a mold tape S such as Hitachi Chemical Co., Ltd. RT-321.

  Next, as shown in FIG. 4B, the semiconductor chip 11 is mounted on the chip support portion 10c using an adhesive layer 12 such as a die attach film or a die bond agent.

  Next, as shown in FIG. 4C, for example, the pads of the semiconductor chip 11 and the inner portions 10e of the leads 10 near the semiconductor chip 11 are electrically connected by a wire bonding portion 13 formed using a gold wire. Connecting.

  Next, as shown in FIG. 5A, for example, a sealing resin layer 14 is formed by transfer molding, the semiconductor chip 11 and the wire bonding portion 13 are sealed, and the leads 10 and the chip support portion 10c are integrated. To form.

Next, as shown in FIG. 5B, for example, the mold tape S is peeled off, the semiconductor chip 11 and the wire bonding portion 13 are sealed, and the lead 10 and the chip support portion 10c are integrally molded. The core substrate is configured.
On the surface of the flat core substrate, the upper and lower surfaces of the lead 10 and the back surface of the support surface of the chip support portion 10c are exposed.

Next, as shown in FIG. 5C, for example, a conductive foil 16 such as a copper foil in which a resin sheet to be the coating resin layer 15 is integrated on the upper surface of the core substrate is vacuum-laminated, for example, 2 kg. Bonding is performed by applying a pressure of 80 ° C. and a temperature of 80 ° C., and the lower surface of the core substrate is similarly bonded with a conductive foil 18 such as a copper foil integrated with a resin sheet to be the coating resin layer 17.
As the copper foil in which the resin sheet is integrated, for example, a copper foil with resin (MGR200) manufactured by Mitsubishi Metal Co., Ltd. in which a 12 μm copper foil is formed on a sheet made of a 40 μm epoxy resin can be used. As a result, the configuration shown in FIG.

Next, as shown in FIG. 6B, for example, a lead opening that reaches the lead through the coating resin layers (15, 17) and the conductive foil (16, 18) by burst processing using an ultraviolet laser. C1 is formed. Burst processing is performed, for example, with a frequency of 25 kHz and a number of shots of 143 shots.
Further, the chip support portion opening C2 reaching the back surface of the support surface of the chip support portion 10c is formed in the same manner.
It is also possible to form the lead opening C1 and the chip support opening C2 by a processing method other than the above.

  Next, as shown in FIG. 6C, the upper surface and the lower surface of the core substrate are each plated with a conductor such as copper, such as electroplating or chemical plating, so that the lead opening C1 and the chip support opening C2 Are embedded to form conductive layers (19, 20). The plating thickness is, for example, about 25 μm.

Next, as shown in FIG. 7A, for example, a dry film is attached on the conductive layer 19, pattern exposure and development are performed to form a resist film, and this is used as a mask to perform an etching process. The layer 19 and the conductive foil 16 are integrally processed to form the extraction electrode 21a embedded in the lead opening C1. Further, by patterning the conductive layer 19 and the conductive foil 16 on the coating resin layer 15, it is possible to form the wiring and / or the electrode 21b formed by being connected to the extraction electrode 21a.
On the other hand, a similar process is performed on the conductive layer 20 to form the extraction electrode 22a embedded in the lead opening C1, and further embedded in the chip support opening C2 reaching the back surface of the chip support 10c. A heat dissipation layer 22b composed of the processed conductive foil 18 and conductive layer 20 is formed.

  Next, as shown in FIG. 7B, a solder resist (23, 24) having a film thickness of 30 to 50 μm is formed by, for example, printing, exposure, development, and post-cure processing of a liquid solder resist.

  Furthermore, by mounting a desired electronic component (25, 26) or other semiconductor chip at a desired location of the extraction electrode (21a, 22a) and wiring and / or electrode 21b formed as described above, A semiconductor device in which the semiconductor chip shown in FIG. 1 is incorporated and packaged can be manufactured.

  According to the semiconductor device manufacturing method of the present embodiment, the lead frame lead is used as the internal wiring of the package, so that the process can be simplified and the cost can be reduced.

  In addition, in the conventional method for manufacturing a component-embedded substrate, the core substrate is patterned by an etching method, a via hole is formed using a drill or a laser, and a conductive paste is filled in for conduction. However, in this embodiment, the core part can be manufactured simply by bonding with a conductive paste using a lead frame, so there is no need for via formation, etc., and the process is short, so the lead time is shortened and manufactured inexpensively. Can do.

  In addition, when a complicated shape is required as the lead frame as a core, a plurality of simple structures of the lead frame are manufactured by a method such as punching as in this embodiment, and a plurality of sheets are bonded to each other and complicated. By realizing a simple shape, productivity can be improved, lead time can be shortened, and manufacturing can be performed at low cost.

  In addition, because the die is processed, a thick lead frame can be used, the heat capacity is kept high, and the heat dissipation effect is high, so the life of the device can be extended, and even a highly exothermic chip can be placed in the substrate. It can be built in stably.

The present invention is not limited to the description of the above embodiment.
For example, in this embodiment, two lead frames are bonded together, but the effect can be further enhanced by stacking and bonding three or more lead frames.
In addition, one layer of resin-coated copper foil is bonded to the top and bottom of the core substrate including the lead frame to form a conductive pattern. Density packaging can be achieved.
In addition, various modifications can be made without departing from the scope of the present invention.

FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention. 2A is a plan view of a lead frame used in the embodiment of the present invention, and FIG. 2B is a cross-sectional view taken along line X-X ′ in FIG. 3A to 3C are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the embodiment of the present invention. 4A to 4C are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the embodiment of the present invention. 5A to 5C are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the embodiment of the present invention. 6A to 6C are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the embodiment of the present invention. 7A and 7B are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Lead, 10a ... 1st metal plate, 10b ... 1st metal plate, 10c ... Chip support part, 10d ... Conductive adhesive layer, 10e ... Inner part near lead semiconductor chip, 11 ... Semiconductor chip, 12 ... Adhesive layer, 13 ... wire bonding part, 14 ... sealing resin layer, 15 ... coating resin layer, 16 ... conductive foil, 17 ... coating resin layer, 18 ... conductive foil, 19 ... conductive layer, 20 ... conductive layer, 21a ... Extraction electrode, 21b ... wiring and / or electrode, 22a ... extraction electrode, 22b ... heat dissipation layer, 23 ... solder resist, 24 ... solder resist, 25 ... electronic component, 26 ... electronic component, C1 ... lead opening, C2 ... Chip support opening, F ... frame part, S ... mold tape

Claims (12)

A semiconductor chip;
Leads arranged on the outer periphery of the semiconductor chip;
A wire bonding portion for connecting the semiconductor chip and the lead;
A resin layer for sealing the semiconductor chip, the lead, and the wire bonding portion;
A semiconductor device comprising: a take-out electrode embedded in a lead opening provided in the resin layer so as to reach the lead. A chip support portion sealed with the resin layer and in contact with the semiconductor chip on a surface opposite to the connection surface of the wire bonding portion of the semiconductor chip;
The semiconductor device according to claim 1, wherein the chip support portion is formed integrally with a part of the lead. The inner surface of the lead near the semiconductor chip is lower than the outer surface of the lead far from the semiconductor chip, the support surface of the chip support portion is lower than the outer surface of the lead far from the semiconductor chip, and the wire The semiconductor device according to claim 2, wherein a top portion of the bonding portion is formed to be lower than an outer surface far from the semiconductor chip of the lead. The lead and the chip support portion have a first metal plate patterned with an outer surface far from the semiconductor chip of the lead as a surface, and the support surface and the semiconductor chip of the lead as a surface. The semiconductor device according to claim 3, wherein the semiconductor device is formed by bonding a patterned second metal plate having an inner surface. The semiconductor device according to claim 1, wherein a wiring and / or an electrode is formed on the resin layer so as to be connected to the extraction electrode. A chip support part opening reaching the surface of the chip support part is formed with respect to the resin layer,
The semiconductor device according to claim 2, wherein a conductive layer is embedded in the chip support portion opening to form a heat dissipation layer. Arranging the leads at predetermined positions on the outer periphery of the semiconductor chip;
Forming a wire bonding portion connecting the semiconductor chip and the lead;
Forming a resin layer for sealing the semiconductor chip, the lead and the wire bonding part;
Forming a lead opening in the resin layer to reach the lead;
And a step of forming an extraction electrode by embedding in the lead opening. As the lead, using a lead in which a chip support portion in contact with the semiconductor chip on the surface opposite to the connection surface of the wire bonding portion of the semiconductor chip is formed integrally with a part of the lead,
In the step of arranging the lead at a predetermined position on the outer peripheral portion of the semiconductor chip, the semiconductor chip is mounted on the support surface of the chip support portion formed integrally with the lead,
The method for manufacturing a semiconductor device according to claim 7, wherein the chip support portion is also sealed in the step of forming the resin layer. As the lead and the chip support portion, the inner surface of the lead near the semiconductor chip is lower than the outer surface of the lead far from the semiconductor chip, and the support surface of the chip support portion is from the semiconductor chip of the lead. 9. The semiconductor device according to claim 8, wherein a lead and a chip support portion are used which are formed so as to be lower than a far outer surface and a top portion of the wire bonding portion is lower than an outer surface far from the semiconductor chip of the lead. Production method. Prior to the step of disposing the lead at a predetermined position on the outer periphery of the semiconductor chip, the first metal plate patterned with the outer surface far from the semiconductor chip of the lead as a surface, and the surface as the surface 10. The method further comprises a step of bonding the support surface and a second metal plate patterned with an inner surface close to the semiconductor chip of the lead to form the lead and the chip support portion. The manufacturing method of the semiconductor device of description. The method for manufacturing a semiconductor device according to claim 7, further comprising a step of forming a wiring and / or an electrode connected to the extraction electrode on the resin layer. In the step of forming the lead opening, a chip support opening that reaches the surface of the chip support with respect to the resin layer is further formed,
The method of manufacturing a semiconductor device according to claim 8, wherein in the step of forming the extraction electrode, a heat dissipation layer is formed by embedding a conductive layer in the opening of the chip support portion.

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