JP2006295027A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress noise and a leakage signal transmitted through a power line or a ground line according to change in circuit operating frequency, ambient surcumstances, or the like, and thereby to stabilize a semiconductor device to prevent malfunction and degradation in characteristics. <P>SOLUTION: Multiple capacitors C101 to C104 and switch elements S101 to S104 are provided between multiple circuit blocks 101 and 102 formed over a semiconductor substrate for the suppression of noise and leakage signals. The switch elements S101 to S104 are operated to obtain information related to an optimum state of connection in which noise and leakage signals are minimized, and this information is stored in a nonvolatile storage device 111. The switches are kept in the optimum state of connection according to the information in the nonvolatile storage device 111. Noise and leakage signals are thereby suppressed to stabilize the semiconductor device and prevent malfunction and degradation in characteristics. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to an interference countermeasure technique for reducing noise and interference on a power supply line or a ground line formed on a semiconductor substrate.

  In recent years, semiconductor devices have become more multifunctional and highly integrated, and semiconductor devices having various circuit blocks in a limited chip size have been developed.

  Conventionally, in a semiconductor device in which multiple circuit blocks exist on the same substrate, a bypass capacitor has been provided between the power supply line and the ground line in order to prevent malfunctions and characteristic degradation caused by mutual noise or leakage signals generated by circuit operation. ing.

  FIG. 6 is a circuit diagram for explaining countermeasures against interference in a conventional semiconductor device.

  In FIG. 6, R601 to R610 are parasitic elements, 601 is a circuit block (A), 602 is a circuit block (B), 603 is a semiconductor device, 604 is a voltage source, 605 to 608 are terminals, 609 is a power supply line, and 610 is The ground lines C601 and C602 are capacitors (bypass capacitors).

  The circuit block (A) 601 and the circuit block (B) 602 exist on the semiconductor device 603 on the same substrate, and the power supply line 609 and the ground line 610 are connected to the voltage source 604 via terminals 605 to 608 by wiring. Has been. Parasitic elements R601 to R610 are generated depending on the length of the wiring or the routing method.

  In this case, when the circuit block (A) 601 and the circuit block (B) 602 are simultaneously operated, interference occurs in the power supply line 609 or the ground line 610, and the circuit block (A) 601 is connected to the circuit block (B) 602. It is easy for malfunction or characteristic deterioration to occur with respect to noise or leakage signals generated by the above operation.

  Therefore, capacitors C601 and C602 are provided between the power supply line 609 and the ground line 610 to suppress noise and leakage signals transmitted through the power supply line 609 or the ground line 610, and a circuit block (B) 602 is generated. Noise is absorbed, the potentials of the power supply line 609 and the ground line 610 are stabilized, and malfunction or characteristic deterioration due to interference is prevented.

Further, Patent Document 1 discloses a method of providing a semiconductor device that can effectively suppress power source ground noise in a high frequency region and can operate stably.
JP 2000-150796 A

  However, in the conventional interference countermeasure, the installation location and the capacitance value of the bypass capacitor are fixed, and the capacitance value cannot be changed in response to changes in the circuit operating frequency or the surrounding environment. There was a problem that it could not be effectively suppressed.

  The present invention solves the above-mentioned problems of the prior art and realizes an optimum capacitance value with respect to changes in the circuit operating frequency or the surrounding environment by changing the capacitance value of the bypass capacitor. It is an object of the present invention to provide a semiconductor device that can suppress noise and leakage signals transmitted through the signal line and stabilize and prevent malfunction and characteristic deterioration.

  In order to achieve the above object, the invention according to claim 1 is a circuit block formed on a semiconductor substrate, at least one bypass capacitor connected to a power supply line and a ground line, the bypass capacitor and a power supply. The at least one switch for connecting a ground line, and a non-volatile memory device connected to the switch, wherein the noise or leakage signal obtained by changing the connection state of the bypass capacitor by the switch is minimized. The connection state information is stored in the nonvolatile storage device. With this configuration, the connection state of the bypass capacitor is switched based on the information stored in the nonvolatile storage device, and the capacitance value of the bypass capacitor is changed. The optimum capacity is selected according to the circuit operating frequency or the surrounding environment. By setting the value, it is possible to stabilize and suppress noise and leakage signals transmitted via the power line or ground line, it is possible to prevent a malfunction or characteristic deterioration.

  According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the semiconductor device includes a controller that rewrites information stored in the nonvolatile memory device and changes a connection state of the switch. The bypass capacitor can be set to an optimum capacitance value in response to changes in the circuit operating frequency and the surrounding environment.

  According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, a bypass capacitor is connected between power supply lines.

  According to a fourth aspect of the present invention, in the semiconductor device according to the first or second aspect, a bypass capacitor is connected between the ground lines.

  According to a fifth aspect of the present invention, in the semiconductor device according to the first or second aspect, a bypass capacitor is connected between the power supply line and the semiconductor substrate.

  According to the present invention, by varying the capacitance value of a bypass capacitor provided as an interference countermeasure for a semiconductor device having a plurality of circuit blocks, the power supply line or the ground line can be changed according to changes in the circuit operating frequency or the surrounding environment. Noise and leakage signals transmitted through the terminal can be suppressed, which is effective as a countermeasure against interference that stabilizes and prevents malfunction and characteristic deterioration.

  Hereinafter, a semiconductor device interference countermeasure method according to an embodiment of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a circuit diagram for explaining countermeasures against interference in a semiconductor device according to the first embodiment of the present invention.

  In FIG. 1, a circuit block (A) 101 and a circuit block (B) 102 exist on a semiconductor device 103 on the same substrate, and a power source line 109 and a ground line 110 are connected to a voltage source via terminals 105 to 108 by wiring. 104 is connected. Parasitic elements R101 to R112 are generated depending on the length of the wiring and the routing method. Further, a nonvolatile memory device 111 is provided, and a plurality of capacitors (bypass capacitors) C101 to C104 and a plurality of switch elements S101 to S104 connected to the nonvolatile memory device 111 are connected between the power supply line 109 and the ground line 110. ing.

  In the circuit configuration, when the circuit block (A) 101 and the circuit block (B) 102 are simultaneously operated, interference occurs in the power supply line 109 and the ground line 110, and the circuit block (A) 101 is connected to the circuit block (B). Malfunctions and characteristic degradation are likely to occur due to noise and leakage signals generated by the operation 102.

  For this reason, a bypass capacitor is provided between the power supply line 109 and the ground line 110 in order to suppress noise and leakage signals transmitted through the power supply line 109 or the ground line 110, but the installation location or capacitance value is fixed. If this is the case, noise and leakage signals may not be sufficiently suppressed depending on the circuit operating frequency or the surrounding environment.

  Therefore, in the present embodiment, the plurality of switch elements S101 to S104 connected to the nonvolatile memory device 111 are operated, and the connection state of the plurality of capacitors C101 to C104 provided between the power supply line 109 and the ground line 110 is changed. Thus, information on the optimum connection state that minimizes noise and leakage signals is obtained, and the information is stored in the nonvolatile storage device 111.

  In this way, the connection state of the plurality of capacitors C101 to C104 as bypass capacitors is appropriately switched based on the information stored in the nonvolatile storage device 111, and the capacitance value of the bypass capacitor is changed to thereby change the circuit operating frequency. Alternatively, it can be set to an optimal capacitance value corresponding to changes in the surrounding environment, etc., and noise and leakage signals transmitted via the power supply line 109 or the ground line 110 can be suppressed and stabilized. It is possible to satisfactorily prevent characteristic deterioration.

(Second Embodiment)
FIG. 2 is a circuit diagram for explaining countermeasures against interference in a semiconductor device according to the second embodiment of the present invention.

  The second embodiment is different from the first embodiment in that the controller 212 for controlling the nonvolatile memory device 211 is provided on the semiconductor device of FIG.

  In the second embodiment, as in the first embodiment, a plurality of switch elements S201 connected to the nonvolatile memory device 211 are used to suppress noise and leakage signals transmitted through the power supply line 209 or the ground line 210. As described above, the optimum connection state in which noise and leakage signals are minimized by operating S204 and changing the connection state of the plurality of capacitors C201 to C204 provided between the power supply line 209 and the ground line 210. Is stored in the nonvolatile storage device 211.

  As the number of circuit blocks increases and the circuit operation becomes complicated, noise and leakage signals also increase in complexity. In order to suppress these, a controller 212 for controlling the nonvolatile memory device 211 is provided, and the contents of the nonvolatile memory device 211 are rewritten by the controller 212 in accordance with the usage state of the semiconductor device 203, so that noise and leakage signals are minimized. Keeps the switch connected. By repeating this operation, it is possible to suppress and stabilize noise and leakage signals under various conditions transmitted through the power supply line 209 or the ground line 210, and to prevent malfunction and characteristic deterioration. Become.

(Third embodiment)
FIG. 3 is a circuit diagram for explaining countermeasures against interference in a semiconductor device according to the third embodiment of the present invention.

  In the second embodiment, the capacitors C201 to C204 and the switch elements S201 to S204 are provided between the power supply line 209 and the ground line 210. However, as in the third embodiment shown in FIG. You may provide between the lines 309.

  A plurality of switch elements S301 to S303 connected to a plurality of capacitors C301 and C302 and a nonvolatile memory device 311 are connected between a power supply line 309 connecting the circuit block (A) 301 and the circuit block (B) 302. Yes.

  In the third embodiment, as described above, the contents of the nonvolatile memory device 311 are rewritten by the controller 312 in accordance with the usage status of the semiconductor device 303, the switch elements S301 to S303 are operated, and the power supply line 309 is provided. By changing the connection state of the capacitors C301 and C302, the optimum switch connection state that minimizes noise and leakage signals is maintained. By repeating this operation, it is possible to suppress and stabilize noise and leakage signals under various conditions transmitted through the power supply line 309, and to prevent malfunction and characteristic deterioration.

  Further, by opening the switch element S301, the power supply line 309 that is common in the semiconductor device 303 can be opened.

(Fourth embodiment)
FIG. 4 is a circuit diagram for explaining countermeasures against interference in a semiconductor device according to the fourth embodiment of the present invention.

  In the second embodiment, the capacitors C201 to C204 and the switch elements S201 to S204 are provided between the power supply line 209 and the ground line 210. However, as in the fourth embodiment shown in FIG. It may be provided between the ground lines 410.

  In the fourth embodiment, a plurality of capacitors C401 and C402 and a plurality of switches connected to the nonvolatile memory device 411 are provided between the ground lines 410 connecting the circuit block (A) 401 and the circuit block (B) 402. Elements S401 to S403 are connected.

  As described above, the contents of the nonvolatile memory device 411 are rewritten by the controller 412 according to the usage state of the semiconductor device 403, the switch elements S 401 to S 403 are operated, and the capacitors C 401 and C 402 provided between the ground lines 410. By changing the connection state, the optimum switch connection state that minimizes noise and leakage signals is maintained. By repeating this operation, it is possible to suppress and stabilize noise and leakage signals under various conditions transmitted through the ground line 410, and to prevent malfunction and characteristic deterioration.

  Further, by opening the switch element S401, the ground line 410 that is common in the semiconductor device 403 can be opened.

(Fifth embodiment)
FIG. 5 is a circuit diagram showing an interference countermeasure method for a semiconductor device according to the fifth embodiment of the present invention.

  In the second embodiment, the capacitors C201 to C204 and the switch elements S201 to S204 are provided between the power supply line 209 and the ground line 210. However, as in the fifth embodiment shown in FIG. The power supply line 509 and the semiconductor substrate 513 may be provided.

  In the fifth embodiment, a plurality of capacitors C501 to C504, a nonvolatile memory device 511, and a power supply line 509 connecting the circuit block (A) 501 and the circuit block (B) 502 and the semiconductor substrate 513 are provided. A plurality of connected switch elements S501 to S504 are connected. As described above, the contents of the nonvolatile memory device 511 are rewritten by the controller 512 in accordance with the usage state of the semiconductor device 503 and the switch elements S501 to S504 are operated to be provided between the power supply line 509 and the semiconductor substrate 513. By changing the connection state of the capacitors C501 to C504, the optimum switch connection state that minimizes noise and leakage signals is maintained. By repeating this operation, it is possible to suppress and stabilize the noise and leakage signal under various conditions transmitted through the ground line 510, and to prevent malfunction and characteristic deterioration.

  As described above, the embodiments of the present invention have been described. However, it is also possible to use the embodiments in combination as appropriate, and it is possible to suppress and stabilize noise and leakage signals, and to prevent malfunctions and characteristic deterioration. Become.

  As described above, according to the present embodiment, the connection state of a plurality of bypass capacitors provided as a countermeasure for interference of a semiconductor device having a plurality of circuit blocks is stored in a nonvolatile memory represented by FeRAM (ferroelectric random access memory). By switching the switch based on the information stored in the device and changing the capacitance value of the bypass capacitor, the optimum capacitance value can be set for changes in the circuit operating frequency or the surrounding environment. Alternatively, noise and leakage signals transmitted through the ground line can be suppressed and stabilized, which is a good countermeasure against interference that prevents malfunction and characteristic deterioration.

  The present invention is effective as a countermeasure against interference of a semiconductor device, and is particularly useful when implemented to reduce noise and interference on a power supply line or a ground line formed on a semiconductor substrate.

FIG. 3 is a circuit diagram for explaining countermeasures against interference in the semiconductor device according to the first embodiment of the present invention; Circuit diagram for explaining interference countermeasures of a semiconductor device according to a second embodiment of the present invention Circuit diagram for explaining interference countermeasures of a semiconductor device according to a third embodiment of the present invention The circuit diagram for demonstrating the interference countermeasure of the semiconductor device which concerns on the 4th Embodiment of this invention Circuit diagram for explaining interference countermeasures of a semiconductor device according to a fifth embodiment of the present invention Circuit diagram for explaining countermeasures against interference in a conventional semiconductor device

Explanation of symbols

101, 201, 301, 401, 501, 601 Circuit block A
102, 202, 302, 402, 502, 602 Circuit block B
103, 203, 303, 403, 503, 603 Semiconductor devices 104, 204, 304, 404, 504, 604 Voltage sources 105-108, 205-208, 305-308, 405-408, 505-508, 605-608 terminals 109, 209, 309, 409, 509, 609 Power line 110, 210, 310, 410, 510, 610 Ground line 111, 211, 311, 411, 511 Nonvolatile memory device 212, 312, 412, 512 Controller 513 Semiconductor substrate R101-R112, R201-R212, R301-R310, R401-R410, R501-R513, R601-R610 Parasitic elements C101-C104, C201-C204, C301, C302, C401, C402, C501, C501 , C601, C602 capacitor S101~S104, S201~S204, S301~S303, S401~S403, S501~S504 switch element

Claims (5)

  A plurality of circuit blocks formed on a semiconductor substrate, at least one bypass capacitor connected to a power supply line and a ground line, at least one switch connecting the bypass capacitor and the power supply ground line, and connected to the switch A non-volatile storage device, and information on the connection state that minimizes noise or a leakage signal obtained by changing the connection state of the bypass capacitor by the switch is stored in the non-volatile storage device. A semiconductor device characterized by the above.   2. The semiconductor device according to claim 1, further comprising a controller that rewrites information stored in the nonvolatile storage device and changes a connection state of the switch.   The semiconductor device according to claim 1, wherein the bypass capacitor is connected between the power supply lines.   The semiconductor device according to claim 1, wherein the bypass capacitor is connected between the ground lines.   The semiconductor device according to claim 1, wherein the bypass capacitor is connected between the power supply line and the semiconductor substrate.

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