JP2006294890A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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JP2006294890A
JP2006294890A JP2005114207A JP2005114207A JP2006294890A JP 2006294890 A JP2006294890 A JP 2006294890A JP 2005114207 A JP2005114207 A JP 2005114207A JP 2005114207 A JP2005114207 A JP 2005114207A JP 2006294890 A JP2006294890 A JP 2006294890A
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thermal expansion
metal plate
low thermal
expansion portion
semiconductor device
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Tatsuhiro Suzuki
達広 鈴木
Masanori Yamagiwa
正憲 山際
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Nissan Motor Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/36—Material effects
    • H01L2924/365—Metallurgical effects
    • H01L2924/3651—Formation of intermetallics

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which is capable of reducing a stress induced on the surface of a metal plate joined to a semiconductor element. <P>SOLUTION: The semiconductor device is equipped with an insulating circuit board 6 provided with a meal plate 2 of aluminum mounted with a semiconductor element 1, a base plate 5, and an insulating board 4. A low-thermal expansion unit 8a formed of porous molybdenum material which has a lower thermal expansion coefficient than the metal plate 2 is embedded in the area of the metal plate 2, or its vicinity where the semiconductor element 1 is mounted, and the low-thermal expansion unit 8a is impregnated with the component metal of the metal plate 2. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、半導体素子を搭載する金属板を備えた半導体装置及びその製造方法に関する。   The present invention relates to a semiconductor device including a metal plate on which a semiconductor element is mounted and a method for manufacturing the semiconductor device.

本発明にかかわる従来技術としては、例えば下記特許文献１に記載されているような構造がある。
下記特許文献１に記載された半導体装置は、アルミニウムからなる金属板がセラミックスからなる絶縁板に直接接合した構造をしている。この半導体装置は、アルミニウム溶湯を絶縁板上に直接凝固させて接合させることで形成されている。なお、半導体素子は、アルミニウムの金属板に半田等で接合されている。この技術の特徴は、金属板として従来用いられていた銅を使わずにアルミニウムを使用し、かつ、金属板をろう材等の接合材を用いて絶縁板に貼り付けるのではなく、アルミ溶湯を使って直接絶縁板上に金属板を形成したことにある。 As a prior art according to the present invention, for example, there is a structure as described in Patent Document 1 below.
The semiconductor device described in the following Patent Document 1 has a structure in which a metal plate made of aluminum is directly bonded to an insulating plate made of ceramics. This semiconductor device is formed by directly solidifying and joining molten aluminum on an insulating plate. The semiconductor element is bonded to an aluminum metal plate with solder or the like. The feature of this technology is that it uses aluminum instead of copper, which has been used conventionally as a metal plate, and uses a molten aluminum instead of affixing the metal plate to the insulating plate using a joining material such as brazing material. The metal plate is formed directly on the insulating plate by using.

特開２００１−１４４２２４号公報JP 2001-144224 A

金属板にろう材を用いて半導体素子を接合して搭載する半導体装置においては、ろう付けの際に半導体素子と金属板を加熱する製造工程を経るので、半導体素子と金属板との間の熱膨張係数差により、半導体素子と金属板との接続部分に残留応力が発生する。また、半導体装置の使用時においては、半導体素子の発熱により、半導体素子と金属板との接合部で熱膨張係数差による応力が発生する。（以下、これらの応力を熱応力と呼ぶことにする。）このときの熱応力の大きさは、熱膨張係数差、接合距離、温度差、ヤング率等の影響を受けることが分かっている。それゆえ、上記特許文献１では、金属板を銅よりもヤング率の低いアルミニウムで形成することにより、半導体素子と金属板との接続部分の熱応力を緩和し、半導体素子、ろう材、または金属板へのクラックの発生を防止している。   In a semiconductor device in which a semiconductor element is bonded and mounted on a metal plate using a brazing material, a manufacturing process for heating the semiconductor element and the metal plate is performed during brazing. Residual stress is generated in the connection portion between the semiconductor element and the metal plate due to the difference in expansion coefficient. Further, when the semiconductor device is used, stress due to a difference in thermal expansion coefficient is generated at the joint between the semiconductor element and the metal plate due to heat generation of the semiconductor element. (Hereinafter, these stresses will be referred to as thermal stresses.) It has been found that the magnitude of the thermal stress at this time is affected by the difference in thermal expansion coefficient, bonding distance, temperature difference, Young's modulus, and the like. Therefore, in Patent Document 1, the metal plate is formed of aluminum having a Young's modulus lower than that of copper, so that the thermal stress at the connection portion between the semiconductor element and the metal plate is alleviated, and the semiconductor element, the brazing material, or the metal The occurrence of cracks in the plate is prevented.

しかし、将来的にＳｉＣ等、さらに高温で使用可能な半導体素子の実装構造では、より高温で使用され、使用時の温度差がさらに広がることから、さらなる熱応力の低減が望まれる。
そこで、本発明の目的は、半導体素子と金属板との接合面に生じる応力を低減できる半導体装置及びその製造方法を提供することを目的としている。 However, a semiconductor element mounting structure that can be used at a higher temperature such as SiC in the future is used at a higher temperature, and the temperature difference during use is further widened. Therefore, further reduction of thermal stress is desired.
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can reduce stress generated on a joint surface between a semiconductor element and a metal plate.

上記課題を解決するために、本発明は、半導体素子を搭載する金属板を有し、この金属板の前記半導体素子を搭載する部分またはその近傍に、前記金属板よりも熱膨張係数が低い多孔質状の低熱膨張部が埋設されている、という構成になっている。   In order to solve the above problems, the present invention has a metal plate on which a semiconductor element is mounted, and a porous plate having a lower thermal expansion coefficient than that of the metal plate at or near a portion of the metal plate on which the semiconductor element is mounted. It has a configuration in which a quality low thermal expansion portion is embedded.

本発明によれば、半導体素子と金属板との接合面に生じる応力を低減できる半導体装置及びその製造方法を提供することができる。   ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device which can reduce the stress which arises in the joint surface of a semiconductor element and a metal plate, and its manufacturing method can be provided.

以下、本発明の実施の形態について図面を用いて詳細に説明する。なお、以下で説明する図面で、同一機能を有するものは同一符号を付け、その繰り返しの説明は省略する。
《第１の実施の形態》
まず、本発明の第一の実施の形態について図１〜図３を用いて説明する。
〈半導体装置の構造〉
図１は本実施の形態の半導体装置の断面図である。図１において、１は半導体素子、２は半導体素子１を搭載する金属板（高熱伝導部）、７は半導体素子１の搭載面、８ａは低熱膨張部、３は半導体素子１と金属板２とを接合する接合材、４は絶縁板、５はベース板、６は金属板２、絶縁板４、ベース板５からなる絶縁回路基板、１０は半導体装置である。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings described below, components having the same function are denoted by the same reference numerals, and repeated description thereof is omitted.
<< First Embodiment >>
First, a first embodiment of the present invention will be described with reference to FIGS.
<Structure of semiconductor device>
FIG. 1 is a cross-sectional view of the semiconductor device of this embodiment. In FIG. 1, 1 is a semiconductor element, 2 is a metal plate (high thermal conduction part) on which the semiconductor element 1 is mounted, 7 is a mounting surface of the semiconductor element 1, 8a is a low thermal expansion part, 3 is a semiconductor element 1 and a metal plate 2, 4 is an insulating plate, 5 is a base plate, 6 is an insulating circuit board composed of a metal plate 2, an insulating plate 4 and a base plate 5, and 10 is a semiconductor device.

本実施の形態の半導体装置１０は、電力用モジュールの一部分である絶縁回路基板６を備えたものである。絶縁回路基板６は、半導体素子１に流れる電流の経路となる金属板２と、半導体素子１から発生する熱を、絶縁板４を介して放熱器（図示せず）に放熱するベース板５と、両者の間に介在する絶縁板４とからなる。このように、本発明における金属板２は、絶縁板４及びベース板５と共に用いてもよく、または絶縁板４のみと用いることも可能である。   The semiconductor device 10 according to the present embodiment includes an insulating circuit substrate 6 that is a part of a power module. The insulating circuit board 6 includes a metal plate 2 serving as a path of a current flowing through the semiconductor element 1, and a base plate 5 that radiates heat generated from the semiconductor element 1 to a radiator (not shown) via the insulating plate 4. , And an insulating plate 4 interposed between the two. Thus, the metal plate 2 in the present invention may be used together with the insulating plate 4 and the base plate 5, or may be used only with the insulating plate 4.

金属板２の上面には半導体素子１の搭載面７が存在し、図１に示すように、その搭載面７の上にろう材等の接合材３を介してＭＯＳＦＥＴまたはＩＧＢＴ等の半導体素子１が搭載される。金属板２は、アルミニウムの純金属またはそれらを主成分とする合金等の高熱伝導性、高電気伝導性を持つ金属から構成されている。その金属板２中に、これよりも熱膨張係数の低い多孔質状の例えばモリブデンやタングステン等の金属もしくはこれらのいずれかの金属の合金、または多孔質状のセラミックス、ガラス、カーボン等の無機物からなる多孔質体（低熱膨張材）からなる低熱膨張部８ａが埋設された構造になっている。また、この多孔質体からなる低熱膨張部８ａには、金属板２の構成金属であるアルミニウムが含浸されている。   A mounting surface 7 of the semiconductor element 1 exists on the upper surface of the metal plate 2. As shown in FIG. 1, the semiconductor element 1 such as MOSFET or IGBT is placed on the mounting surface 7 via a bonding material 3 such as a brazing material. Is installed. The metal plate 2 is made of a metal having high thermal conductivity and high electrical conductivity such as a pure metal of aluminum or an alloy containing them as a main component. In the metal plate 2, a porous metal having a lower thermal expansion coefficient than this, such as a metal such as molybdenum or tungsten, or an alloy of any of these metals, or an inorganic material such as porous ceramics, glass, or carbon. A low thermal expansion portion 8a made of a porous body (low thermal expansion material) is embedded. Further, the low thermal expansion portion 8 a made of the porous body is impregnated with aluminum which is a constituent metal of the metal plate 2.

図２（Ａ）、（Ｂ）は、図１の低熱膨張部８ａを構成する多孔質体１１ａ、１１ｂの構造を示す断面図である。図２（Ａ）に示すように多孔質体１１ａは発泡体からなっているか、または図２（Ｂ）に示すように多孔質体１１ｂが粒子の焼結体からなっている。なお、図２（Ａ）、（Ｂ）に示す空隙１２ａ、１２ｂは、垂直方向についても水平方向についても均等に分布している。これらの空隙１２ａ、１２ｂに金属板２の構成金属であるアルミニウムが含浸される。   2A and 2B are cross-sectional views showing the structures of the porous bodies 11a and 11b constituting the low thermal expansion portion 8a of FIG. As shown in FIG. 2 (A), the porous body 11a is made of a foam, or as shown in FIG. 2 (B), the porous body 11b is made of a sintered body of particles. Note that the gaps 12a and 12b shown in FIGS. 2A and 2B are evenly distributed both in the vertical direction and in the horizontal direction. These voids 12a and 12b are impregnated with aluminum which is a constituent metal of the metal plate 2.

本実施の形態では、一例として、線熱膨張係数が２３．５（ｐｐｍ／Ｋ）のアルミニウムからなる金属板２中に、線熱膨張係数が５．１（ｐｐｍ／Ｋ）であるモリブデンの多孔質体が埋設されている例を挙げることとする。
絶縁板４は、金属板２の下面に直接接続されている。絶縁板４は、アルミナ、窒化アルミニウム、窒化珪素等の熱伝導性が良く、耐熱性の高いセラミックスで作られている。
ベース板５は、絶縁板４の下面に直接接続されている。なお、金属板２中に埋設された低熱膨張部８ａを取り囲むアルミニウムで形成された金属板２の部分を、高熱伝導部と呼ぶことにする。 In the present embodiment, as an example, the porosity of molybdenum having a linear thermal expansion coefficient of 5.1 (ppm / K) in a metal plate 2 made of aluminum having a linear thermal expansion coefficient of 23.5 (ppm / K). An example in which a material is embedded will be given.
The insulating plate 4 is directly connected to the lower surface of the metal plate 2. The insulating plate 4 is made of a ceramic having high thermal conductivity and high heat resistance such as alumina, aluminum nitride, and silicon nitride.
The base plate 5 is directly connected to the lower surface of the insulating plate 4. A portion of the metal plate 2 formed of aluminum surrounding the low thermal expansion portion 8a embedded in the metal plate 2 is referred to as a high thermal conduction portion.

上記のように本実施の形態の半導体装置は、半導体素子１を搭載する金属板２を備えた半導体装置において、金属板２の半導体素子１を搭載する部分（搭載された半導体素子１の直下の部分をいう）またはその近傍に、金属板２よりも熱膨張係数が低い多孔質体１１ａ（１１ｂ）からなる低熱膨張部８ａが埋設されている。また、低熱膨張部８ａには金属板２の構成金属が含浸されている。   As described above, the semiconductor device of the present embodiment is a semiconductor device including the metal plate 2 on which the semiconductor element 1 is mounted. The portion of the metal plate 2 on which the semiconductor element 1 is mounted (immediately below the mounted semiconductor element 1). A low thermal expansion portion 8a made of a porous body 11a (11b) having a lower thermal expansion coefficient than that of the metal plate 2 is embedded in the vicinity thereof. The low thermal expansion portion 8a is impregnated with the constituent metal of the metal plate 2.

これまでに述べた構造の利点は、金属板２が半導体素子１の搭載面２ａの直下に低熱膨張部８ａを有しているため、金属板２の半導体素子１の搭載面７の直下の熱膨張係数が半導体素子１（Ｓｉでは２．６（ｐｐｍ／Ｋ））に近くなることである。従って、従来の金属板２がアルミニウム単体でできている構造よりも、本発明の実施の形態においては、接合材３を含む半導体素子１と金属板２との接続部分における熱応力を減らすことができる。   The advantage of the structure described so far is that the metal plate 2 has the low thermal expansion portion 8a immediately below the mounting surface 2a of the semiconductor element 1, so that the heat immediately below the mounting surface 7 of the semiconductor element 1 of the metal plate 2 is. The expansion coefficient is close to that of the semiconductor element 1 (2.6 (ppm / K) for Si). Therefore, in the embodiment of the present invention, the thermal stress at the connecting portion between the semiconductor element 1 including the bonding material 3 and the metal plate 2 can be reduced in comparison with the structure in which the conventional metal plate 2 is made of aluminum alone. it can.

また、低熱膨張部８ａが多孔質体に金属板の構成金属が含浸した構造であるため、金属板２の半導体素子１の搭載面７にもアルミニウムが存在し、半導体素子１の搭載面７付近の金属板２は変形しやすくなっている。従って、半導体素子１と金属板２との間の熱膨張係数差により半導体素子１と金属板２との接続部分で歪が生じたとしても、半導体素子１の搭載面７付近の金属板２が変形することで熱応力を緩和することができる。   In addition, since the low thermal expansion portion 8a has a structure in which the porous plate is impregnated with the constituent metal of the metal plate, aluminum is also present on the mounting surface 7 of the semiconductor element 1 of the metal plate 2, and the vicinity of the mounting surface 7 of the semiconductor element 1 The metal plate 2 is easily deformed. Therefore, even if a distortion occurs at the connection portion between the semiconductor element 1 and the metal plate 2 due to the difference in thermal expansion coefficient between the semiconductor element 1 and the metal plate 2, the metal plate 2 near the mounting surface 7 of the semiconductor element 1 is By deforming, thermal stress can be relaxed.

このように本実施の形態では、金属板２の熱膨張係数を半導体素子１の熱膨張係数に近づけることによる熱応力低減と、半導体素子１の搭載面７付近の金属板２を変形しやすくすることによる熱応力低減の両方の効果を同時に得ることができる。これにより接合材３等へのクラックを防止することができ、その結果、従来の半導体装置よりも信頼性を向上させることができる。   As described above, in the present embodiment, thermal stress is reduced by bringing the thermal expansion coefficient of the metal plate 2 close to the thermal expansion coefficient of the semiconductor element 1, and the metal plate 2 near the mounting surface 7 of the semiconductor element 1 is easily deformed. Both effects of reducing thermal stress can be obtained at the same time. As a result, cracks in the bonding material 3 and the like can be prevented, and as a result, the reliability can be improved as compared with the conventional semiconductor device.

また、低熱膨張部８ａは上記のように多孔質状の例えばモリブデン中に金属板２を構成する金属であるアルミニウムが含浸した構造としたことで、多孔質状のモリブデンの孔部にアルミニウムが入り込むというアンカー効果のため、低熱膨張部８ａとそれを取り囲む高熱伝導部との接合は強固な構造になる。従って、低熱膨張部８ａと高熱伝導部との接続部分では、低熱膨張部８ａと高熱伝導部との熱膨張係数差による熱応力に十分に耐えることができる。   Further, the low thermal expansion portion 8a has a structure in which aluminum, which is a metal constituting the metal plate 2, is impregnated with porous, for example, molybdenum as described above, so that the aluminum enters the pores of the porous molybdenum. Because of the anchor effect, the joint between the low thermal expansion portion 8a and the high thermal conduction portion surrounding it has a strong structure. Therefore, the connection portion between the low thermal expansion portion 8a and the high thermal conduction portion can sufficiently withstand the thermal stress due to the difference in thermal expansion coefficient between the low thermal expansion portion 8a and the high thermal conduction portion.

また、低熱膨張部８ａは上記のように多孔質状の例えばモリブデン中にアルミニウムが含浸した構造としたことで、アルミニウムよりも電気伝導率の低いモリブデンによる多孔質体の電気伝導率を、含浸したアルミニウムが補い、モリブデン単体で用いる場合よりも電気伝導率を上げることができる。同様に熱伝導率についても、アルミニウムが含浸することによって、向上させることができる。   Further, the low thermal expansion portion 8a has a structure in which aluminum is impregnated with porous, for example, molybdenum as described above, so that the electrical conductivity of the porous body made of molybdenum having a lower electrical conductivity than aluminum is impregnated. The electrical conductivity can be increased as compared with the case where aluminum is supplemented and molybdenum alone is used. Similarly, thermal conductivity can be improved by impregnation with aluminum.

また、低熱膨張部８ａが多孔質状であるため、アルミニウム溶湯を流し込む製造時において、アルミニウム溶湯が多孔質状の低熱膨張部８ａを通って半導体素子１の搭載面７に染み出すことで、搭載面７と低熱膨張部８ａとの間に空隙ができにくくなり、製品の歩留まりが向上する。   Further, since the low thermal expansion portion 8a is porous, the molten aluminum oozes out to the mounting surface 7 of the semiconductor element 1 through the porous low thermal expansion portion 8a at the time of manufacturing by pouring the molten aluminum. It becomes difficult to form a gap between the surface 7 and the low thermal expansion portion 8a, and the yield of products is improved.

さらに、後で述べるように本発明は、このような構造をアルミニウムの溶湯を流しこみ、一回で製造することができるという効率的な製造方法により容易に製造できるという利点がある。   Further, as will be described later, the present invention has an advantage that such a structure can be easily manufactured by an efficient manufacturing method in which a molten aluminum is poured into the structure and can be manufactured at a time.

〈半導体装置の製造方法〉
次に、本実施の形態の半導体装置の製造方法について説明する。例えば図１の構造を実現するためには、まず、金属板２を所定の形状に作るための鋳型中に、あらかじめモリブデンやセラミックス等からなる多孔質体（低熱膨張部８ａ）を、金属板２の搭載面７に来るように保持する。加えて、絶縁板４を金属板２の搭載面７と対向する面に配置する。そこへ、アルミニウム溶湯を真空または不活性雰囲気中で鋳型中に加圧注入し、金属板２の成型と多孔質体へのアルミニウム溶湯の含浸を同時に行う。 <Method for Manufacturing Semiconductor Device>
Next, a method for manufacturing the semiconductor device of the present embodiment will be described. For example, in order to realize the structure of FIG. 1, first, a porous body (low thermal expansion portion 8 a) made of molybdenum, ceramics, or the like is previously placed in a mold for making the metal plate 2 in a predetermined shape. Is held so as to come to the mounting surface 7. In addition, the insulating plate 4 is disposed on a surface facing the mounting surface 7 of the metal plate 2. There, the molten aluminum is pressurized and injected into the mold in a vacuum or an inert atmosphere, and the metal plate 2 is molded and the porous body is impregnated with the molten aluminum simultaneously.

このように本実施の形態の半導体装置の製造方法は、金属板２を形成する鋳型中に多孔質体１１ａ（１１ｂ）を所定の位置に固定する工程と、金属板２の構成金属の溶湯を鋳型中に充填して金属板２を形成するとともに、多孔質体１１ａ（１１ｂ）に金属板２の構成金属の溶湯を含浸させる工程とを有する。本製造方法では、金属板２の成型による形成、金属板２と多孔質体１１ａ（１１ｂ）（低熱膨張部８ａ）との接合、多孔質体１１ａ（１１ｂ）へのアルミニウム溶湯の含浸、金属板２と絶縁板４との接合を同時に行うことができるので、金属板２と低熱膨張部８ａを個別に製造し、後からろう材等で両者を接合する製造方法と比較して、製造工程を効率化できる。   As described above, in the method of manufacturing the semiconductor device according to the present embodiment, the step of fixing the porous body 11a (11b) in a predetermined position in the mold for forming the metal plate 2 and the molten metal of the constituent metal of the metal plate 2 are performed. And filling the mold to form the metal plate 2 and impregnating the porous body 11a (11b) with the molten metal of the constituent metal of the metal plate 2. In this manufacturing method, the metal plate 2 is formed by molding, the metal plate 2 and the porous body 11a (11b) (low thermal expansion portion 8a) are joined, the porous body 11a (11b) is impregnated with molten aluminum, the metal plate 2 and the insulating plate 4 can be joined at the same time, so that the metal plate 2 and the low thermal expansion part 8a are manufactured separately, and the manufacturing process is compared with the manufacturing method in which both are joined with a brazing material later. Increase efficiency.

また、鋳型中へのアルミニウム溶湯の加圧注入による金属板２の鋳造と同時に、絶縁板４を鋳型中に保持し、ベース板５の鋳造も加えて行うことも可能である。このようにすることで、金属板２の成型、金属板２と多孔質体１１ａ（１１ｂ）（低熱膨張部８ａ）との接合、多孔質体１１ａ（１１ｂ）へのアルミニウム溶湯の含浸、金属板２と絶縁板４との接合、並びにベース板５の成型、絶縁板４とベース板５との接合を同時に行うことができ、製造工程をより効率化できる。   Further, simultaneously with casting of the metal plate 2 by pressure injection of molten aluminum into the mold, the insulating plate 4 can be held in the mold and the base plate 5 can be cast. In this way, the metal plate 2 is molded, the metal plate 2 is joined to the porous body 11a (11b) (low thermal expansion portion 8a), the molten aluminum is impregnated into the porous body 11a (11b), the metal plate 2 and the insulating plate 4 can be joined, the base plate 5 can be molded, and the insulating plate 4 and the base plate 5 can be joined at the same time, so that the manufacturing process can be made more efficient.

また、多孔質体１１ａ（１１ｂ）を鋳型に保持する前に、それ自体にメッキをしても良い。例えば多孔質体がモリブデンで有る場合には、それ自体にニッケルメッキをすると良い。このようにすると、鋳造の際にモリブデンとアルミニウムの間で脆い金属間化合物が生成されるのを防ぐことができ、金属板２と低熱膨張部８ａの接合の信頼性を増すことができる。   Alternatively, the porous body 11a (11b) may be plated before it is held in the mold. For example, when the porous body is made of molybdenum, it is preferable to perform nickel plating on itself. If it does in this way, it can prevent that a brittle intermetallic compound is generated between molybdenum and aluminum at the time of casting, and the reliability of joining of metal plate 2 and low thermal expansion part 8a can be increased.

《第２の実施の形態》
次に、本発明の第２の実施の形態を図３に示す。図３は本実施の形態の半導体装置の断面図である。本実施の形態が第１の実施の形態と異なる点は、低熱膨張部８ｂの構造である。
図４（Ａ）、（Ｂ）は、図３の低熱膨張部８ｂを構成する多孔質体１１ｃ、１１ｄの構造を示す断面図である。図４（Ａ）に示すように多孔質体１１ｃは例えばモリブデンからなる複数の細線を布状にした構造からなっているか、または図４（Ｂ）に示すように多孔質体１１ｄが例えばモリブデンからなる複数の細線を縦横に重ねた構造からなっている。なお、図４（Ａ）、（Ｂ）に示す空隙１２ｃ、１２ｄは、垂直方向についても水平方向についても均等に分布している。これらの空隙１２ｃ、１２ｄに金属板２の構成金属であるアルミニウムが含浸される。
このように本実施の形態では、低熱膨張部８ｂが、金属板２よりも熱膨張係数が低い複数の細線を布状にした構造、または複数の前記細線を縦横に重ねた構造からなっている。本実施の形態においても、低熱膨張であるモリブデン等からなり、隙間を多く含む構造になっている低熱膨張部８ｂを設けたことから、第１の実施の形態と同様の効果を得られる。なお、上記細線は、モリブデンやタングステン等の金属に限らず、セラミックス、グラスファイバー、カーボンファイバー等を用いても良い。なお、これらの細線の表面に凹凸が設けられていると金属板２との密着性を増すことができる。
本実施の形態では、多孔質体に複数の細線を布状にした構造、または複数の前記細線を縦横に重ねた構造を用いることによって、多孔質体中の空孔率を制御することが容易になっている。よって、最適な空孔率にすることで、多孔質体中にアルミニウムを確実に含浸させることができ、低熱膨張部の高熱伝導化・高電気伝導度化を確実に行うことができる。 << Second Embodiment >>
Next, a second embodiment of the present invention is shown in FIG. FIG. 3 is a cross-sectional view of the semiconductor device of this embodiment. The present embodiment is different from the first embodiment in the structure of the low thermal expansion portion 8b.
4A and 4B are cross-sectional views showing the structures of the porous bodies 11c and 11d constituting the low thermal expansion part 8b of FIG. As shown in FIG. 4 (A), the porous body 11c has a structure in which a plurality of thin wires made of, for example, molybdenum are cloth-like, or as shown in FIG. 4 (B), the porous body 11d is made of, for example, molybdenum. It has a structure in which multiple thin lines are stacked vertically and horizontally. Note that the gaps 12c and 12d shown in FIGS. 4A and 4B are evenly distributed both in the vertical direction and in the horizontal direction. These gaps 12c and 12d are impregnated with aluminum which is a constituent metal of the metal plate 2.
As described above, in the present embodiment, the low thermal expansion portion 8b has a structure in which a plurality of thin wires having a thermal expansion coefficient lower than that of the metal plate 2 are formed in a cloth shape, or a structure in which the plurality of thin wires are stacked vertically and horizontally. . Also in the present embodiment, since the low thermal expansion portion 8b made of molybdenum having a low thermal expansion and having a structure including many gaps is provided, the same effect as that of the first embodiment can be obtained. The fine wire is not limited to a metal such as molybdenum or tungsten, but may be ceramic, glass fiber, carbon fiber, or the like. In addition, if the surface of these fine lines is provided with irregularities, the adhesion to the metal plate 2 can be increased.
In the present embodiment, it is easy to control the porosity in the porous body by using a structure in which a plurality of fine lines are cloth-like on the porous body or a structure in which a plurality of the thin lines are stacked vertically and horizontally. It has become. Therefore, by setting the optimum porosity, aluminum can be surely impregnated in the porous body, and the high thermal conductivity and high electrical conductivity of the low thermal expansion portion can be reliably performed.

《第３の実施の形態》
次に、本発明の第３の実施の形態を図５に示す。図５は本実施の形態の半導体装置の断面図である。本実施の形態が第１の実施の形態と異なる点は、低熱膨張部８ｃの構造である。
図６は、図５の低熱膨張部８ｃを構成する多孔質体１１ｅの構造を示す斜視図である。本実施の形態では、図６に示すように多孔質体１１ｅがモリブデンまたはセラミックスからなる板に、表裏を貫通する表裏貫通孔１２ｅを設けた構造になっている。表裏貫通孔１２ｅに金属板２の構成金属であるアルミニウムが含浸される。
本実施の形態においても、低熱膨張であるモリブデン等からなり、隙間を多く含む構造になっている低熱膨張部８ｃを設けたことから、第１の実施の形態と同様の効果を得られる。 << Third Embodiment >>
Next, FIG. 5 shows a third embodiment of the present invention. FIG. 5 is a cross-sectional view of the semiconductor device of this embodiment. The present embodiment differs from the first embodiment in the structure of the low thermal expansion portion 8c.
6 is a perspective view showing the structure of the porous body 11e constituting the low thermal expansion portion 8c of FIG. In the present embodiment, as shown in FIG. 6, the porous body 11e has a structure in which front and back through holes 12e penetrating the front and back are provided on a plate made of molybdenum or ceramics. The front and back through holes 12e are impregnated with aluminum which is a constituent metal of the metal plate 2.
Also in the present embodiment, since the low thermal expansion portion 8c made of molybdenum having a low thermal expansion and having a structure including many gaps is provided, the same effect as that of the first embodiment can be obtained.

《第４の実施の形態》
次に、本発明の第４の実施の形態を図７に示す。図７は本実施の形態の半導体装置の断面図である。本実施の形態が第１の実施の形態と異なる点は、モリブデンまたはセラミックスでできた低熱膨張部８ｄが半導体素子１の搭載面７を取り囲むように環状構造をなしていて、金属板２に埋設されている点である。すなわち、低熱膨張部８ｄは、金属板２の半導体素子１を搭載する部分を取り囲むように配置された環状体からなっている。 << Fourth Embodiment >>
Next, FIG. 7 shows a fourth embodiment of the present invention. FIG. 7 is a cross-sectional view of the semiconductor device of this embodiment. This embodiment differs from the first embodiment in that the low thermal expansion portion 8d made of molybdenum or ceramics has an annular structure so as to surround the mounting surface 7 of the semiconductor element 1, and is embedded in the metal plate 2. It is a point that has been. That is, the low thermal expansion portion 8d is formed of an annular body arranged so as to surround a portion of the metal plate 2 on which the semiconductor element 1 is mounted.

本構造においては、低熱膨張部８ｄが半導体素子１の搭載面７を取り囲んでいるため、半導体素子１の搭載面７近傍の金属板２の熱膨張は抑制される。従って、本実施の形態においても第１の実施の形態と同様に、半導体素子１の搭載面７近傍の金属板２の等価的な熱膨張係数は小さくなり、半導体素子１の熱膨張係数に近づくことで、熱応力を抑制することができる。   In this structure, since the low thermal expansion portion 8d surrounds the mounting surface 7 of the semiconductor element 1, thermal expansion of the metal plate 2 near the mounting surface 7 of the semiconductor element 1 is suppressed. Accordingly, also in the present embodiment, as in the first embodiment, the equivalent thermal expansion coefficient of the metal plate 2 in the vicinity of the mounting surface 7 of the semiconductor element 1 becomes small and approaches the thermal expansion coefficient of the semiconductor element 1. Thus, thermal stress can be suppressed.

さらに、半導体素子１の搭載面７は軟らかいアルミニウムでできているため、変形しやすくなっている。従って、半導体素子１と金属板２との間の熱膨張係数差により半導体素子１と金属板２との接続部分で歪が生じたとしても、金属板２が変形することで熱応力を緩和することができる。   Furthermore, since the mounting surface 7 of the semiconductor element 1 is made of soft aluminum, it is easily deformed. Therefore, even if distortion occurs in the connection portion between the semiconductor element 1 and the metal plate 2 due to the difference in thermal expansion coefficient between the semiconductor element 1 and the metal plate 2, the thermal stress is reduced by the deformation of the metal plate 2. be able to.

《第５の実施の形態》
次に、本発明の第５の実施の形態を図８に示す。図８は本実施の形態の半導体装置の断面図である。本実施の形態が第１の実施の形態と異なる点は、金属板２中の低熱膨張部８ａ（図１の第１の実施の形態と同様の構造）の位置が、半導体素子１の搭載面７より下にＤ１分だけずれて埋設されている点にある。１３は金属板２の半導体素子１の搭載面７と、低熱膨張部８ａとの間に設けられたアルミニウム層である。 << Fifth Embodiment >>
Next, a fifth embodiment of the present invention is shown in FIG. FIG. 8 is a cross-sectional view of the semiconductor device of this embodiment. This embodiment is different from the first embodiment in that the position of the low thermal expansion portion 8a (the same structure as that of the first embodiment in FIG. 1) in the metal plate 2 is the mounting surface of the semiconductor element 1. The point is that it is buried below 7 by a distance of D1. Reference numeral 13 denotes an aluminum layer provided between the mounting surface 7 of the semiconductor element 1 of the metal plate 2 and the low thermal expansion portion 8a.

本構造においても、半導体素子１の搭載面７近傍の金属板２の熱膨張は、低熱膨張部８ａによって抑制される。従って、本実施の形態においても第１の実施の形態と同様に、半導体素子１と金属板２の熱膨張係数差は小さくなり、熱膨張係数差による応力が抑制され、半導体装置１０の信頼性が向上する。
さらに、第４の実施の形態と同様に半導体素子１の搭載面７に、モリブデンよりもヤング率の低いアルミニウム層１３が存在していることで、半導体素子１の直下の金属板２自体が変形しやすくなっており、応力が緩和されやすくなる。
なお、低熱膨張部８ａの代わりに、図４（Ａ）に示した複数の細線を布状にした構造、図４（Ｂ）に示した細線を縦横に重ねた構造、または図６に示した板に表裏貫通孔１２ｅを有する構造を用いても良い。 Also in this structure, the thermal expansion of the metal plate 2 in the vicinity of the mounting surface 7 of the semiconductor element 1 is suppressed by the low thermal expansion portion 8a. Accordingly, also in the present embodiment, as in the first embodiment, the difference in thermal expansion coefficient between the semiconductor element 1 and the metal plate 2 is reduced, the stress due to the difference in thermal expansion coefficient is suppressed, and the reliability of the semiconductor device 10 is reduced. Will improve.
Further, as in the fourth embodiment, the aluminum layer 13 having a Young's modulus lower than that of molybdenum is present on the mounting surface 7 of the semiconductor element 1, so that the metal plate 2 itself directly under the semiconductor element 1 is deformed. The stress is easily relieved.
In addition, instead of the low thermal expansion portion 8a, a structure in which a plurality of fine wires shown in FIG. 4 (A) is formed in a cloth shape, a structure in which the thin wires shown in FIG. 4 (B) are stacked vertically and horizontally, or shown in FIG. You may use the structure which has the front and back through-holes 12e in a board.

《第６の実施の形態》
次に、本発明の第６の実施の形態における半導体装置の製造装置を図９に示す。図９は、本実施の形態の半導体装置の製造装置の断面図である。図９において、２０は鋳型、２１は鋳型２０の底面に一体に形成された横方向固定用突起、２２は鋳型２０の底面に一体に形成された縦方向固定用突起、１１は多孔質体である。 << Sixth Embodiment >>
Next, FIG. 9 shows a semiconductor device manufacturing apparatus according to the sixth embodiment of the present invention. FIG. 9 is a cross-sectional view of the semiconductor device manufacturing apparatus of the present embodiment. In FIG. 9, 20 is a mold, 21 is a lateral fixing protrusion integrally formed on the bottom surface of the mold 20, 22 is a vertical fixing protrusion integrally formed on the bottom surface of the mold 20, and 11 is a porous body. is there.

金属板２は鋳型２０を用いて鋳造される。鋳型２０の底面には、モリブデンやセラミックスからなる多孔質体１１を横方向の所定の位置に保持するための横方向固定用突起２１と、多孔質体１１を半導体素子１（図８参照）の搭載面７からＤ１だけ離して保持するための縦方向固定用突起２２とが設けられている。これらの突起２１、２２は柱状をしている。突起２１、２２の形状、数、配置位置は、適宜設定可能である。すなわち、多孔質体１１の搭載面７に平行でかつ近い側の面に接し、鋳型２０中における多孔質体１１の高さを決め、多孔質体１１の側面に接し、鋳型２０中における多孔質体１１の水平方向の位置を決める複数の突起２１、２２が、鋳型２０の底面に設けられている。   The metal plate 2 is cast using a mold 20. On the bottom surface of the mold 20, a lateral fixing protrusion 21 for holding the porous body 11 made of molybdenum or ceramics at a predetermined position in the lateral direction, and the porous body 11 of the semiconductor element 1 (see FIG. 8). A vertical fixing projection 22 is provided to hold the mounting surface 7 away from the mounting surface 7 by D1. These protrusions 21 and 22 are columnar. The shape, number, and arrangement position of the protrusions 21 and 22 can be set as appropriate. That is, the surface of the porous body 11 that is parallel to and close to the mounting surface 7 is determined, the height of the porous body 11 in the mold 20 is determined, the height of the porous body 11 is contacted, and the porous body 11 is in contact with the side surface. A plurality of protrusions 21 and 22 for determining the horizontal position of the body 11 are provided on the bottom surface of the mold 20.

このような鋳型２０にアルミニウム溶湯を注入することで、多孔質体１１が横方向及び縦方向の所定位置に正確に埋設された金属板２を得ることができる。このように本実施の形態の製造装置においては、金属板２中の横方向の正確な所定の位置に多孔質体１１（図８の低熱膨張部８ａ）が配置できることによって、半導体素子１の搭載面７の直下を正確に低熱膨張化し、確実に熱応力を減らすことができる。また、金属板２中の縦方向の正確な所定の位置に多孔質体が配置できることによって、半導体素子１の搭載面７の直下（金属板２の半導体素子１の搭載面７と、低熱膨張部８ａとの間）にアルミニウム層（図８の１３）を正確に形成することができ、このアルミニウム層の変形による熱応力緩和を確実に行うことができる。   By injecting molten aluminum into such a mold 20, it is possible to obtain the metal plate 2 in which the porous body 11 is accurately embedded at predetermined positions in the horizontal and vertical directions. As described above, in the manufacturing apparatus of the present embodiment, the porous body 11 (low thermal expansion portion 8a in FIG. 8) can be disposed at an accurate predetermined position in the lateral direction in the metal plate 2, thereby mounting the semiconductor element 1. The thermal expansion can be reliably reduced by accurately reducing the thermal expansion directly under the surface 7. Further, since the porous body can be arranged at a predetermined position in the vertical direction in the metal plate 2, the semiconductor element 1 is mounted directly below the mounting surface 7 (the mounting surface 7 of the semiconductor element 1 on the metal plate 2 and the low thermal expansion portion). 8a), an aluminum layer (13 in FIG. 8) can be accurately formed, and thermal stress relaxation due to deformation of the aluminum layer can be reliably performed.

《第７の実施の形態》
次に、本発明の第７の実施の形態における半導体装置の製造装置を図１０に示す。図１０は、本実施の形態の半導体装置の製造装置の断面図である。図１０において、２３は横方向・縦方向固定用突起である。
本実施の形態が第６の実施の形態と異なる点は、第６の実施の形態の横方向固定用突起２１と、縦方向固定用突起２２（図９）との代わりに、縦方向・横方向固定用突起２３を設けたことである。これらの突起２３も柱状をしており、各上部に段差が形成されている。すなわち、突起２３の上部に、鋳型２０中における多孔質体１１の高さと水平方向の位置を決める段差が設けられている。突起２３の形状、数、設置位置は、適宜設定可能である。突起２３は多孔質体１１の４つの側面にもしくは搭載面７に近い側の４つの頂点に対して適宜の本数設ける。なお、多孔質体１１の４つの側面を取り囲むように長く設けることも可能である。
本実施の形態では、第６の実施の形態よりも少ない突起の本数で第６の実施の形態と同等の効果を得ることができる。 << Seventh Embodiment >>
Next, FIG. 10 shows a semiconductor device manufacturing apparatus according to the seventh embodiment of the present invention. FIG. 10 is a cross-sectional view of the semiconductor device manufacturing apparatus of the present embodiment. In FIG. 10, reference numeral 23 denotes a horizontal / vertical fixing pin.
This embodiment is different from the sixth embodiment in that, instead of the horizontal fixing protrusion 21 and the vertical fixing protrusion 22 (FIG. 9) of the sixth embodiment, the vertical and horizontal protrusions are used. That is, the direction fixing projection 23 is provided. These protrusions 23 are also columnar, and a step is formed at each upper portion. That is, a step for determining the height of the porous body 11 in the mold 20 and the position in the horizontal direction is provided above the protrusion 23. The shape, number, and installation position of the protrusions 23 can be set as appropriate. An appropriate number of protrusions 23 are provided on the four side surfaces of the porous body 11 or on the four apexes on the side close to the mounting surface 7. It is also possible to provide a long length so as to surround the four side surfaces of the porous body 11.
In the present embodiment, the same effect as in the sixth embodiment can be obtained with a smaller number of protrusions than in the sixth embodiment.

《第８の実施の形態》
次に、本発明の第８の実施の形態における半導体装置の製造装置を図１１に示す。図１１は、本実施の形態の半導体装置の製造装置の断面図である。図１１において、２４は横方向固定用足、２５は縦方向固定用足である。
本実施の形態が第６の実施の形態と異なる点は、多孔質体１１の固定の機構を、第６の実施の形態（図９）の鋳型２０の底面に設けられた横方向固定用突起２１から、多孔質体１１の側面に設けられた横方向固定用足２４に変更したことと、また多孔質体を半導体素子１（図８参照）の搭載面７からＤ１だけ離して保持するための機構を、第６の実施の形態の鋳型２０の底面に設けられた縦方向固定用突起２２から、多孔質体の搭載面７に平行でかつ近い側の面に設けられた縦方向固定用足２５に変更したことである。これらの足２４、２５も柱状をしている。すなわち、多孔質体１１に、鋳型２０中における多孔質体１１の高さと水平方向の位置を決める複数の足２４、２５が設けられている。これらの足２４、２５は、多孔質体１１の搭載面７に平行でかつ近い側の面に設けられ、鋳型２０中における多孔質体１１の高さを決める複数の足２５と、多孔質体１１の側面に設けられ、鋳型２０中における多孔質体１１の水平方向の位置を決める複数の足２４からなっている。足２４、２５の形状、数、設置位置は、適宜設定可能である。足２４は多孔質体１１の４つの側面に対して適宜の本数設ける。なお、足２４を多孔質体１１の４つの側面に沿って該４つの側面をぐるりと取り囲むように長く設けても良い。また、足２５も多孔質体１１の搭載面７に平行でかつ近い側の面に適宜の本数設けても良いし、足２５を多孔質体１１の搭載面７に平行でかつ近い側の面に矩形枠状に設けることも可能である。 << Eighth Embodiment >>
Next, FIG. 11 shows a semiconductor device manufacturing apparatus according to the eighth embodiment of the present invention. FIG. 11 is a cross-sectional view of the semiconductor device manufacturing apparatus of the present embodiment. In FIG. 11, 24 is a horizontal direction fixing foot, and 25 is a vertical direction fixing foot.
This embodiment is different from the sixth embodiment in that the fixing mechanism of the porous body 11 is the same as the lateral fixing protrusion provided on the bottom surface of the mold 20 of the sixth embodiment (FIG. 9). 21 is changed to the lateral fixing foot 24 provided on the side surface of the porous body 11, and the porous body is held away from the mounting surface 7 of the semiconductor element 1 (see FIG. 8) by D1. The vertical direction fixing protrusion 22 provided on the surface parallel to and close to the mounting surface 7 of the porous body from the vertical direction fixing protrusion 22 provided on the bottom surface of the mold 20 of the sixth embodiment. That is, the foot 25 is changed. These legs 24 and 25 are also columnar. That is, the porous body 11 is provided with a plurality of legs 24 and 25 that determine the height and the horizontal position of the porous body 11 in the mold 20. The legs 24 and 25 are provided on a surface parallel to and close to the mounting surface 7 of the porous body 11, and a plurality of legs 25 that determine the height of the porous body 11 in the mold 20, and the porous body 11 includes a plurality of legs 24 that determine the horizontal position of the porous body 11 in the mold 20. The shape, number, and installation position of the legs 24 and 25 can be set as appropriate. An appropriate number of legs 24 are provided on the four side surfaces of the porous body 11. The legs 24 may be provided long along the four side surfaces of the porous body 11 so as to surround the four side surfaces. In addition, an appropriate number of legs 25 may be provided on the surface that is parallel to and close to the mounting surface 7 of the porous body 11, and the feet 25 are surfaces that are parallel and close to the mounting surface 7 of the porous body 11. It is also possible to provide a rectangular frame.

このような多孔質体１１を用いることにより、第６の実施の形態と同様の効果を得ることができる。また、さらに、第６の実施の形態及び第７の実施の形態においては、鋳型２０の内面にそれぞれ突起２１、２２、２３が存在しているため、金属板２の半導体素子１の搭載面７に、これらの突起２１、２２、２３による穴が形成されてしまうが、多孔質体１１に横方向固定用足２４、縦方向固定用足２５を設けた本実施の形態では、搭載面７に穴が形成されないことから、半導体素子１の搭載が容易になる。   By using such a porous body 11, the same effect as that of the sixth embodiment can be obtained. Furthermore, in the sixth embodiment and the seventh embodiment, since the protrusions 21, 22, and 23 exist on the inner surface of the mold 20, the mounting surface 7 of the semiconductor element 1 on the metal plate 2. In addition, in the present embodiment in which the lateral fixing feet 24 and the vertical fixing feet 25 are provided in the porous body 11, holes are formed in the mounting surface 7. Since no hole is formed, the semiconductor element 1 can be easily mounted.

《第９の実施の形態》
次に、本発明の第９の実施の形態における半導体装置の製造装置を図１２に示す。図１２は、本実施の形態の半導体装置の製造装置の断面図である。図１２において、２６は横方向・縦方向固定用足である。
本実施の形態が第８の実施の形態と異なる点は、第８の実施の形態の横方向固定用足２４と、縦方向固定用足２５の代わりに、縦方向・横方向固定用突起２６を設けたことである。これらの突起２６も柱状をしている。足２６の形状、数、設置位置は、適宜設定可能である。本実施の形態では、第８の実施の形態よりも少ない本数の足で第８の実施の形態と同等の効果を得ることができる。 << Ninth embodiment >>
Next, FIG. 12 shows a semiconductor device manufacturing apparatus according to the ninth embodiment of the present invention. FIG. 12 is a cross-sectional view of the semiconductor device manufacturing apparatus of the present embodiment. In FIG. 12, reference numeral 26 denotes a foot for fixing in the horizontal and vertical directions.
The present embodiment is different from the eighth embodiment in that, in place of the lateral fixing feet 24 and the vertical fixing feet 25 of the eighth embodiment, the vertical and lateral fixing protrusions 26 are used. It is to have established. These protrusions 26 are also columnar. The shape, number and installation position of the feet 26 can be set as appropriate. In the present embodiment, the same effect as in the eighth embodiment can be obtained with a smaller number of legs than in the eighth embodiment.

以上、説明したように、本発明によれば、半導体素子１と金属板２との接合部分において、熱応力を緩和することができるという効果があり、半導体装置１０の信頼性を増すことができる。また、本発明の構造はアルミニウムの溶湯で一回で鋳造するという製造方法を採っていることで、効率的な製造ができるという利点がある。
なお、以上説明した実施の形態は、本発明の理解を容易にするために記載されたものであって、本発明を限定するために記載されたものではない。従って、上記実施の形態に開示された各要素は、本発明の技術的範囲に属する全ての設計変更や均等物をも含む趣旨である。 As described above, according to the present invention, there is an effect that the thermal stress can be relaxed at the joint portion between the semiconductor element 1 and the metal plate 2, and the reliability of the semiconductor device 10 can be increased. . Further, the structure of the present invention has an advantage that it can be efficiently manufactured by adopting a manufacturing method in which casting is performed once with a molten aluminum.
The embodiment described above is described in order to facilitate understanding of the present invention, and is not described in order to limit the present invention. Therefore, each element disclosed in the above embodiment includes all design changes and equivalents belonging to the technical scope of the present invention.

本発明の第１の実施の形態による半導体装置の断面図である。1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. 本発明の第１の実施の形態による多孔質体の構造図である。1 is a structural diagram of a porous body according to a first embodiment of the present invention. 本発明の第２の実施の形態による半導体装置の断面図である。It is sectional drawing of the semiconductor device by the 2nd Embodiment of this invention. 本発明の第２の実施の形態による多孔質体の構造図である。FIG. 4 is a structural diagram of a porous body according to a second embodiment of the present invention. 本発明の第３の実施の形態による半導体装置の断面図である。It is sectional drawing of the semiconductor device by the 3rd Embodiment of this invention. 本発明の第３の実施の形態による表裏貫通孔を有する多孔質体の構造である。It is the structure of the porous body which has the front and back through-hole by the 3rd Embodiment of this invention. 本発明の第４の実施の形態による半導体装置の断面図である。It is sectional drawing of the semiconductor device by the 4th Embodiment of this invention. 本発明の第５の実施の形態による半導体装置装置の断面図である。It is sectional drawing of the semiconductor device apparatus by the 5th Embodiment of this invention. 本発明の第６の実施の形態による半導体装置の製造装置の断面図である。It is sectional drawing of the manufacturing apparatus of the semiconductor device by the 6th Embodiment of this invention. 本発明の第７の実施の形態による半導体装置の製造装置の断面図である。It is sectional drawing of the manufacturing apparatus of the semiconductor device by the 7th Embodiment of this invention. 本発明の第８の実施の形態による半導体装置の製造装置の断面図である。It is sectional drawing of the manufacturing apparatus of the semiconductor device by the 8th Embodiment of this invention. 本発明の第９の実施の形態による半導体装置の製造装置の断面図である。It is sectional drawing of the manufacturing apparatus of the semiconductor device by the 9th Embodiment of this invention.

符号の説明Explanation of symbols

１…半導体素子 ２…金属板
３…接合材 ４…絶縁板
５…ベース板 ６…絶縁回路基板
７…搭載面 ８ａ、８ｂ、８ｃ、８ｄ…低熱膨張部
１０…半導体装置
１１、１１ａ、１１ｂ、１１ｃ、１１ｄ、１１ｅ…多孔質体
１２ａ、１２ｂ、１２ｃ、１２ｄ、１２ｅ…空隙
１２ｅ…表裏貫通孔
１３…アルミニウム層
２０…鋳型 ２１…横方向固定用突起
２２…縦方向固定用突起 ２３…横方向・縦方向固定用突起
２４…横方向固定用足 ２５…縦方向固定用足
２６…横方向・縦方向固定用足 DESCRIPTION OF SYMBOLS 1 ... Semiconductor element 2 ... Metal plate 3 ... Bonding material 4 ... Insulating plate 5 ... Base plate 6 ... Insulated circuit board 7 ... Mounting surface 8a, 8b, 8c, 8d ... Low thermal expansion part 10 ... Semiconductor device 11, 11a, 11b, 11c, 11d, 11e ... porous bodies 12a, 12b, 12c, 12d, 12e ... void 12e ... front and back through holes 13 ... aluminum layer 20 ... mold 21 ... lateral direction fixing projection 22 ... vertical direction fixing projection 23 ... lateral direction・ Vertical fixing protrusion 24 .. Horizontal fixing foot 25. Vertical fixing foot 26. Horizontal and vertical fixing foot

Claims (17)

半導体素子を搭載する金属板を備えた半導体装置において、
前記金属板の前記半導体素子を搭載する部分またはその近傍に、
前記金属板よりも熱膨張係数が低い多孔質体からなる低熱膨張部が埋設されていることを特徴とする半導体装置。 In a semiconductor device including a metal plate on which a semiconductor element is mounted,
In the portion where the semiconductor element is mounted on the metal plate or in the vicinity thereof,
A semiconductor device, wherein a low thermal expansion portion made of a porous body having a lower thermal expansion coefficient than that of the metal plate is embedded. 半導体素子を搭載する金属板を備えた半導体装置において、
前記金属板よりも熱膨張係数が低く、
前記金属板の前記半導体素子を搭載する部分を取り囲む部分またはその近傍に環状体からなる、
低熱膨張部が埋設されていることを特徴とする半導体装置。 In a semiconductor device including a metal plate on which a semiconductor element is mounted,
The coefficient of thermal expansion is lower than that of the metal plate,
A portion surrounding the portion on which the semiconductor element is mounted of the metal plate or a vicinity thereof is formed of an annular body.
A semiconductor device, wherein a low thermal expansion portion is embedded. 前記金属板の前記半導体素子を搭載する面の反対側の面に、絶縁板が接合されていることを特徴とする請求項１または２記載の半導体装置。   3. The semiconductor device according to claim 1, wherein an insulating plate is bonded to a surface of the metal plate opposite to a surface on which the semiconductor element is mounted. 前記低熱膨張部が、前記金属板よりも熱膨張係数が低い複数の細線を布状にした構造、または複数の前記細線を縦横に重ねた構造からなることを特徴とする請求項１乃至３記載の半導体装置。   4. The low thermal expansion portion has a structure in which a plurality of fine wires having a thermal expansion coefficient lower than that of the metal plate are formed in a cloth shape, or a structure in which a plurality of the thin wires are stacked vertically and horizontally. Semiconductor device. 前記低熱膨張部には前記金属板の構成金属が含浸されていることを特徴とする請求項１乃至４のいずれか記載の半導体装置。   The semiconductor device according to claim 1, wherein the low thermal expansion portion is impregnated with a constituent metal of the metal plate. 前記低熱膨張部が金属で構成されることを特徴とする請求項１乃至５記載の半導体装置。   6. The semiconductor device according to claim 1, wherein the low thermal expansion portion is made of metal. 前記多孔質体がセラミックス、炭素、ガラス、もしくはこれらの複合体で構成されることを特徴とする請求項１乃至４のいずれか記載の半導体装置。   The semiconductor device according to claim 1, wherein the porous body is made of ceramics, carbon, glass, or a composite thereof. 前記低熱膨張部にそれ自体の金属または前記金属板を構成する金属と異なる金属でメッキがされていることを特徴とする請求項６または７記載の半導体装置。   8. The semiconductor device according to claim 6, wherein the low thermal expansion portion is plated with a metal different from a metal constituting the metal plate or the metal constituting the metal plate. 請求項１記載の半導体装置の製造方法であって、
前記金属板を形成する鋳型中に前記低熱膨張部を所定の位置に固定する工程と、
前記金属板の構成金属の溶湯を前記鋳型中に充填して前記金属板を形成するとともに、前記多孔質体に前記金属板の構成金属の溶湯を含浸させる工程と
を有することを特徴とする半導体装置の製造方法。 A method of manufacturing a semiconductor device according to claim 1,
Fixing the low thermal expansion portion in a predetermined position in a mold for forming the metal plate;
Filling the molten metal of the metal constituting the metal plate into the mold to form the metal plate, and impregnating the porous body with the molten metal of the metal constituting the metal plate. Device manufacturing method. 前記鋳型中に絶縁板を所定の位置に固定する工程を有することを特徴とする請求項９記載の半導体装置の製造方法。   The method for manufacturing a semiconductor device according to claim 9, further comprising a step of fixing an insulating plate in a predetermined position in the mold. 前記低熱膨張部の前記半導体素子を搭載する面からの距離を決めるべく、前記鋳型の底面に設けられた高さが揃った複数の突起に、前記低熱膨張部を設置する工程を有することを特徴とする請求項９または１０記載の半導体装置の製造方法。   In order to determine the distance from the surface on which the semiconductor element is mounted, the low thermal expansion portion has a step of installing the low thermal expansion portion on a plurality of protrusions provided on the bottom surface of the mold having the same height. A method for manufacturing a semiconductor device according to claim 9 or 10. 前記低熱膨張部の前記鋳型中の水平位置を決めるべく、前記鋳型の底面に設けられた複数の突起に前記低熱膨張部を接触させる工程を有すること特徴とする請求項９乃至１１のいずれか記載の製造方法。   12. The method according to claim 9, further comprising a step of bringing the low thermal expansion portion into contact with a plurality of protrusions provided on a bottom surface of the mold in order to determine a horizontal position of the low thermal expansion portion in the mold. Manufacturing method. 前記低熱膨張部の前記半導体素子を搭載する面からの距離と前記鋳型中の水平位置を決めるべく、前記鋳型の底面に設けられた、高さの揃った切り欠きをもった複数の突起に前記低熱膨張部を接触させるとともに、前記切り欠きに前記低熱膨張部を設置する工程を有することを特徴とする請求項９乃至１２のいずれか記載の製造方法。   In order to determine the distance from the surface on which the semiconductor element is mounted of the low thermal expansion portion and the horizontal position in the mold, a plurality of protrusions having notches of uniform height provided on the bottom surface of the mold The manufacturing method according to claim 9, further comprising a step of bringing the low thermal expansion portion into contact with the low thermal expansion portion and installing the low thermal expansion portion in the notch. 前記低熱膨張部の前記半導体素子を搭載する面からの距離を決めるべく、一主面に複数の足を有する前記低熱膨張部を、前記鋳型の底部の然るべき位置に設置する工程を有することを特徴とする請求項９乃至１３のいずれか記載の製造方法。   In order to determine the distance from the surface on which the semiconductor element is mounted, the low thermal expansion portion has a step of installing the low thermal expansion portion having a plurality of legs on one main surface at an appropriate position on the bottom of the mold. The manufacturing method according to any one of claims 9 to 13. 前記低熱膨張部の前記鋳型中の水平位置を決めるべく前記低熱膨張部から伸びた複数の足の少なくとも一部を前記鋳型の側面に接触させる工程を有することを特徴とする請求項９乃至１４のいずれか記載の製造方法。   15. The method according to claim 9, further comprising a step of contacting at least a part of a plurality of legs extending from the low thermal expansion portion with a side surface of the mold to determine a horizontal position of the low thermal expansion portion in the mold. Any manufacturing method. 前記低熱膨張部の前記半導体素子を搭載する面からの距離と前記鋳型中の水平位置を決めるべく、前記低熱膨張部から斜めに伸びた複数の足を、前記鋳型の隅部もしくは鋳型に穿たれた凹型領域の隅部に接触させる工程を有することを特徴とする請求項９乃至１５のいずれか記載の製造方法。   In order to determine the distance from the surface on which the semiconductor element is mounted of the low thermal expansion portion and the horizontal position in the mold, a plurality of legs extending obliquely from the low thermal expansion portion are formed in corners of the mold or the mold. The manufacturing method according to claim 9, further comprising a step of contacting a corner of the concave region. 前記鋳型の淵に設けられた段差に、前記絶縁板を設置する工程を有することを特徴とする請求項９乃至１６のいずれか記載の製造方法。   The manufacturing method according to any one of claims 9 to 16, further comprising a step of installing the insulating plate at a step provided on a ridge of the mold.
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